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xed-iform-enum.h File Reference
#include "xed-common-hdrs.h"
#include "xed-iclass-enum.h"

Macros

#define XED_IFORM_AAA_DEFINED   1
 
#define XED_IFORM_AAD_IMMb_DEFINED   1
 
#define XED_IFORM_AADD_MEM32_GPR32_DEFINED   1
 
#define XED_IFORM_AADD_MEM64_GPR64_DEFINED   1
 
#define XED_IFORM_AADD_MEMi32_GPR32i32_APX_DEFINED   1
 
#define XED_IFORM_AADD_MEMi64_GPR64i64_APX_DEFINED   1
 
#define XED_IFORM_AAM_IMMb_DEFINED   1
 
#define XED_IFORM_AAND_MEM32_GPR32_DEFINED   1
 
#define XED_IFORM_AAND_MEM64_GPR64_DEFINED   1
 
#define XED_IFORM_AAND_MEMi32_GPR32i32_APX_DEFINED   1
 
#define XED_IFORM_AAND_MEMi64_GPR64i64_APX_DEFINED   1
 
#define XED_IFORM_AAS_DEFINED   1
 
#define XED_IFORM_ADC_AL_IMMb_DEFINED   1
 
#define XED_IFORM_ADC_GPR8_GPR8_10_DEFINED   1
 
#define XED_IFORM_ADC_GPR8_GPR8_12_DEFINED   1
 
#define XED_IFORM_ADC_GPR8_IMMb_80r2_DEFINED   1
 
#define XED_IFORM_ADC_GPR8_IMMb_82r2_DEFINED   1
 
#define XED_IFORM_ADC_GPR8_MEMb_DEFINED   1
 
#define XED_IFORM_ADC_GPR8i8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_ADC_GPR8i8_GPR8i8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_ADC_GPR8i8_GPR8i8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ADC_GPR8i8_GPR8i8_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_ADC_GPR8i8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ADC_GPR8i8_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_ADC_GPR8i8_MEMi8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_ADC_GPR8i8_MEMi8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ADC_GPRv_GPRv_11_DEFINED   1
 
#define XED_IFORM_ADC_GPRv_GPRv_13_DEFINED   1
 
#define XED_IFORM_ADC_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_ADC_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_ADC_GPRv_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ADC_GPRv_GPRv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_ADC_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_ADC_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ADC_GPRv_IMMb_DEFINED   1
 
#define XED_IFORM_ADC_GPRv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_ADC_GPRv_IMMz_DEFINED   1
 
#define XED_IFORM_ADC_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_ADC_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_ADC_GPRv_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_ADC_GPRv_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ADC_GPRv_MEMv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_ADC_LOCK_MEMb_GPR8_DEFINED   1
 
#define XED_IFORM_ADC_LOCK_MEMb_IMMb_80r2_DEFINED   1
 
#define XED_IFORM_ADC_LOCK_MEMb_IMMb_82r2_DEFINED   1
 
#define XED_IFORM_ADC_LOCK_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_ADC_LOCK_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_ADC_LOCK_MEMv_IMMz_DEFINED   1
 
#define XED_IFORM_ADC_MEMb_GPR8_DEFINED   1
 
#define XED_IFORM_ADC_MEMb_IMMb_80r2_DEFINED   1
 
#define XED_IFORM_ADC_MEMb_IMMb_82r2_DEFINED   1
 
#define XED_IFORM_ADC_MEMi8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_ADC_MEMi8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ADC_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_ADC_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_ADC_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ADC_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_ADC_MEMv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_ADC_MEMv_IMMz_DEFINED   1
 
#define XED_IFORM_ADC_OrAX_IMMz_DEFINED   1
 
#define XED_IFORM_ADCX_GPR32d_GPR32d_DEFINED   1
 
#define XED_IFORM_ADCX_GPR32d_MEMd_DEFINED   1
 
#define XED_IFORM_ADCX_GPR32i32_GPR32i32_APX_DEFINED   1
 
#define XED_IFORM_ADCX_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED   1
 
#define XED_IFORM_ADCX_GPR32i32_GPR32i32_MEMi32_APX_DEFINED   1
 
#define XED_IFORM_ADCX_GPR32i32_MEMi32_APX_DEFINED   1
 
#define XED_IFORM_ADCX_GPR64i64_GPR64i64_APX_DEFINED   1
 
#define XED_IFORM_ADCX_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED   1
 
#define XED_IFORM_ADCX_GPR64i64_GPR64i64_MEMi64_APX_DEFINED   1
 
#define XED_IFORM_ADCX_GPR64i64_MEMi64_APX_DEFINED   1
 
#define XED_IFORM_ADCX_GPR64q_GPR64q_DEFINED   1
 
#define XED_IFORM_ADCX_GPR64q_MEMq_DEFINED   1
 
#define XED_IFORM_ADD_AL_IMMb_DEFINED   1
 
#define XED_IFORM_ADD_GPR8_GPR8_00_DEFINED   1
 
#define XED_IFORM_ADD_GPR8_GPR8_02_DEFINED   1
 
#define XED_IFORM_ADD_GPR8_IMMb_80r0_DEFINED   1
 
#define XED_IFORM_ADD_GPR8_IMMb_82r0_DEFINED   1
 
#define XED_IFORM_ADD_GPR8_MEMb_DEFINED   1
 
#define XED_IFORM_ADD_GPR8i8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_ADD_GPR8i8_GPR8i8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_ADD_GPR8i8_GPR8i8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ADD_GPR8i8_GPR8i8_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_ADD_GPR8i8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ADD_GPR8i8_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_ADD_GPR8i8_MEMi8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_ADD_GPR8i8_MEMi8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ADD_GPRv_GPRv_01_DEFINED   1
 
#define XED_IFORM_ADD_GPRv_GPRv_03_DEFINED   1
 
#define XED_IFORM_ADD_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_ADD_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_ADD_GPRv_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ADD_GPRv_GPRv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_ADD_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_ADD_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ADD_GPRv_IMMb_DEFINED   1
 
#define XED_IFORM_ADD_GPRv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_ADD_GPRv_IMMz_DEFINED   1
 
#define XED_IFORM_ADD_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_ADD_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_ADD_GPRv_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_ADD_GPRv_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ADD_GPRv_MEMv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_ADD_LOCK_MEMb_GPR8_DEFINED   1
 
#define XED_IFORM_ADD_LOCK_MEMb_IMMb_80r0_DEFINED   1
 
#define XED_IFORM_ADD_LOCK_MEMb_IMMb_82r0_DEFINED   1
 
#define XED_IFORM_ADD_LOCK_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_ADD_LOCK_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_ADD_LOCK_MEMv_IMMz_DEFINED   1
 
#define XED_IFORM_ADD_MEMb_GPR8_DEFINED   1
 
#define XED_IFORM_ADD_MEMb_IMMb_80r0_DEFINED   1
 
#define XED_IFORM_ADD_MEMb_IMMb_82r0_DEFINED   1
 
#define XED_IFORM_ADD_MEMi8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_ADD_MEMi8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ADD_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_ADD_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_ADD_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ADD_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_ADD_MEMv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_ADD_MEMv_IMMz_DEFINED   1
 
#define XED_IFORM_ADD_OrAX_IMMz_DEFINED   1
 
#define XED_IFORM_ADDPD_XMMpd_MEMpd_DEFINED   1
 
#define XED_IFORM_ADDPD_XMMpd_XMMpd_DEFINED   1
 
#define XED_IFORM_ADDPS_XMMps_MEMps_DEFINED   1
 
#define XED_IFORM_ADDPS_XMMps_XMMps_DEFINED   1
 
#define XED_IFORM_ADDSD_XMMsd_MEMsd_DEFINED   1
 
#define XED_IFORM_ADDSD_XMMsd_XMMsd_DEFINED   1
 
#define XED_IFORM_ADDSS_XMMss_MEMss_DEFINED   1
 
#define XED_IFORM_ADDSS_XMMss_XMMss_DEFINED   1
 
#define XED_IFORM_ADDSUBPD_XMMpd_MEMpd_DEFINED   1
 
#define XED_IFORM_ADDSUBPD_XMMpd_XMMpd_DEFINED   1
 
#define XED_IFORM_ADDSUBPS_XMMps_MEMps_DEFINED   1
 
#define XED_IFORM_ADDSUBPS_XMMps_XMMps_DEFINED   1
 
#define XED_IFORM_ADOX_GPR32d_GPR32d_DEFINED   1
 
#define XED_IFORM_ADOX_GPR32d_MEMd_DEFINED   1
 
#define XED_IFORM_ADOX_GPR32i32_GPR32i32_APX_DEFINED   1
 
#define XED_IFORM_ADOX_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED   1
 
#define XED_IFORM_ADOX_GPR32i32_GPR32i32_MEMi32_APX_DEFINED   1
 
#define XED_IFORM_ADOX_GPR32i32_MEMi32_APX_DEFINED   1
 
#define XED_IFORM_ADOX_GPR64i64_GPR64i64_APX_DEFINED   1
 
#define XED_IFORM_ADOX_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED   1
 
#define XED_IFORM_ADOX_GPR64i64_GPR64i64_MEMi64_APX_DEFINED   1
 
#define XED_IFORM_ADOX_GPR64i64_MEMi64_APX_DEFINED   1
 
#define XED_IFORM_ADOX_GPR64q_GPR64q_DEFINED   1
 
#define XED_IFORM_ADOX_GPR64q_MEMq_DEFINED   1
 
#define XED_IFORM_AESDEC128KL_XMMu8_MEMu8_DEFINED   1
 
#define XED_IFORM_AESDEC256KL_XMMu8_MEMu8_DEFINED   1
 
#define XED_IFORM_AESDEC_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_AESDEC_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_AESDECLAST_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_AESDECLAST_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_AESDECWIDE128KL_MEMu8_DEFINED   1
 
#define XED_IFORM_AESDECWIDE256KL_MEMu8_DEFINED   1
 
#define XED_IFORM_AESENC128KL_XMMu8_MEMu8_DEFINED   1
 
#define XED_IFORM_AESENC256KL_XMMu8_MEMu8_DEFINED   1
 
#define XED_IFORM_AESENC_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_AESENC_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_AESENCLAST_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_AESENCLAST_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_AESENCWIDE128KL_MEMu8_DEFINED   1
 
#define XED_IFORM_AESENCWIDE256KL_MEMu8_DEFINED   1
 
#define XED_IFORM_AESIMC_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_AESIMC_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_AESKEYGENASSIST_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_AESKEYGENASSIST_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_AND_AL_IMMb_DEFINED   1
 
#define XED_IFORM_AND_GPR8_GPR8_20_DEFINED   1
 
#define XED_IFORM_AND_GPR8_GPR8_22_DEFINED   1
 
#define XED_IFORM_AND_GPR8_IMMb_80r4_DEFINED   1
 
#define XED_IFORM_AND_GPR8_IMMb_82r4_DEFINED   1
 
#define XED_IFORM_AND_GPR8_MEMb_DEFINED   1
 
#define XED_IFORM_AND_GPR8i8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_AND_GPR8i8_GPR8i8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_AND_GPR8i8_GPR8i8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_AND_GPR8i8_GPR8i8_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_AND_GPR8i8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_AND_GPR8i8_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_AND_GPR8i8_MEMi8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_AND_GPR8i8_MEMi8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_AND_GPRv_GPRv_21_DEFINED   1
 
#define XED_IFORM_AND_GPRv_GPRv_23_DEFINED   1
 
#define XED_IFORM_AND_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_AND_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_AND_GPRv_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_AND_GPRv_GPRv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_AND_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_AND_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_AND_GPRv_IMMb_DEFINED   1
 
#define XED_IFORM_AND_GPRv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_AND_GPRv_IMMz_DEFINED   1
 
#define XED_IFORM_AND_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_AND_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_AND_GPRv_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_AND_GPRv_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_AND_GPRv_MEMv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_AND_LOCK_MEMb_GPR8_DEFINED   1
 
#define XED_IFORM_AND_LOCK_MEMb_IMMb_80r4_DEFINED   1
 
#define XED_IFORM_AND_LOCK_MEMb_IMMb_82r4_DEFINED   1
 
#define XED_IFORM_AND_LOCK_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_AND_LOCK_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_AND_LOCK_MEMv_IMMz_DEFINED   1
 
#define XED_IFORM_AND_MEMb_GPR8_DEFINED   1
 
#define XED_IFORM_AND_MEMb_IMMb_80r4_DEFINED   1
 
#define XED_IFORM_AND_MEMb_IMMb_82r4_DEFINED   1
 
#define XED_IFORM_AND_MEMi8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_AND_MEMi8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_AND_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_AND_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_AND_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_AND_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_AND_MEMv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_AND_MEMv_IMMz_DEFINED   1
 
#define XED_IFORM_AND_OrAX_IMMz_DEFINED   1
 
#define XED_IFORM_ANDN_GPR32d_GPR32d_GPR32d_DEFINED   1
 
#define XED_IFORM_ANDN_GPR32d_GPR32d_MEMd_DEFINED   1
 
#define XED_IFORM_ANDN_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED   1
 
#define XED_IFORM_ANDN_GPR32i32_GPR32i32_MEMi32_APX_DEFINED   1
 
#define XED_IFORM_ANDN_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED   1
 
#define XED_IFORM_ANDN_GPR64i64_GPR64i64_MEMi64_APX_DEFINED   1
 
#define XED_IFORM_ANDN_GPR64q_GPR64q_GPR64q_DEFINED   1
 
#define XED_IFORM_ANDN_GPR64q_GPR64q_MEMq_DEFINED   1
 
#define XED_IFORM_ANDNPD_XMMxuq_MEMxuq_DEFINED   1
 
#define XED_IFORM_ANDNPD_XMMxuq_XMMxuq_DEFINED   1
 
#define XED_IFORM_ANDNPS_XMMxud_MEMxud_DEFINED   1
 
#define XED_IFORM_ANDNPS_XMMxud_XMMxud_DEFINED   1
 
#define XED_IFORM_ANDPD_XMMxuq_MEMxuq_DEFINED   1
 
#define XED_IFORM_ANDPD_XMMxuq_XMMxuq_DEFINED   1
 
#define XED_IFORM_ANDPS_XMMxud_MEMxud_DEFINED   1
 
#define XED_IFORM_ANDPS_XMMxud_XMMxud_DEFINED   1
 
#define XED_IFORM_AOR_MEM32_GPR32_DEFINED   1
 
#define XED_IFORM_AOR_MEM64_GPR64_DEFINED   1
 
#define XED_IFORM_AOR_MEMi32_GPR32i32_APX_DEFINED   1
 
#define XED_IFORM_AOR_MEMi64_GPR64i64_APX_DEFINED   1
 
#define XED_IFORM_ARPL_GPR16_GPR16_DEFINED   1
 
#define XED_IFORM_ARPL_MEMw_GPR16_DEFINED   1
 
#define XED_IFORM_AXOR_MEM32_GPR32_DEFINED   1
 
#define XED_IFORM_AXOR_MEM64_GPR64_DEFINED   1
 
#define XED_IFORM_AXOR_MEMi32_GPR32i32_APX_DEFINED   1
 
#define XED_IFORM_AXOR_MEMi64_GPR64i64_APX_DEFINED   1
 
#define XED_IFORM_BEXTR_GPR32d_GPR32d_GPR32d_DEFINED   1
 
#define XED_IFORM_BEXTR_GPR32d_MEMd_GPR32d_DEFINED   1
 
#define XED_IFORM_BEXTR_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED   1
 
#define XED_IFORM_BEXTR_GPR32i32_MEMi32_GPR32i32_APX_DEFINED   1
 
#define XED_IFORM_BEXTR_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED   1
 
#define XED_IFORM_BEXTR_GPR64i64_MEMi64_GPR64i64_APX_DEFINED   1
 
#define XED_IFORM_BEXTR_GPR64q_GPR64q_GPR64q_DEFINED   1
 
#define XED_IFORM_BEXTR_GPR64q_MEMq_GPR64q_DEFINED   1
 
#define XED_IFORM_BEXTR_XOP_GPR32d_GPR32d_IMMd_DEFINED   1
 
#define XED_IFORM_BEXTR_XOP_GPR32d_MEMd_IMMd_DEFINED   1
 
#define XED_IFORM_BEXTR_XOP_GPRyy_GPRyy_IMMd_DEFINED   1
 
#define XED_IFORM_BEXTR_XOP_GPRyy_MEMy_IMMd_DEFINED   1
 
#define XED_IFORM_BLCFILL_GPR32d_GPR32d_DEFINED   1
 
#define XED_IFORM_BLCFILL_GPR32d_MEMd_DEFINED   1
 
#define XED_IFORM_BLCFILL_GPRyy_GPRyy_DEFINED   1
 
#define XED_IFORM_BLCFILL_GPRyy_MEMy_DEFINED   1
 
#define XED_IFORM_BLCI_GPR32d_GPR32d_DEFINED   1
 
#define XED_IFORM_BLCI_GPR32d_MEMd_DEFINED   1
 
#define XED_IFORM_BLCI_GPRyy_GPRyy_DEFINED   1
 
#define XED_IFORM_BLCI_GPRyy_MEMy_DEFINED   1
 
#define XED_IFORM_BLCIC_GPR32d_GPR32d_DEFINED   1
 
#define XED_IFORM_BLCIC_GPR32d_MEMd_DEFINED   1
 
#define XED_IFORM_BLCIC_GPRyy_GPRyy_DEFINED   1
 
#define XED_IFORM_BLCIC_GPRyy_MEMy_DEFINED   1
 
#define XED_IFORM_BLCMSK_GPR32d_GPR32d_DEFINED   1
 
#define XED_IFORM_BLCMSK_GPR32d_MEMd_DEFINED   1
 
#define XED_IFORM_BLCMSK_GPRyy_GPRyy_DEFINED   1
 
#define XED_IFORM_BLCMSK_GPRyy_MEMy_DEFINED   1
 
#define XED_IFORM_BLCS_GPR32d_GPR32d_DEFINED   1
 
#define XED_IFORM_BLCS_GPR32d_MEMd_DEFINED   1
 
#define XED_IFORM_BLCS_GPRyy_GPRyy_DEFINED   1
 
#define XED_IFORM_BLCS_GPRyy_MEMy_DEFINED   1
 
#define XED_IFORM_BLENDPD_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_BLENDPD_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_BLENDPS_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_BLENDPS_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_BLENDVPD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_BLENDVPD_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_BLENDVPS_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_BLENDVPS_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_BLSFILL_GPR32d_GPR32d_DEFINED   1
 
#define XED_IFORM_BLSFILL_GPR32d_MEMd_DEFINED   1
 
#define XED_IFORM_BLSFILL_GPRyy_GPRyy_DEFINED   1
 
#define XED_IFORM_BLSFILL_GPRyy_MEMy_DEFINED   1
 
#define XED_IFORM_BLSI_GPR32d_GPR32d_DEFINED   1
 
#define XED_IFORM_BLSI_GPR32d_MEMd_DEFINED   1
 
#define XED_IFORM_BLSI_GPR32i32_GPR32i32_APX_DEFINED   1
 
#define XED_IFORM_BLSI_GPR32i32_MEMi32_APX_DEFINED   1
 
#define XED_IFORM_BLSI_GPR64i64_GPR64i64_APX_DEFINED   1
 
#define XED_IFORM_BLSI_GPR64i64_MEMi64_APX_DEFINED   1
 
#define XED_IFORM_BLSI_GPR64q_GPR64q_DEFINED   1
 
#define XED_IFORM_BLSI_GPR64q_MEMq_DEFINED   1
 
#define XED_IFORM_BLSIC_GPR32d_GPR32d_DEFINED   1
 
#define XED_IFORM_BLSIC_GPR32d_MEMd_DEFINED   1
 
#define XED_IFORM_BLSIC_GPRyy_GPRyy_DEFINED   1
 
#define XED_IFORM_BLSIC_GPRyy_MEMy_DEFINED   1
 
#define XED_IFORM_BLSMSK_GPR32d_GPR32d_DEFINED   1
 
#define XED_IFORM_BLSMSK_GPR32d_MEMd_DEFINED   1
 
#define XED_IFORM_BLSMSK_GPR32i32_GPR32i32_APX_DEFINED   1
 
#define XED_IFORM_BLSMSK_GPR32i32_MEMi32_APX_DEFINED   1
 
#define XED_IFORM_BLSMSK_GPR64i64_GPR64i64_APX_DEFINED   1
 
#define XED_IFORM_BLSMSK_GPR64i64_MEMi64_APX_DEFINED   1
 
#define XED_IFORM_BLSMSK_GPR64q_GPR64q_DEFINED   1
 
#define XED_IFORM_BLSMSK_GPR64q_MEMq_DEFINED   1
 
#define XED_IFORM_BLSR_GPR32d_GPR32d_DEFINED   1
 
#define XED_IFORM_BLSR_GPR32d_MEMd_DEFINED   1
 
#define XED_IFORM_BLSR_GPR32i32_GPR32i32_APX_DEFINED   1
 
#define XED_IFORM_BLSR_GPR32i32_MEMi32_APX_DEFINED   1
 
#define XED_IFORM_BLSR_GPR64i64_GPR64i64_APX_DEFINED   1
 
#define XED_IFORM_BLSR_GPR64i64_MEMi64_APX_DEFINED   1
 
#define XED_IFORM_BLSR_GPR64q_GPR64q_DEFINED   1
 
#define XED_IFORM_BLSR_GPR64q_MEMq_DEFINED   1
 
#define XED_IFORM_BNDCL_BND_AGEN_DEFINED   1
 
#define XED_IFORM_BNDCL_BND_GPR32_DEFINED   1
 
#define XED_IFORM_BNDCL_BND_GPR64_DEFINED   1
 
#define XED_IFORM_BNDCN_BND_AGEN_DEFINED   1
 
#define XED_IFORM_BNDCN_BND_GPR32_DEFINED   1
 
#define XED_IFORM_BNDCN_BND_GPR64_DEFINED   1
 
#define XED_IFORM_BNDCU_BND_AGEN_DEFINED   1
 
#define XED_IFORM_BNDCU_BND_GPR32_DEFINED   1
 
#define XED_IFORM_BNDCU_BND_GPR64_DEFINED   1
 
#define XED_IFORM_BNDLDX_BND_MEMbnd32_DEFINED   1
 
#define XED_IFORM_BNDLDX_BND_MEMbnd64_DEFINED   1
 
#define XED_IFORM_BNDMK_BND_AGEN_DEFINED   1
 
#define XED_IFORM_BNDMOV_BND_BND_DEFINED   1
 
#define XED_IFORM_BNDMOV_BND_MEMdq_DEFINED   1
 
#define XED_IFORM_BNDMOV_BND_MEMq_DEFINED   1
 
#define XED_IFORM_BNDMOV_MEMdq_BND_DEFINED   1
 
#define XED_IFORM_BNDMOV_MEMq_BND_DEFINED   1
 
#define XED_IFORM_BNDSTX_MEMbnd32_BND_DEFINED   1
 
#define XED_IFORM_BNDSTX_MEMbnd64_BND_DEFINED   1
 
#define XED_IFORM_BOUND_GPR16_MEMa16_DEFINED   1
 
#define XED_IFORM_BOUND_GPR32_MEMa32_DEFINED   1
 
#define XED_IFORM_BSF_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_BSF_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_BSR_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_BSR_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_BSWAP_GPRv_DEFINED   1
 
#define XED_IFORM_BT_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_BT_GPRv_IMMb_DEFINED   1
 
#define XED_IFORM_BT_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_BT_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_BTC_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_BTC_GPRv_IMMb_DEFINED   1
 
#define XED_IFORM_BTC_LOCK_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_BTC_LOCK_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_BTC_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_BTC_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_BTR_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_BTR_GPRv_IMMb_DEFINED   1
 
#define XED_IFORM_BTR_LOCK_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_BTR_LOCK_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_BTR_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_BTR_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_BTS_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_BTS_GPRv_IMMb_DEFINED   1
 
#define XED_IFORM_BTS_LOCK_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_BTS_LOCK_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_BTS_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_BTS_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_BZHI_GPR32d_GPR32d_GPR32d_DEFINED   1
 
#define XED_IFORM_BZHI_GPR32d_MEMd_GPR32d_DEFINED   1
 
#define XED_IFORM_BZHI_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED   1
 
#define XED_IFORM_BZHI_GPR32i32_MEMi32_GPR32i32_APX_DEFINED   1
 
#define XED_IFORM_BZHI_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED   1
 
#define XED_IFORM_BZHI_GPR64i64_MEMi64_GPR64i64_APX_DEFINED   1
 
#define XED_IFORM_BZHI_GPR64q_GPR64q_GPR64q_DEFINED   1
 
#define XED_IFORM_BZHI_GPR64q_MEMq_GPR64q_DEFINED   1
 
#define XED_IFORM_CALL_FAR_MEMp2_DEFINED   1
 
#define XED_IFORM_CALL_FAR_PTRp_IMMw_DEFINED   1
 
#define XED_IFORM_CALL_NEAR_GPRv_DEFINED   1
 
#define XED_IFORM_CALL_NEAR_MEMv_DEFINED   1
 
#define XED_IFORM_CALL_NEAR_RELBRd_DEFINED   1
 
#define XED_IFORM_CALL_NEAR_RELBRz_DEFINED   1
 
#define XED_IFORM_CBW_DEFINED   1
 
#define XED_IFORM_CCMPB_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPB_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPB_GPR8i8_MEMi8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPB_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPB_GPRv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPB_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPB_GPRv_MEMv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPB_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPB_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPB_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPB_MEMv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPB_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPBE_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPBE_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPBE_GPR8i8_MEMi8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPBE_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPBE_GPRv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPBE_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPBE_GPRv_MEMv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPBE_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPBE_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPBE_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPBE_MEMv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPBE_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPF_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPF_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPF_GPR8i8_MEMi8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPF_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPF_GPRv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPF_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPF_GPRv_MEMv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPF_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPF_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPF_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPF_MEMv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPF_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPL_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPL_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPL_GPR8i8_MEMi8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPL_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPL_GPRv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPL_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPL_GPRv_MEMv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPL_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPL_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPL_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPL_MEMv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPL_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPLE_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPLE_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPLE_GPR8i8_MEMi8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPLE_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPLE_GPRv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPLE_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPLE_GPRv_MEMv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPLE_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPLE_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPLE_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPLE_MEMv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPLE_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNB_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNB_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNB_GPR8i8_MEMi8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNB_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNB_GPRv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNB_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNB_GPRv_MEMv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNB_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNB_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNB_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNB_MEMv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNB_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNBE_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNBE_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNBE_GPR8i8_MEMi8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNBE_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNBE_GPRv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNBE_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNBE_GPRv_MEMv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNBE_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNBE_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNBE_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNBE_MEMv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNBE_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNL_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNL_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNL_GPR8i8_MEMi8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNL_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNL_GPRv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNL_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNL_GPRv_MEMv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNL_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNL_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNL_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNL_MEMv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNL_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNLE_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNLE_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNLE_GPR8i8_MEMi8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNLE_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNLE_GPRv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNLE_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNLE_GPRv_MEMv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNLE_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNLE_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNLE_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNLE_MEMv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNLE_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNO_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNO_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNO_GPR8i8_MEMi8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNO_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNO_GPRv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNO_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNO_GPRv_MEMv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNO_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNO_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNO_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNO_MEMv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNO_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNS_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNS_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNS_GPR8i8_MEMi8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNS_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNS_GPRv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNS_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNS_GPRv_MEMv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNS_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNS_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNS_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNS_MEMv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNS_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNZ_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNZ_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNZ_GPR8i8_MEMi8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNZ_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNZ_GPRv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNZ_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNZ_GPRv_MEMv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNZ_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNZ_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNZ_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNZ_MEMv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPNZ_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPO_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPO_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPO_GPR8i8_MEMi8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPO_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPO_GPRv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPO_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPO_GPRv_MEMv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPO_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPO_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPO_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPO_MEMv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPO_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPS_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPS_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPS_GPR8i8_MEMi8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPS_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPS_GPRv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPS_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPS_GPRv_MEMv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPS_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPS_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPS_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPS_MEMv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPS_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPT_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPT_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPT_GPR8i8_MEMi8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPT_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPT_GPRv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPT_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPT_GPRv_MEMv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPT_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPT_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPT_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPT_MEMv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPT_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPZ_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPZ_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPZ_GPR8i8_MEMi8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPZ_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPZ_GPRv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPZ_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPZ_GPRv_MEMv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPZ_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPZ_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPZ_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPZ_MEMv_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CCMPZ_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CDQ_DEFINED   1
 
#define XED_IFORM_CDQE_DEFINED   1
 
#define XED_IFORM_CFCMOVB_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVB_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVB_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVB_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVB_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVBE_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVBE_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVBE_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVBE_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVBE_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVL_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVL_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVL_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVL_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVL_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVLE_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVLE_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVLE_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVLE_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVLE_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNB_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNB_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNB_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNB_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNB_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNBE_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNBE_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNBE_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNBE_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNBE_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNL_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNL_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNL_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNL_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNL_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNLE_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNLE_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNLE_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNLE_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNLE_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNO_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNO_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNO_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNO_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNO_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNP_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNP_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNP_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNP_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNP_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNS_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNS_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNS_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNS_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNS_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNZ_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNZ_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNZ_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNZ_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVNZ_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVO_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVO_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVO_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVO_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVO_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVP_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVP_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVP_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVP_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVP_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVS_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVS_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVS_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVS_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVS_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVZ_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVZ_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVZ_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVZ_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CFCMOVZ_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CLAC_DEFINED   1
 
#define XED_IFORM_CLC_DEFINED   1
 
#define XED_IFORM_CLD_DEFINED   1
 
#define XED_IFORM_CLDEMOTE_MEMu8_DEFINED   1
 
#define XED_IFORM_CLFLUSH_MEMmprefetch_DEFINED   1
 
#define XED_IFORM_CLFLUSHOPT_MEMmprefetch_DEFINED   1
 
#define XED_IFORM_CLGI_DEFINED   1
 
#define XED_IFORM_CLI_DEFINED   1
 
#define XED_IFORM_CLRSSBSY_MEMu64_DEFINED   1
 
#define XED_IFORM_CLTS_DEFINED   1
 
#define XED_IFORM_CLUI_DEFINED   1
 
#define XED_IFORM_CLWB_MEMmprefetch_DEFINED   1
 
#define XED_IFORM_CLZERO_DEFINED   1
 
#define XED_IFORM_CMC_DEFINED   1
 
#define XED_IFORM_CMOVB_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_CMOVB_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CMOVB_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CMOVB_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_CMOVBE_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_CMOVBE_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CMOVBE_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CMOVBE_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_CMOVL_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_CMOVL_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CMOVL_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CMOVL_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_CMOVLE_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_CMOVLE_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CMOVLE_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CMOVLE_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_CMOVNB_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_CMOVNB_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CMOVNB_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CMOVNB_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_CMOVNBE_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_CMOVNBE_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CMOVNBE_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CMOVNBE_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_CMOVNL_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_CMOVNL_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CMOVNL_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CMOVNL_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_CMOVNLE_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_CMOVNLE_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CMOVNLE_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CMOVNLE_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_CMOVNO_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_CMOVNO_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CMOVNO_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CMOVNO_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_CMOVNP_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_CMOVNP_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CMOVNP_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CMOVNP_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_CMOVNS_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_CMOVNS_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CMOVNS_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CMOVNS_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_CMOVNZ_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_CMOVNZ_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CMOVNZ_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CMOVNZ_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_CMOVO_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_CMOVO_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CMOVO_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CMOVO_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_CMOVP_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_CMOVP_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CMOVP_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CMOVP_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_CMOVS_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_CMOVS_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CMOVS_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CMOVS_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_CMOVZ_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_CMOVZ_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CMOVZ_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CMOVZ_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_CMP_AL_IMMb_DEFINED   1
 
#define XED_IFORM_CMP_GPR8_GPR8_38_DEFINED   1
 
#define XED_IFORM_CMP_GPR8_GPR8_3A_DEFINED   1
 
#define XED_IFORM_CMP_GPR8_IMMb_80r7_DEFINED   1
 
#define XED_IFORM_CMP_GPR8_IMMb_82r7_DEFINED   1
 
#define XED_IFORM_CMP_GPR8_MEMb_DEFINED   1
 
#define XED_IFORM_CMP_GPRv_GPRv_39_DEFINED   1
 
#define XED_IFORM_CMP_GPRv_GPRv_3B_DEFINED   1
 
#define XED_IFORM_CMP_GPRv_IMMb_DEFINED   1
 
#define XED_IFORM_CMP_GPRv_IMMz_DEFINED   1
 
#define XED_IFORM_CMP_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_CMP_MEMb_GPR8_DEFINED   1
 
#define XED_IFORM_CMP_MEMb_IMMb_80r7_DEFINED   1
 
#define XED_IFORM_CMP_MEMb_IMMb_82r7_DEFINED   1
 
#define XED_IFORM_CMP_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_CMP_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_CMP_MEMv_IMMz_DEFINED   1
 
#define XED_IFORM_CMP_OrAX_IMMz_DEFINED   1
 
#define XED_IFORM_CMPBEXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1
 
#define XED_IFORM_CMPBEXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1
 
#define XED_IFORM_CMPBEXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1
 
#define XED_IFORM_CMPBEXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1
 
#define XED_IFORM_CMPBXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1
 
#define XED_IFORM_CMPBXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1
 
#define XED_IFORM_CMPBXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1
 
#define XED_IFORM_CMPBXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1
 
#define XED_IFORM_CMPLEXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1
 
#define XED_IFORM_CMPLEXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1
 
#define XED_IFORM_CMPLEXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1
 
#define XED_IFORM_CMPLEXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1
 
#define XED_IFORM_CMPLXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1
 
#define XED_IFORM_CMPLXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1
 
#define XED_IFORM_CMPLXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1
 
#define XED_IFORM_CMPLXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1
 
#define XED_IFORM_CMPNBEXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1
 
#define XED_IFORM_CMPNBEXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1
 
#define XED_IFORM_CMPNBEXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1
 
#define XED_IFORM_CMPNBEXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1
 
#define XED_IFORM_CMPNBXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1
 
#define XED_IFORM_CMPNBXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1
 
#define XED_IFORM_CMPNBXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1
 
#define XED_IFORM_CMPNBXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1
 
#define XED_IFORM_CMPNLEXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1
 
#define XED_IFORM_CMPNLEXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1
 
#define XED_IFORM_CMPNLEXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1
 
#define XED_IFORM_CMPNLEXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1
 
#define XED_IFORM_CMPNLXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1
 
#define XED_IFORM_CMPNLXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1
 
#define XED_IFORM_CMPNLXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1
 
#define XED_IFORM_CMPNLXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1
 
#define XED_IFORM_CMPNOXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1
 
#define XED_IFORM_CMPNOXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1
 
#define XED_IFORM_CMPNOXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1
 
#define XED_IFORM_CMPNOXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1
 
#define XED_IFORM_CMPNPXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1
 
#define XED_IFORM_CMPNPXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1
 
#define XED_IFORM_CMPNPXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1
 
#define XED_IFORM_CMPNPXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1
 
#define XED_IFORM_CMPNSXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1
 
#define XED_IFORM_CMPNSXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1
 
#define XED_IFORM_CMPNSXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1
 
#define XED_IFORM_CMPNSXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1
 
#define XED_IFORM_CMPNZXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1
 
#define XED_IFORM_CMPNZXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1
 
#define XED_IFORM_CMPNZXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1
 
#define XED_IFORM_CMPNZXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1
 
#define XED_IFORM_CMPOXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1
 
#define XED_IFORM_CMPOXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1
 
#define XED_IFORM_CMPOXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1
 
#define XED_IFORM_CMPOXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1
 
#define XED_IFORM_CMPPD_XMMpd_MEMpd_IMMb_DEFINED   1
 
#define XED_IFORM_CMPPD_XMMpd_XMMpd_IMMb_DEFINED   1
 
#define XED_IFORM_CMPPS_XMMps_MEMps_IMMb_DEFINED   1
 
#define XED_IFORM_CMPPS_XMMps_XMMps_IMMb_DEFINED   1
 
#define XED_IFORM_CMPPXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1
 
#define XED_IFORM_CMPPXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1
 
#define XED_IFORM_CMPPXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1
 
#define XED_IFORM_CMPPXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1
 
#define XED_IFORM_CMPSB_DEFINED   1
 
#define XED_IFORM_CMPSD_DEFINED   1
 
#define XED_IFORM_CMPSD_XMM_XMMsd_MEMsd_IMMb_DEFINED   1
 
#define XED_IFORM_CMPSD_XMM_XMMsd_XMMsd_IMMb_DEFINED   1
 
#define XED_IFORM_CMPSQ_DEFINED   1
 
#define XED_IFORM_CMPSS_XMMss_MEMss_IMMb_DEFINED   1
 
#define XED_IFORM_CMPSS_XMMss_XMMss_IMMb_DEFINED   1
 
#define XED_IFORM_CMPSW_DEFINED   1
 
#define XED_IFORM_CMPSXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1
 
#define XED_IFORM_CMPSXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1
 
#define XED_IFORM_CMPSXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1
 
#define XED_IFORM_CMPSXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1
 
#define XED_IFORM_CMPXCHG16B_LOCK_MEMdq_DEFINED   1
 
#define XED_IFORM_CMPXCHG16B_MEMdq_DEFINED   1
 
#define XED_IFORM_CMPXCHG8B_LOCK_MEMq_DEFINED   1
 
#define XED_IFORM_CMPXCHG8B_MEMq_DEFINED   1
 
#define XED_IFORM_CMPXCHG_GPR8_GPR8_DEFINED   1
 
#define XED_IFORM_CMPXCHG_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_CMPXCHG_LOCK_MEMb_GPR8_DEFINED   1
 
#define XED_IFORM_CMPXCHG_LOCK_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_CMPXCHG_MEMb_GPR8_DEFINED   1
 
#define XED_IFORM_CMPXCHG_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_CMPZXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1
 
#define XED_IFORM_CMPZXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1
 
#define XED_IFORM_CMPZXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1
 
#define XED_IFORM_CMPZXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1
 
#define XED_IFORM_COMISD_XMMsd_MEMsd_DEFINED   1
 
#define XED_IFORM_COMISD_XMMsd_XMMsd_DEFINED   1
 
#define XED_IFORM_COMISS_XMMss_MEMss_DEFINED   1
 
#define XED_IFORM_COMISS_XMMss_XMMss_DEFINED   1
 
#define XED_IFORM_CPUID_DEFINED   1
 
#define XED_IFORM_CQO_DEFINED   1
 
#define XED_IFORM_CRC32_GPRy_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_CRC32_GPRy_GPRv_APX_DEFINED   1
 
#define XED_IFORM_CRC32_GPRy_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_CRC32_GPRy_MEMv_APX_DEFINED   1
 
#define XED_IFORM_CRC32_GPRyy_GPR8b_DEFINED   1
 
#define XED_IFORM_CRC32_GPRyy_GPRv_DEFINED   1
 
#define XED_IFORM_CRC32_GPRyy_MEMb_DEFINED   1
 
#define XED_IFORM_CRC32_GPRyy_MEMv_DEFINED   1
 
#define XED_IFORM_CTESTB_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTB_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTB_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTB_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTB_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTB_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTB_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTB_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTBE_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTBE_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTBE_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTBE_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTBE_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTBE_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTBE_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTBE_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTF_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTF_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTF_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTF_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTF_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTF_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTF_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTF_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTL_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTL_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTL_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTL_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTL_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTL_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTL_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTL_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTLE_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTLE_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTLE_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTLE_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTLE_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTLE_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTLE_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTLE_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNB_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNB_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNB_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNB_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNB_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNB_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNB_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNB_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNBE_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNBE_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNBE_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNBE_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNBE_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNBE_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNBE_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNBE_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNL_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNL_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNL_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNL_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNL_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNL_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNL_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNL_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNLE_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNLE_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNLE_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNLE_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNLE_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNLE_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNLE_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNLE_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNO_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNO_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNO_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNO_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNO_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNO_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNO_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNO_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNS_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNS_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNS_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNS_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNS_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNS_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNS_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNS_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNZ_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNZ_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNZ_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNZ_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNZ_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNZ_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNZ_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTNZ_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTO_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTO_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTO_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTO_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTO_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTO_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTO_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTO_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTS_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTS_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTS_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTS_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTS_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTS_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTS_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTS_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTT_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTT_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTT_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTT_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTT_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTT_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTT_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTT_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTZ_GPR8i8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTZ_GPR8i8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTZ_GPRv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTZ_GPRv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTZ_MEMi8_GPR8i8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTZ_MEMi8_IMM8_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTZ_MEMv_GPRv_DFV_APX_DEFINED   1
 
#define XED_IFORM_CTESTZ_MEMv_IMMz_DFV_APX_DEFINED   1
 
#define XED_IFORM_CVTDQ2PD_XMMpd_MEMq_DEFINED   1
 
#define XED_IFORM_CVTDQ2PD_XMMpd_XMMq_DEFINED   1
 
#define XED_IFORM_CVTDQ2PS_XMMps_MEMdq_DEFINED   1
 
#define XED_IFORM_CVTDQ2PS_XMMps_XMMdq_DEFINED   1
 
#define XED_IFORM_CVTPD2DQ_XMMdq_MEMpd_DEFINED   1
 
#define XED_IFORM_CVTPD2DQ_XMMdq_XMMpd_DEFINED   1
 
#define XED_IFORM_CVTPD2PI_MMXq_MEMpd_DEFINED   1
 
#define XED_IFORM_CVTPD2PI_MMXq_XMMpd_DEFINED   1
 
#define XED_IFORM_CVTPD2PS_XMMps_MEMpd_DEFINED   1
 
#define XED_IFORM_CVTPD2PS_XMMps_XMMpd_DEFINED   1
 
#define XED_IFORM_CVTPI2PD_XMMpd_MEMq_DEFINED   1
 
#define XED_IFORM_CVTPI2PD_XMMpd_MMXq_DEFINED   1
 
#define XED_IFORM_CVTPI2PS_XMMq_MEMq_DEFINED   1
 
#define XED_IFORM_CVTPI2PS_XMMq_MMXq_DEFINED   1
 
#define XED_IFORM_CVTPS2DQ_XMMdq_MEMps_DEFINED   1
 
#define XED_IFORM_CVTPS2DQ_XMMdq_XMMps_DEFINED   1
 
#define XED_IFORM_CVTPS2PD_XMMpd_MEMq_DEFINED   1
 
#define XED_IFORM_CVTPS2PD_XMMpd_XMMq_DEFINED   1
 
#define XED_IFORM_CVTPS2PI_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_CVTPS2PI_MMXq_XMMq_DEFINED   1
 
#define XED_IFORM_CVTSD2SI_GPR32d_MEMsd_DEFINED   1
 
#define XED_IFORM_CVTSD2SI_GPR32d_XMMsd_DEFINED   1
 
#define XED_IFORM_CVTSD2SI_GPR64q_MEMsd_DEFINED   1
 
#define XED_IFORM_CVTSD2SI_GPR64q_XMMsd_DEFINED   1
 
#define XED_IFORM_CVTSD2SS_XMMss_MEMsd_DEFINED   1
 
#define XED_IFORM_CVTSD2SS_XMMss_XMMsd_DEFINED   1
 
#define XED_IFORM_CVTSI2SD_XMMsd_GPR32d_DEFINED   1
 
#define XED_IFORM_CVTSI2SD_XMMsd_GPR64q_DEFINED   1
 
#define XED_IFORM_CVTSI2SD_XMMsd_MEMd_DEFINED   1
 
#define XED_IFORM_CVTSI2SD_XMMsd_MEMq_DEFINED   1
 
#define XED_IFORM_CVTSI2SS_XMMss_GPR32d_DEFINED   1
 
#define XED_IFORM_CVTSI2SS_XMMss_GPR64q_DEFINED   1
 
#define XED_IFORM_CVTSI2SS_XMMss_MEMd_DEFINED   1
 
#define XED_IFORM_CVTSI2SS_XMMss_MEMq_DEFINED   1
 
#define XED_IFORM_CVTSS2SD_XMMsd_MEMss_DEFINED   1
 
#define XED_IFORM_CVTSS2SD_XMMsd_XMMss_DEFINED   1
 
#define XED_IFORM_CVTSS2SI_GPR32d_MEMss_DEFINED   1
 
#define XED_IFORM_CVTSS2SI_GPR32d_XMMss_DEFINED   1
 
#define XED_IFORM_CVTSS2SI_GPR64q_MEMss_DEFINED   1
 
#define XED_IFORM_CVTSS2SI_GPR64q_XMMss_DEFINED   1
 
#define XED_IFORM_CVTTPD2DQ_XMMdq_MEMpd_DEFINED   1
 
#define XED_IFORM_CVTTPD2DQ_XMMdq_XMMpd_DEFINED   1
 
#define XED_IFORM_CVTTPD2PI_MMXq_MEMpd_DEFINED   1
 
#define XED_IFORM_CVTTPD2PI_MMXq_XMMpd_DEFINED   1
 
#define XED_IFORM_CVTTPS2DQ_XMMdq_MEMps_DEFINED   1
 
#define XED_IFORM_CVTTPS2DQ_XMMdq_XMMps_DEFINED   1
 
#define XED_IFORM_CVTTPS2PI_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_CVTTPS2PI_MMXq_XMMq_DEFINED   1
 
#define XED_IFORM_CVTTSD2SI_GPR32d_MEMsd_DEFINED   1
 
#define XED_IFORM_CVTTSD2SI_GPR32d_XMMsd_DEFINED   1
 
#define XED_IFORM_CVTTSD2SI_GPR64q_MEMsd_DEFINED   1
 
#define XED_IFORM_CVTTSD2SI_GPR64q_XMMsd_DEFINED   1
 
#define XED_IFORM_CVTTSS2SI_GPR32d_MEMss_DEFINED   1
 
#define XED_IFORM_CVTTSS2SI_GPR32d_XMMss_DEFINED   1
 
#define XED_IFORM_CVTTSS2SI_GPR64q_MEMss_DEFINED   1
 
#define XED_IFORM_CVTTSS2SI_GPR64q_XMMss_DEFINED   1
 
#define XED_IFORM_CWD_DEFINED   1
 
#define XED_IFORM_CWDE_DEFINED   1
 
#define XED_IFORM_DAA_DEFINED   1
 
#define XED_IFORM_DAS_DEFINED   1
 
#define XED_IFORM_DEC_GPR8_DEFINED   1
 
#define XED_IFORM_DEC_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_DEC_GPR8i8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_DEC_GPR8i8_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_DEC_GPRv_48_DEFINED   1
 
#define XED_IFORM_DEC_GPRv_APX_DEFINED   1
 
#define XED_IFORM_DEC_GPRv_FFr1_DEFINED   1
 
#define XED_IFORM_DEC_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_DEC_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_DEC_LOCK_MEMb_DEFINED   1
 
#define XED_IFORM_DEC_LOCK_MEMv_DEFINED   1
 
#define XED_IFORM_DEC_MEMb_DEFINED   1
 
#define XED_IFORM_DEC_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_DEC_MEMv_APX_DEFINED   1
 
#define XED_IFORM_DEC_MEMv_DEFINED   1
 
#define XED_IFORM_DIV_GPR8_DEFINED   1
 
#define XED_IFORM_DIV_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_DIV_GPRv_APX_DEFINED   1
 
#define XED_IFORM_DIV_GPRv_DEFINED   1
 
#define XED_IFORM_DIV_MEMb_DEFINED   1
 
#define XED_IFORM_DIV_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_DIV_MEMv_APX_DEFINED   1
 
#define XED_IFORM_DIV_MEMv_DEFINED   1
 
#define XED_IFORM_DIVPD_XMMpd_MEMpd_DEFINED   1
 
#define XED_IFORM_DIVPD_XMMpd_XMMpd_DEFINED   1
 
#define XED_IFORM_DIVPS_XMMps_MEMps_DEFINED   1
 
#define XED_IFORM_DIVPS_XMMps_XMMps_DEFINED   1
 
#define XED_IFORM_DIVSD_XMMsd_MEMsd_DEFINED   1
 
#define XED_IFORM_DIVSD_XMMsd_XMMsd_DEFINED   1
 
#define XED_IFORM_DIVSS_XMMss_MEMss_DEFINED   1
 
#define XED_IFORM_DIVSS_XMMss_XMMss_DEFINED   1
 
#define XED_IFORM_DPPD_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_DPPD_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_DPPS_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_DPPS_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_EMMS_DEFINED   1
 
#define XED_IFORM_ENCLS_DEFINED   1
 
#define XED_IFORM_ENCLU_DEFINED   1
 
#define XED_IFORM_ENCLV_DEFINED   1
 
#define XED_IFORM_ENCODEKEY128_GPR32u8_GPR32u8_DEFINED   1
 
#define XED_IFORM_ENCODEKEY256_GPR32u8_GPR32u8_DEFINED   1
 
#define XED_IFORM_ENDBR32_DEFINED   1
 
#define XED_IFORM_ENDBR64_DEFINED   1
 
#define XED_IFORM_ENQCMD_GPRa_MEMu32_DEFINED   1
 
#define XED_IFORM_ENQCMD_GPRav_MEMu32_APX_DEFINED   1
 
#define XED_IFORM_ENQCMDS_GPRa_MEMu32_DEFINED   1
 
#define XED_IFORM_ENQCMDS_GPRav_MEMu32_APX_DEFINED   1
 
#define XED_IFORM_ENTER_IMMw_IMMb_DEFINED   1
 
#define XED_IFORM_ERETS_DEFINED   1
 
#define XED_IFORM_ERETU_DEFINED   1
 
#define XED_IFORM_EXTRACTPS_GPR32d_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_EXTRACTPS_MEMd_XMMps_IMMb_DEFINED   1
 
#define XED_IFORM_EXTRQ_XMMq_IMMb_IMMb_DEFINED   1
 
#define XED_IFORM_EXTRQ_XMMq_XMMdq_DEFINED   1
 
#define XED_IFORM_F2XM1_DEFINED   1
 
#define XED_IFORM_FABS_DEFINED   1
 
#define XED_IFORM_FADD_MEMm64real_DEFINED   1
 
#define XED_IFORM_FADD_MEMmem32real_DEFINED   1
 
#define XED_IFORM_FADD_ST0_X87_DEFINED   1
 
#define XED_IFORM_FADD_X87_ST0_DEFINED   1
 
#define XED_IFORM_FADDP_X87_ST0_DEFINED   1
 
#define XED_IFORM_FBLD_ST0_MEMmem80dec_DEFINED   1
 
#define XED_IFORM_FBSTP_MEMmem80dec_ST0_DEFINED   1
 
#define XED_IFORM_FCHS_DEFINED   1
 
#define XED_IFORM_FCMOVB_ST0_X87_DEFINED   1
 
#define XED_IFORM_FCMOVBE_ST0_X87_DEFINED   1
 
#define XED_IFORM_FCMOVE_ST0_X87_DEFINED   1
 
#define XED_IFORM_FCMOVNB_ST0_X87_DEFINED   1
 
#define XED_IFORM_FCMOVNBE_ST0_X87_DEFINED   1
 
#define XED_IFORM_FCMOVNE_ST0_X87_DEFINED   1
 
#define XED_IFORM_FCMOVNU_ST0_X87_DEFINED   1
 
#define XED_IFORM_FCMOVU_ST0_X87_DEFINED   1
 
#define XED_IFORM_FCOM_ST0_MEMm64real_DEFINED   1
 
#define XED_IFORM_FCOM_ST0_MEMmem32real_DEFINED   1
 
#define XED_IFORM_FCOM_ST0_X87_DCD0_DEFINED   1
 
#define XED_IFORM_FCOM_ST0_X87_DEFINED   1
 
#define XED_IFORM_FCOMI_ST0_X87_DEFINED   1
 
#define XED_IFORM_FCOMIP_ST0_X87_DEFINED   1
 
#define XED_IFORM_FCOMP_ST0_MEMm64real_DEFINED   1
 
#define XED_IFORM_FCOMP_ST0_MEMmem32real_DEFINED   1
 
#define XED_IFORM_FCOMP_ST0_X87_DCD1_DEFINED   1
 
#define XED_IFORM_FCOMP_ST0_X87_DED0_DEFINED   1
 
#define XED_IFORM_FCOMP_ST0_X87_DEFINED   1
 
#define XED_IFORM_FCOMPP_DEFINED   1
 
#define XED_IFORM_FCOS_DEFINED   1
 
#define XED_IFORM_FDECSTP_DEFINED   1
 
#define XED_IFORM_FDISI8087_NOP_DEFINED   1
 
#define XED_IFORM_FDIV_ST0_MEMm64real_DEFINED   1
 
#define XED_IFORM_FDIV_ST0_MEMmem32real_DEFINED   1
 
#define XED_IFORM_FDIV_ST0_X87_DEFINED   1
 
#define XED_IFORM_FDIV_X87_ST0_DEFINED   1
 
#define XED_IFORM_FDIVP_X87_ST0_DEFINED   1
 
#define XED_IFORM_FDIVR_ST0_MEMm64real_DEFINED   1
 
#define XED_IFORM_FDIVR_ST0_MEMmem32real_DEFINED   1
 
#define XED_IFORM_FDIVR_ST0_X87_DEFINED   1
 
#define XED_IFORM_FDIVR_X87_ST0_DEFINED   1
 
#define XED_IFORM_FDIVRP_X87_ST0_DEFINED   1
 
#define XED_IFORM_FEMMS_DEFINED   1
 
#define XED_IFORM_FENI8087_NOP_DEFINED   1
 
#define XED_IFORM_FFREE_X87_DEFINED   1
 
#define XED_IFORM_FFREEP_X87_DEFINED   1
 
#define XED_IFORM_FIADD_ST0_MEMmem16int_DEFINED   1
 
#define XED_IFORM_FIADD_ST0_MEMmem32int_DEFINED   1
 
#define XED_IFORM_FICOM_ST0_MEMmem16int_DEFINED   1
 
#define XED_IFORM_FICOM_ST0_MEMmem32int_DEFINED   1
 
#define XED_IFORM_FICOMP_ST0_MEMmem16int_DEFINED   1
 
#define XED_IFORM_FICOMP_ST0_MEMmem32int_DEFINED   1
 
#define XED_IFORM_FIDIV_ST0_MEMmem16int_DEFINED   1
 
#define XED_IFORM_FIDIV_ST0_MEMmem32int_DEFINED   1
 
#define XED_IFORM_FIDIVR_ST0_MEMmem16int_DEFINED   1
 
#define XED_IFORM_FIDIVR_ST0_MEMmem32int_DEFINED   1
 
#define XED_IFORM_FILD_ST0_MEMm64int_DEFINED   1
 
#define XED_IFORM_FILD_ST0_MEMmem16int_DEFINED   1
 
#define XED_IFORM_FILD_ST0_MEMmem32int_DEFINED   1
 
#define XED_IFORM_FIMUL_ST0_MEMmem16int_DEFINED   1
 
#define XED_IFORM_FIMUL_ST0_MEMmem32int_DEFINED   1
 
#define XED_IFORM_FINCSTP_DEFINED   1
 
#define XED_IFORM_FIST_MEMmem16int_ST0_DEFINED   1
 
#define XED_IFORM_FIST_MEMmem32int_ST0_DEFINED   1
 
#define XED_IFORM_FISTP_MEMm64int_ST0_DEFINED   1
 
#define XED_IFORM_FISTP_MEMmem16int_ST0_DEFINED   1
 
#define XED_IFORM_FISTP_MEMmem32int_ST0_DEFINED   1
 
#define XED_IFORM_FISTTP_MEMm64int_ST0_DEFINED   1
 
#define XED_IFORM_FISTTP_MEMmem16int_ST0_DEFINED   1
 
#define XED_IFORM_FISTTP_MEMmem32int_ST0_DEFINED   1
 
#define XED_IFORM_FISUB_ST0_MEMmem16int_DEFINED   1
 
#define XED_IFORM_FISUB_ST0_MEMmem32int_DEFINED   1
 
#define XED_IFORM_FISUBR_ST0_MEMmem16int_DEFINED   1
 
#define XED_IFORM_FISUBR_ST0_MEMmem32int_DEFINED   1
 
#define XED_IFORM_FLD1_DEFINED   1
 
#define XED_IFORM_FLD_ST0_MEMm64real_DEFINED   1
 
#define XED_IFORM_FLD_ST0_MEMmem32real_DEFINED   1
 
#define XED_IFORM_FLD_ST0_MEMmem80real_DEFINED   1
 
#define XED_IFORM_FLD_ST0_X87_DEFINED   1
 
#define XED_IFORM_FLDCW_MEMmem16_DEFINED   1
 
#define XED_IFORM_FLDENV_MEMmem14_DEFINED   1
 
#define XED_IFORM_FLDENV_MEMmem28_DEFINED   1
 
#define XED_IFORM_FLDL2E_DEFINED   1
 
#define XED_IFORM_FLDL2T_DEFINED   1
 
#define XED_IFORM_FLDLG2_DEFINED   1
 
#define XED_IFORM_FLDLN2_DEFINED   1
 
#define XED_IFORM_FLDPI_DEFINED   1
 
#define XED_IFORM_FLDZ_DEFINED   1
 
#define XED_IFORM_FMUL_ST0_MEMm64real_DEFINED   1
 
#define XED_IFORM_FMUL_ST0_MEMmem32real_DEFINED   1
 
#define XED_IFORM_FMUL_ST0_X87_DEFINED   1
 
#define XED_IFORM_FMUL_X87_ST0_DEFINED   1
 
#define XED_IFORM_FMULP_X87_ST0_DEFINED   1
 
#define XED_IFORM_FNCLEX_DEFINED   1
 
#define XED_IFORM_FNINIT_DEFINED   1
 
#define XED_IFORM_FNOP_DEFINED   1
 
#define XED_IFORM_FNSAVE_MEMmem108_DEFINED   1
 
#define XED_IFORM_FNSAVE_MEMmem94_DEFINED   1
 
#define XED_IFORM_FNSTCW_MEMmem16_DEFINED   1
 
#define XED_IFORM_FNSTENV_MEMmem14_DEFINED   1
 
#define XED_IFORM_FNSTENV_MEMmem28_DEFINED   1
 
#define XED_IFORM_FNSTSW_AX_DEFINED   1
 
#define XED_IFORM_FNSTSW_MEMmem16_DEFINED   1
 
#define XED_IFORM_FPATAN_DEFINED   1
 
#define XED_IFORM_FPREM1_DEFINED   1
 
#define XED_IFORM_FPREM_DEFINED   1
 
#define XED_IFORM_FPTAN_DEFINED   1
 
#define XED_IFORM_FRNDINT_DEFINED   1
 
#define XED_IFORM_FRSTOR_MEMmem108_DEFINED   1
 
#define XED_IFORM_FRSTOR_MEMmem94_DEFINED   1
 
#define XED_IFORM_FSCALE_DEFINED   1
 
#define XED_IFORM_FSETPM287_NOP_DEFINED   1
 
#define XED_IFORM_FSIN_DEFINED   1
 
#define XED_IFORM_FSINCOS_DEFINED   1
 
#define XED_IFORM_FSQRT_DEFINED   1
 
#define XED_IFORM_FST_MEMm64real_ST0_DEFINED   1
 
#define XED_IFORM_FST_MEMmem32real_ST0_DEFINED   1
 
#define XED_IFORM_FST_X87_ST0_DEFINED   1
 
#define XED_IFORM_FSTP_MEMm64real_ST0_DEFINED   1
 
#define XED_IFORM_FSTP_MEMmem32real_ST0_DEFINED   1
 
#define XED_IFORM_FSTP_MEMmem80real_ST0_DEFINED   1
 
#define XED_IFORM_FSTP_X87_ST0_DEFINED   1
 
#define XED_IFORM_FSTP_X87_ST0_DFD0_DEFINED   1
 
#define XED_IFORM_FSTP_X87_ST0_DFD1_DEFINED   1
 
#define XED_IFORM_FSTPNCE_X87_ST0_DEFINED   1
 
#define XED_IFORM_FSUB_ST0_MEMm64real_DEFINED   1
 
#define XED_IFORM_FSUB_ST0_MEMmem32real_DEFINED   1
 
#define XED_IFORM_FSUB_ST0_X87_DEFINED   1
 
#define XED_IFORM_FSUB_X87_ST0_DEFINED   1
 
#define XED_IFORM_FSUBP_X87_ST0_DEFINED   1
 
#define XED_IFORM_FSUBR_ST0_MEMm64real_DEFINED   1
 
#define XED_IFORM_FSUBR_ST0_MEMmem32real_DEFINED   1
 
#define XED_IFORM_FSUBR_ST0_X87_DEFINED   1
 
#define XED_IFORM_FSUBR_X87_ST0_DEFINED   1
 
#define XED_IFORM_FSUBRP_X87_ST0_DEFINED   1
 
#define XED_IFORM_FTST_DEFINED   1
 
#define XED_IFORM_FUCOM_ST0_X87_DEFINED   1
 
#define XED_IFORM_FUCOMI_ST0_X87_DEFINED   1
 
#define XED_IFORM_FUCOMIP_ST0_X87_DEFINED   1
 
#define XED_IFORM_FUCOMP_ST0_X87_DEFINED   1
 
#define XED_IFORM_FUCOMPP_DEFINED   1
 
#define XED_IFORM_FWAIT_DEFINED   1
 
#define XED_IFORM_FXAM_DEFINED   1
 
#define XED_IFORM_FXCH_ST0_X87_DDC1_DEFINED   1
 
#define XED_IFORM_FXCH_ST0_X87_DEFINED   1
 
#define XED_IFORM_FXCH_ST0_X87_DFC1_DEFINED   1
 
#define XED_IFORM_FXRSTOR64_MEMmfpxenv_DEFINED   1
 
#define XED_IFORM_FXRSTOR_MEMmfpxenv_DEFINED   1
 
#define XED_IFORM_FXSAVE64_MEMmfpxenv_DEFINED   1
 
#define XED_IFORM_FXSAVE_MEMmfpxenv_DEFINED   1
 
#define XED_IFORM_FXTRACT_DEFINED   1
 
#define XED_IFORM_FYL2X_DEFINED   1
 
#define XED_IFORM_FYL2XP1_DEFINED   1
 
#define XED_IFORM_GETSEC_DEFINED   1
 
#define XED_IFORM_GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8_DEFINED   1
 
#define XED_IFORM_GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8_DEFINED   1
 
#define XED_IFORM_GF2P8AFFINEQB_XMMu8_MEMu64_IMM8_DEFINED   1
 
#define XED_IFORM_GF2P8AFFINEQB_XMMu8_XMMu64_IMM8_DEFINED   1
 
#define XED_IFORM_GF2P8MULB_XMMu8_MEMu8_DEFINED   1
 
#define XED_IFORM_GF2P8MULB_XMMu8_XMMu8_DEFINED   1
 
#define XED_IFORM_HADDPD_XMMpd_MEMpd_DEFINED   1
 
#define XED_IFORM_HADDPD_XMMpd_XMMpd_DEFINED   1
 
#define XED_IFORM_HADDPS_XMMps_MEMps_DEFINED   1
 
#define XED_IFORM_HADDPS_XMMps_XMMps_DEFINED   1
 
#define XED_IFORM_HLT_DEFINED   1
 
#define XED_IFORM_HRESET_IMM8_DEFINED   1
 
#define XED_IFORM_HSUBPD_XMMpd_MEMpd_DEFINED   1
 
#define XED_IFORM_HSUBPD_XMMpd_XMMpd_DEFINED   1
 
#define XED_IFORM_HSUBPS_XMMps_MEMps_DEFINED   1
 
#define XED_IFORM_HSUBPS_XMMps_XMMps_DEFINED   1
 
#define XED_IFORM_IDIV_GPR8_DEFINED   1
 
#define XED_IFORM_IDIV_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_IDIV_GPRv_APX_DEFINED   1
 
#define XED_IFORM_IDIV_GPRv_DEFINED   1
 
#define XED_IFORM_IDIV_MEMb_DEFINED   1
 
#define XED_IFORM_IDIV_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_IDIV_MEMv_APX_DEFINED   1
 
#define XED_IFORM_IDIV_MEMv_DEFINED   1
 
#define XED_IFORM_IMUL_GPR8_DEFINED   1
 
#define XED_IFORM_IMUL_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_IMUL_GPRv_APX_DEFINED   1
 
#define XED_IFORM_IMUL_GPRv_DEFINED   1
 
#define XED_IFORM_IMUL_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_IMUL_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_IMUL_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_IMUL_GPRv_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_IMUL_GPRv_GPRv_IMM8_APX_ZU_DEFINED   1
 
#define XED_IFORM_IMUL_GPRv_GPRv_IMMb_DEFINED   1
 
#define XED_IFORM_IMUL_GPRv_GPRv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_IMUL_GPRv_GPRv_IMMz_APX_ZU_DEFINED   1
 
#define XED_IFORM_IMUL_GPRv_GPRv_IMMz_DEFINED   1
 
#define XED_IFORM_IMUL_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_IMUL_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_IMUL_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_IMUL_GPRv_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_IMUL_GPRv_MEMv_IMM8_APX_ZU_DEFINED   1
 
#define XED_IFORM_IMUL_GPRv_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_IMUL_GPRv_MEMv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_IMUL_GPRv_MEMv_IMMz_APX_ZU_DEFINED   1
 
#define XED_IFORM_IMUL_GPRv_MEMv_IMMz_DEFINED   1
 
#define XED_IFORM_IMUL_MEMb_DEFINED   1
 
#define XED_IFORM_IMUL_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_IMUL_MEMv_APX_DEFINED   1
 
#define XED_IFORM_IMUL_MEMv_DEFINED   1
 
#define XED_IFORM_IN_AL_DX_DEFINED   1
 
#define XED_IFORM_IN_AL_IMMb_DEFINED   1
 
#define XED_IFORM_IN_OeAX_DX_DEFINED   1
 
#define XED_IFORM_IN_OeAX_IMMb_DEFINED   1
 
#define XED_IFORM_INC_GPR8_DEFINED   1
 
#define XED_IFORM_INC_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_INC_GPR8i8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_INC_GPR8i8_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_INC_GPRv_40_DEFINED   1
 
#define XED_IFORM_INC_GPRv_APX_DEFINED   1
 
#define XED_IFORM_INC_GPRv_FFr0_DEFINED   1
 
#define XED_IFORM_INC_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_INC_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_INC_LOCK_MEMb_DEFINED   1
 
#define XED_IFORM_INC_LOCK_MEMv_DEFINED   1
 
#define XED_IFORM_INC_MEMb_DEFINED   1
 
#define XED_IFORM_INC_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_INC_MEMv_APX_DEFINED   1
 
#define XED_IFORM_INC_MEMv_DEFINED   1
 
#define XED_IFORM_INCSSPD_GPR32u8_DEFINED   1
 
#define XED_IFORM_INCSSPQ_GPR64u8_DEFINED   1
 
#define XED_IFORM_INSB_DEFINED   1
 
#define XED_IFORM_INSD_DEFINED   1
 
#define XED_IFORM_INSERTPS_XMMps_MEMd_IMMb_DEFINED   1
 
#define XED_IFORM_INSERTPS_XMMps_XMMps_IMMb_DEFINED   1
 
#define XED_IFORM_INSERTQ_XMMq_XMMdq_DEFINED   1
 
#define XED_IFORM_INSERTQ_XMMq_XMMq_IMMb_IMMb_DEFINED   1
 
#define XED_IFORM_INSW_DEFINED   1
 
#define XED_IFORM_INT1_DEFINED   1
 
#define XED_IFORM_INT3_DEFINED   1
 
#define XED_IFORM_INT_IMMb_DEFINED   1
 
#define XED_IFORM_INTO_DEFINED   1
 
#define XED_IFORM_INVALID_DEFINED   1
 
#define XED_IFORM_INVD_DEFINED   1
 
#define XED_IFORM_INVEPT_GPR32_MEMdq_DEFINED   1
 
#define XED_IFORM_INVEPT_GPR64_MEMdq_DEFINED   1
 
#define XED_IFORM_INVEPT_GPR64i64_MEMi128_APX_DEFINED   1
 
#define XED_IFORM_INVLPG_MEMb_DEFINED   1
 
#define XED_IFORM_INVLPGA_ArAX_ECX_DEFINED   1
 
#define XED_IFORM_INVLPGB_DEFINED   1
 
#define XED_IFORM_INVPCID_GPR32_MEMdq_DEFINED   1
 
#define XED_IFORM_INVPCID_GPR64_MEMdq_DEFINED   1
 
#define XED_IFORM_INVPCID_GPR64i64_MEMi128_APX_DEFINED   1
 
#define XED_IFORM_INVVPID_GPR32_MEMdq_DEFINED   1
 
#define XED_IFORM_INVVPID_GPR64_MEMdq_DEFINED   1
 
#define XED_IFORM_INVVPID_GPR64i64_MEMi128_APX_DEFINED   1
 
#define XED_IFORM_IRET_DEFINED   1
 
#define XED_IFORM_IRETD_DEFINED   1
 
#define XED_IFORM_IRETQ_DEFINED   1
 
#define XED_IFORM_JB_RELBRb_DEFINED   1
 
#define XED_IFORM_JB_RELBRd_DEFINED   1
 
#define XED_IFORM_JB_RELBRz_DEFINED   1
 
#define XED_IFORM_JBE_RELBRb_DEFINED   1
 
#define XED_IFORM_JBE_RELBRd_DEFINED   1
 
#define XED_IFORM_JBE_RELBRz_DEFINED   1
 
#define XED_IFORM_JCXZ_RELBRb_DEFINED   1
 
#define XED_IFORM_JECXZ_RELBRb_DEFINED   1
 
#define XED_IFORM_JL_RELBRb_DEFINED   1
 
#define XED_IFORM_JL_RELBRd_DEFINED   1
 
#define XED_IFORM_JL_RELBRz_DEFINED   1
 
#define XED_IFORM_JLE_RELBRb_DEFINED   1
 
#define XED_IFORM_JLE_RELBRd_DEFINED   1
 
#define XED_IFORM_JLE_RELBRz_DEFINED   1
 
#define XED_IFORM_JMP_FAR_MEMp2_DEFINED   1
 
#define XED_IFORM_JMP_FAR_PTRp_IMMw_DEFINED   1
 
#define XED_IFORM_JMP_GPRv_DEFINED   1
 
#define XED_IFORM_JMP_MEMv_DEFINED   1
 
#define XED_IFORM_JMP_RELBRb_DEFINED   1
 
#define XED_IFORM_JMP_RELBRd_DEFINED   1
 
#define XED_IFORM_JMP_RELBRz_DEFINED   1
 
#define XED_IFORM_JMPABS_ABSBRu64_APX_DEFINED   1
 
#define XED_IFORM_JNB_RELBRb_DEFINED   1
 
#define XED_IFORM_JNB_RELBRd_DEFINED   1
 
#define XED_IFORM_JNB_RELBRz_DEFINED   1
 
#define XED_IFORM_JNBE_RELBRb_DEFINED   1
 
#define XED_IFORM_JNBE_RELBRd_DEFINED   1
 
#define XED_IFORM_JNBE_RELBRz_DEFINED   1
 
#define XED_IFORM_JNL_RELBRb_DEFINED   1
 
#define XED_IFORM_JNL_RELBRd_DEFINED   1
 
#define XED_IFORM_JNL_RELBRz_DEFINED   1
 
#define XED_IFORM_JNLE_RELBRb_DEFINED   1
 
#define XED_IFORM_JNLE_RELBRd_DEFINED   1
 
#define XED_IFORM_JNLE_RELBRz_DEFINED   1
 
#define XED_IFORM_JNO_RELBRb_DEFINED   1
 
#define XED_IFORM_JNO_RELBRd_DEFINED   1
 
#define XED_IFORM_JNO_RELBRz_DEFINED   1
 
#define XED_IFORM_JNP_RELBRb_DEFINED   1
 
#define XED_IFORM_JNP_RELBRd_DEFINED   1
 
#define XED_IFORM_JNP_RELBRz_DEFINED   1
 
#define XED_IFORM_JNS_RELBRb_DEFINED   1
 
#define XED_IFORM_JNS_RELBRd_DEFINED   1
 
#define XED_IFORM_JNS_RELBRz_DEFINED   1
 
#define XED_IFORM_JNZ_RELBRb_DEFINED   1
 
#define XED_IFORM_JNZ_RELBRd_DEFINED   1
 
#define XED_IFORM_JNZ_RELBRz_DEFINED   1
 
#define XED_IFORM_JO_RELBRb_DEFINED   1
 
#define XED_IFORM_JO_RELBRd_DEFINED   1
 
#define XED_IFORM_JO_RELBRz_DEFINED   1
 
#define XED_IFORM_JP_RELBRb_DEFINED   1
 
#define XED_IFORM_JP_RELBRd_DEFINED   1
 
#define XED_IFORM_JP_RELBRz_DEFINED   1
 
#define XED_IFORM_JRCXZ_RELBRb_DEFINED   1
 
#define XED_IFORM_JS_RELBRb_DEFINED   1
 
#define XED_IFORM_JS_RELBRd_DEFINED   1
 
#define XED_IFORM_JS_RELBRz_DEFINED   1
 
#define XED_IFORM_JZ_RELBRb_DEFINED   1
 
#define XED_IFORM_JZ_RELBRd_DEFINED   1
 
#define XED_IFORM_JZ_RELBRz_DEFINED   1
 
#define XED_IFORM_KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KMOVB_GPR32u32_MASKmskw_APX_DEFINED   1
 
#define XED_IFORM_KMOVB_GPR32u32_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KMOVB_MASKmskw_GPR32u32_APX_DEFINED   1
 
#define XED_IFORM_KMOVB_MASKmskw_GPR32u32_AVX512_DEFINED   1
 
#define XED_IFORM_KMOVB_MASKmskw_MASKu8_APX_DEFINED   1
 
#define XED_IFORM_KMOVB_MASKmskw_MASKu8_AVX512_DEFINED   1
 
#define XED_IFORM_KMOVB_MASKmskw_MEMu8_APX_DEFINED   1
 
#define XED_IFORM_KMOVB_MASKmskw_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_KMOVB_MEMu8_MASKmskw_APX_DEFINED   1
 
#define XED_IFORM_KMOVB_MEMu8_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KMOVD_GPR32u32_MASKmskw_APX_DEFINED   1
 
#define XED_IFORM_KMOVD_GPR32u32_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KMOVD_MASKmskw_GPR32u32_APX_DEFINED   1
 
#define XED_IFORM_KMOVD_MASKmskw_GPR32u32_AVX512_DEFINED   1
 
#define XED_IFORM_KMOVD_MASKmskw_MASKu32_APX_DEFINED   1
 
#define XED_IFORM_KMOVD_MASKmskw_MASKu32_AVX512_DEFINED   1
 
#define XED_IFORM_KMOVD_MASKmskw_MEMu32_APX_DEFINED   1
 
#define XED_IFORM_KMOVD_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_KMOVD_MEMu32_MASKmskw_APX_DEFINED   1
 
#define XED_IFORM_KMOVD_MEMu32_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KMOVQ_GPR64u64_MASKmskw_APX_DEFINED   1
 
#define XED_IFORM_KMOVQ_GPR64u64_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KMOVQ_MASKmskw_GPR64u64_APX_DEFINED   1
 
#define XED_IFORM_KMOVQ_MASKmskw_GPR64u64_AVX512_DEFINED   1
 
#define XED_IFORM_KMOVQ_MASKmskw_MASKu64_APX_DEFINED   1
 
#define XED_IFORM_KMOVQ_MASKmskw_MASKu64_AVX512_DEFINED   1
 
#define XED_IFORM_KMOVQ_MASKmskw_MEMu64_APX_DEFINED   1
 
#define XED_IFORM_KMOVQ_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_KMOVQ_MEMu64_MASKmskw_APX_DEFINED   1
 
#define XED_IFORM_KMOVQ_MEMu64_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KMOVW_GPR32u32_MASKmskw_APX_DEFINED   1
 
#define XED_IFORM_KMOVW_GPR32u32_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KMOVW_MASKmskw_GPR32u32_APX_DEFINED   1
 
#define XED_IFORM_KMOVW_MASKmskw_GPR32u32_AVX512_DEFINED   1
 
#define XED_IFORM_KMOVW_MASKmskw_MASKu16_APX_DEFINED   1
 
#define XED_IFORM_KMOVW_MASKmskw_MASKu16_AVX512_DEFINED   1
 
#define XED_IFORM_KMOVW_MASKmskw_MEMu16_APX_DEFINED   1
 
#define XED_IFORM_KMOVW_MASKmskw_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_KMOVW_MEMu16_MASKmskw_APX_DEFINED   1
 
#define XED_IFORM_KMOVW_MEMu16_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KNOTB_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KNOTD_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KNOTQ_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KNOTW_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KORB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KORD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KORTESTB_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KORTESTD_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KORTESTQ_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KORTESTW_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KORW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_KTESTB_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KTESTD_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KTESTQ_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KTESTW_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_LAHF_DEFINED   1
 
#define XED_IFORM_LAR_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_LAR_GPRv_MEMw_DEFINED   1
 
#define XED_IFORM_LAST_DEFINED   1
 
#define XED_IFORM_LDDQU_XMMpd_MEMdq_DEFINED   1
 
#define XED_IFORM_LDMXCSR_MEMd_DEFINED   1
 
#define XED_IFORM_LDS_GPRz_MEMp_DEFINED   1
 
#define XED_IFORM_LDTILECFG_MEM_APX_DEFINED   1
 
#define XED_IFORM_LDTILECFG_MEM_DEFINED   1
 
#define XED_IFORM_LEA_GPRv_AGEN_DEFINED   1
 
#define XED_IFORM_LEAVE_DEFINED   1
 
#define XED_IFORM_LES_GPRz_MEMp_DEFINED   1
 
#define XED_IFORM_LFENCE_DEFINED   1
 
#define XED_IFORM_LFS_GPRv_MEMp2_DEFINED   1
 
#define XED_IFORM_LGDT_MEMs64_DEFINED   1
 
#define XED_IFORM_LGDT_MEMs_DEFINED   1
 
#define XED_IFORM_LGS_GPRv_MEMp2_DEFINED   1
 
#define XED_IFORM_LIDT_MEMs64_DEFINED   1
 
#define XED_IFORM_LIDT_MEMs_DEFINED   1
 
#define XED_IFORM_LKGS_GPR16u16_DEFINED   1
 
#define XED_IFORM_LKGS_MEMu16_DEFINED   1
 
#define XED_IFORM_LLDT_GPR16_DEFINED   1
 
#define XED_IFORM_LLDT_MEMw_DEFINED   1
 
#define XED_IFORM_LLWPCB_GPRyy_DEFINED   1
 
#define XED_IFORM_LMSW_GPR16_DEFINED   1
 
#define XED_IFORM_LMSW_MEMw_DEFINED   1
 
#define XED_IFORM_LOADIWKEY_XMMu8_XMMu8_DEFINED   1
 
#define XED_IFORM_LODSB_DEFINED   1
 
#define XED_IFORM_LODSD_DEFINED   1
 
#define XED_IFORM_LODSQ_DEFINED   1
 
#define XED_IFORM_LODSW_DEFINED   1
 
#define XED_IFORM_LOOP_RELBRb_DEFINED   1
 
#define XED_IFORM_LOOPE_RELBRb_DEFINED   1
 
#define XED_IFORM_LOOPNE_RELBRb_DEFINED   1
 
#define XED_IFORM_LSL_GPRv_GPRz_DEFINED   1
 
#define XED_IFORM_LSL_GPRv_MEMw_DEFINED   1
 
#define XED_IFORM_LSS_GPRv_MEMp2_DEFINED   1
 
#define XED_IFORM_LTR_GPR16_DEFINED   1
 
#define XED_IFORM_LTR_MEMw_DEFINED   1
 
#define XED_IFORM_LWPINS_GPRyy_GPR32d_IMMd_DEFINED   1
 
#define XED_IFORM_LWPINS_GPRyy_MEMd_IMMd_DEFINED   1
 
#define XED_IFORM_LWPVAL_GPRyy_GPR32d_IMMd_DEFINED   1
 
#define XED_IFORM_LWPVAL_GPRyy_MEMd_IMMd_DEFINED   1
 
#define XED_IFORM_LZCNT_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_LZCNT_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_LZCNT_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_LZCNT_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_MASKMOVDQU_XMMxub_XMMxub_DEFINED   1
 
#define XED_IFORM_MASKMOVQ_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_MAXPD_XMMpd_MEMpd_DEFINED   1
 
#define XED_IFORM_MAXPD_XMMpd_XMMpd_DEFINED   1
 
#define XED_IFORM_MAXPS_XMMps_MEMps_DEFINED   1
 
#define XED_IFORM_MAXPS_XMMps_XMMps_DEFINED   1
 
#define XED_IFORM_MAXSD_XMMsd_MEMsd_DEFINED   1
 
#define XED_IFORM_MAXSD_XMMsd_XMMsd_DEFINED   1
 
#define XED_IFORM_MAXSS_XMMss_MEMss_DEFINED   1
 
#define XED_IFORM_MAXSS_XMMss_XMMss_DEFINED   1
 
#define XED_IFORM_MCOMMIT_DEFINED   1
 
#define XED_IFORM_MFENCE_DEFINED   1
 
#define XED_IFORM_MINPD_XMMpd_MEMpd_DEFINED   1
 
#define XED_IFORM_MINPD_XMMpd_XMMpd_DEFINED   1
 
#define XED_IFORM_MINPS_XMMps_MEMps_DEFINED   1
 
#define XED_IFORM_MINPS_XMMps_XMMps_DEFINED   1
 
#define XED_IFORM_MINSD_XMMsd_MEMsd_DEFINED   1
 
#define XED_IFORM_MINSD_XMMsd_XMMsd_DEFINED   1
 
#define XED_IFORM_MINSS_XMMss_MEMss_DEFINED   1
 
#define XED_IFORM_MINSS_XMMss_XMMss_DEFINED   1
 
#define XED_IFORM_MONITOR_DEFINED   1
 
#define XED_IFORM_MONITORX_DEFINED   1
 
#define XED_IFORM_MOV_AL_MEMb_DEFINED   1
 
#define XED_IFORM_MOV_CR_CR_GPR32_DEFINED   1
 
#define XED_IFORM_MOV_CR_CR_GPR64_DEFINED   1
 
#define XED_IFORM_MOV_CR_GPR32_CR_DEFINED   1
 
#define XED_IFORM_MOV_CR_GPR64_CR_DEFINED   1
 
#define XED_IFORM_MOV_DR_DR_GPR32_DEFINED   1
 
#define XED_IFORM_MOV_DR_DR_GPR64_DEFINED   1
 
#define XED_IFORM_MOV_DR_GPR32_DR_DEFINED   1
 
#define XED_IFORM_MOV_DR_GPR64_DR_DEFINED   1
 
#define XED_IFORM_MOV_GPR8_GPR8_88_DEFINED   1
 
#define XED_IFORM_MOV_GPR8_GPR8_8A_DEFINED   1
 
#define XED_IFORM_MOV_GPR8_IMMb_B0_DEFINED   1
 
#define XED_IFORM_MOV_GPR8_IMMb_C6r0_DEFINED   1
 
#define XED_IFORM_MOV_GPR8_MEMb_DEFINED   1
 
#define XED_IFORM_MOV_GPRv_GPRv_89_DEFINED   1
 
#define XED_IFORM_MOV_GPRv_GPRv_8B_DEFINED   1
 
#define XED_IFORM_MOV_GPRv_IMMv_DEFINED   1
 
#define XED_IFORM_MOV_GPRv_IMMz_DEFINED   1
 
#define XED_IFORM_MOV_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_MOV_GPRv_SEG_DEFINED   1
 
#define XED_IFORM_MOV_MEMb_AL_DEFINED   1
 
#define XED_IFORM_MOV_MEMb_GPR8_DEFINED   1
 
#define XED_IFORM_MOV_MEMb_IMMb_DEFINED   1
 
#define XED_IFORM_MOV_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_MOV_MEMv_IMMz_DEFINED   1
 
#define XED_IFORM_MOV_MEMv_OrAX_DEFINED   1
 
#define XED_IFORM_MOV_MEMw_SEG_DEFINED   1
 
#define XED_IFORM_MOV_OrAX_MEMv_DEFINED   1
 
#define XED_IFORM_MOV_SEG_GPR16_DEFINED   1
 
#define XED_IFORM_MOV_SEG_MEMw_DEFINED   1
 
#define XED_IFORM_MOVAPD_MEMpd_XMMpd_DEFINED   1
 
#define XED_IFORM_MOVAPD_XMMpd_MEMpd_DEFINED   1
 
#define XED_IFORM_MOVAPD_XMMpd_XMMpd_0F28_DEFINED   1
 
#define XED_IFORM_MOVAPD_XMMpd_XMMpd_0F29_DEFINED   1
 
#define XED_IFORM_MOVAPS_MEMps_XMMps_DEFINED   1
 
#define XED_IFORM_MOVAPS_XMMps_MEMps_DEFINED   1
 
#define XED_IFORM_MOVAPS_XMMps_XMMps_0F28_DEFINED   1
 
#define XED_IFORM_MOVAPS_XMMps_XMMps_0F29_DEFINED   1
 
#define XED_IFORM_MOVBE_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_MOVBE_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_MOVBE_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_MOVBE_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_MOVBE_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_MOVD_GPR32_MMXd_DEFINED   1
 
#define XED_IFORM_MOVD_GPR32_XMMd_DEFINED   1
 
#define XED_IFORM_MOVD_MEMd_MMXd_DEFINED   1
 
#define XED_IFORM_MOVD_MEMd_XMMd_DEFINED   1
 
#define XED_IFORM_MOVD_MMXq_GPR32_DEFINED   1
 
#define XED_IFORM_MOVD_MMXq_MEMd_DEFINED   1
 
#define XED_IFORM_MOVD_XMMdq_GPR32_DEFINED   1
 
#define XED_IFORM_MOVD_XMMdq_MEMd_DEFINED   1
 
#define XED_IFORM_MOVDDUP_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_MOVDDUP_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_MOVDIR64B_GPRa_MEM_DEFINED   1
 
#define XED_IFORM_MOVDIR64B_GPRav_MEMu32_APX_DEFINED   1
 
#define XED_IFORM_MOVDIRI_MEMu32_GPR32u32_DEFINED   1
 
#define XED_IFORM_MOVDIRI_MEMu64_GPR64u64_DEFINED   1
 
#define XED_IFORM_MOVDIRI_MEMyu_GPRyu_APX_DEFINED   1
 
#define XED_IFORM_MOVDQ2Q_MMXq_XMMq_DEFINED   1
 
#define XED_IFORM_MOVDQA_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_MOVDQA_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_MOVDQA_XMMdq_XMMdq_0F6F_DEFINED   1
 
#define XED_IFORM_MOVDQA_XMMdq_XMMdq_0F7F_DEFINED   1
 
#define XED_IFORM_MOVDQU_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_MOVDQU_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_MOVDQU_XMMdq_XMMdq_0F6F_DEFINED   1
 
#define XED_IFORM_MOVDQU_XMMdq_XMMdq_0F7F_DEFINED   1
 
#define XED_IFORM_MOVHLPS_XMMq_XMMq_DEFINED   1
 
#define XED_IFORM_MOVHPD_MEMq_XMMsd_DEFINED   1
 
#define XED_IFORM_MOVHPD_XMMsd_MEMq_DEFINED   1
 
#define XED_IFORM_MOVHPS_MEMq_XMMps_DEFINED   1
 
#define XED_IFORM_MOVHPS_XMMq_MEMq_DEFINED   1
 
#define XED_IFORM_MOVLHPS_XMMq_XMMq_DEFINED   1
 
#define XED_IFORM_MOVLPD_MEMq_XMMsd_DEFINED   1
 
#define XED_IFORM_MOVLPD_XMMsd_MEMq_DEFINED   1
 
#define XED_IFORM_MOVLPS_MEMq_XMMq_DEFINED   1
 
#define XED_IFORM_MOVLPS_XMMq_MEMq_DEFINED   1
 
#define XED_IFORM_MOVMSKPD_GPR32_XMMpd_DEFINED   1
 
#define XED_IFORM_MOVMSKPS_GPR32_XMMps_DEFINED   1
 
#define XED_IFORM_MOVNTDQ_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_MOVNTDQA_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_MOVNTI_MEMd_GPR32_DEFINED   1
 
#define XED_IFORM_MOVNTI_MEMq_GPR64_DEFINED   1
 
#define XED_IFORM_MOVNTPD_MEMdq_XMMpd_DEFINED   1
 
#define XED_IFORM_MOVNTPS_MEMdq_XMMps_DEFINED   1
 
#define XED_IFORM_MOVNTQ_MEMq_MMXq_DEFINED   1
 
#define XED_IFORM_MOVNTSD_MEMq_XMMq_DEFINED   1
 
#define XED_IFORM_MOVNTSS_MEMd_XMMd_DEFINED   1
 
#define XED_IFORM_MOVQ2DQ_XMMdq_MMXq_DEFINED   1
 
#define XED_IFORM_MOVQ_GPR64_MMXq_DEFINED   1
 
#define XED_IFORM_MOVQ_GPR64_XMMq_DEFINED   1
 
#define XED_IFORM_MOVQ_MEMq_MMXq_0F7E_DEFINED   1
 
#define XED_IFORM_MOVQ_MEMq_MMXq_0F7F_DEFINED   1
 
#define XED_IFORM_MOVQ_MEMq_XMMq_0F7E_DEFINED   1
 
#define XED_IFORM_MOVQ_MEMq_XMMq_0FD6_DEFINED   1
 
#define XED_IFORM_MOVQ_MMXq_GPR64_DEFINED   1
 
#define XED_IFORM_MOVQ_MMXq_MEMq_0F6E_DEFINED   1
 
#define XED_IFORM_MOVQ_MMXq_MEMq_0F6F_DEFINED   1
 
#define XED_IFORM_MOVQ_MMXq_MMXq_0F6F_DEFINED   1
 
#define XED_IFORM_MOVQ_MMXq_MMXq_0F7F_DEFINED   1
 
#define XED_IFORM_MOVQ_XMMdq_GPR64_DEFINED   1
 
#define XED_IFORM_MOVQ_XMMdq_MEMq_0F6E_DEFINED   1
 
#define XED_IFORM_MOVQ_XMMdq_MEMq_0F7E_DEFINED   1
 
#define XED_IFORM_MOVQ_XMMdq_XMMq_0F7E_DEFINED   1
 
#define XED_IFORM_MOVQ_XMMdq_XMMq_0FD6_DEFINED   1
 
#define XED_IFORM_MOVRS_GPR8i8_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_MOVRS_GPR8i8_MEMi8_DEFINED   1
 
#define XED_IFORM_MOVRS_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_MOVRS_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_MOVSB_DEFINED   1
 
#define XED_IFORM_MOVSD_DEFINED   1
 
#define XED_IFORM_MOVSD_XMM_MEMsd_XMMsd_DEFINED   1
 
#define XED_IFORM_MOVSD_XMM_XMMdq_MEMsd_DEFINED   1
 
#define XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F10_DEFINED   1
 
#define XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F11_DEFINED   1
 
#define XED_IFORM_MOVSHDUP_XMMps_MEMps_DEFINED   1
 
#define XED_IFORM_MOVSHDUP_XMMps_XMMps_DEFINED   1
 
#define XED_IFORM_MOVSLDUP_XMMps_MEMps_DEFINED   1
 
#define XED_IFORM_MOVSLDUP_XMMps_XMMps_DEFINED   1
 
#define XED_IFORM_MOVSQ_DEFINED   1
 
#define XED_IFORM_MOVSS_MEMss_XMMss_DEFINED   1
 
#define XED_IFORM_MOVSS_XMMdq_MEMss_DEFINED   1
 
#define XED_IFORM_MOVSS_XMMss_XMMss_0F10_DEFINED   1
 
#define XED_IFORM_MOVSS_XMMss_XMMss_0F11_DEFINED   1
 
#define XED_IFORM_MOVSW_DEFINED   1
 
#define XED_IFORM_MOVSX_GPR16_MEMw_DEFINED   1
 
#define XED_IFORM_MOVSX_GPR32_MEMw_DEFINED   1
 
#define XED_IFORM_MOVSX_GPR64_MEMw_DEFINED   1
 
#define XED_IFORM_MOVSX_GPRv_GPR16_DEFINED   1
 
#define XED_IFORM_MOVSX_GPRv_GPR8_DEFINED   1
 
#define XED_IFORM_MOVSX_GPRv_MEMb_DEFINED   1
 
#define XED_IFORM_MOVSX_GPRv_MEMw_DEFINED   1
 
#define XED_IFORM_MOVSXD_GPR64_MEMd_DEFINED   1
 
#define XED_IFORM_MOVSXD_GPRv_GPRz_DEFINED   1
 
#define XED_IFORM_MOVSXD_GPRz_MEMz_DEFINED   1
 
#define XED_IFORM_MOVUPD_MEMpd_XMMpd_DEFINED   1
 
#define XED_IFORM_MOVUPD_XMMpd_MEMpd_DEFINED   1
 
#define XED_IFORM_MOVUPD_XMMpd_XMMpd_0F10_DEFINED   1
 
#define XED_IFORM_MOVUPD_XMMpd_XMMpd_0F11_DEFINED   1
 
#define XED_IFORM_MOVUPS_MEMps_XMMps_DEFINED   1
 
#define XED_IFORM_MOVUPS_XMMps_MEMps_DEFINED   1
 
#define XED_IFORM_MOVUPS_XMMps_XMMps_0F10_DEFINED   1
 
#define XED_IFORM_MOVUPS_XMMps_XMMps_0F11_DEFINED   1
 
#define XED_IFORM_MOVZX_GPR16_MEMw_DEFINED   1
 
#define XED_IFORM_MOVZX_GPR32_MEMw_DEFINED   1
 
#define XED_IFORM_MOVZX_GPR64_MEMw_DEFINED   1
 
#define XED_IFORM_MOVZX_GPRv_GPR16_DEFINED   1
 
#define XED_IFORM_MOVZX_GPRv_GPR8_DEFINED   1
 
#define XED_IFORM_MOVZX_GPRv_MEMb_DEFINED   1
 
#define XED_IFORM_MOVZX_GPRv_MEMw_DEFINED   1
 
#define XED_IFORM_MPSADBW_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_MUL_GPR8_DEFINED   1
 
#define XED_IFORM_MUL_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_MUL_GPRv_APX_DEFINED   1
 
#define XED_IFORM_MUL_GPRv_DEFINED   1
 
#define XED_IFORM_MUL_MEMb_DEFINED   1
 
#define XED_IFORM_MUL_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_MUL_MEMv_APX_DEFINED   1
 
#define XED_IFORM_MUL_MEMv_DEFINED   1
 
#define XED_IFORM_MULPD_XMMpd_MEMpd_DEFINED   1
 
#define XED_IFORM_MULPD_XMMpd_XMMpd_DEFINED   1
 
#define XED_IFORM_MULPS_XMMps_MEMps_DEFINED   1
 
#define XED_IFORM_MULPS_XMMps_XMMps_DEFINED   1
 
#define XED_IFORM_MULSD_XMMsd_MEMsd_DEFINED   1
 
#define XED_IFORM_MULSD_XMMsd_XMMsd_DEFINED   1
 
#define XED_IFORM_MULSS_XMMss_MEMss_DEFINED   1
 
#define XED_IFORM_MULSS_XMMss_XMMss_DEFINED   1
 
#define XED_IFORM_MULX_GPR32d_GPR32d_GPR32d_DEFINED   1
 
#define XED_IFORM_MULX_GPR32d_GPR32d_MEMd_DEFINED   1
 
#define XED_IFORM_MULX_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED   1
 
#define XED_IFORM_MULX_GPR32i32_GPR32i32_MEMi32_APX_DEFINED   1
 
#define XED_IFORM_MULX_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED   1
 
#define XED_IFORM_MULX_GPR64i64_GPR64i64_MEMi64_APX_DEFINED   1
 
#define XED_IFORM_MULX_GPR64q_GPR64q_GPR64q_DEFINED   1
 
#define XED_IFORM_MULX_GPR64q_GPR64q_MEMq_DEFINED   1
 
#define XED_IFORM_MWAIT_DEFINED   1
 
#define XED_IFORM_MWAITX_DEFINED   1
 
#define XED_IFORM_NEG_GPR8_DEFINED   1
 
#define XED_IFORM_NEG_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_NEG_GPR8i8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_NEG_GPR8i8_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_NEG_GPRv_APX_DEFINED   1
 
#define XED_IFORM_NEG_GPRv_DEFINED   1
 
#define XED_IFORM_NEG_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_NEG_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_NEG_LOCK_MEMb_DEFINED   1
 
#define XED_IFORM_NEG_LOCK_MEMv_DEFINED   1
 
#define XED_IFORM_NEG_MEMb_DEFINED   1
 
#define XED_IFORM_NEG_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_NEG_MEMv_APX_DEFINED   1
 
#define XED_IFORM_NEG_MEMv_DEFINED   1
 
#define XED_IFORM_NOP_90_DEFINED   1
 
#define XED_IFORM_NOP_GPRv_0F18r0_DEFINED   1
 
#define XED_IFORM_NOP_GPRv_0F18r1_DEFINED   1
 
#define XED_IFORM_NOP_GPRv_0F18r2_DEFINED   1
 
#define XED_IFORM_NOP_GPRv_0F18r3_DEFINED   1
 
#define XED_IFORM_NOP_GPRv_0F18r4_DEFINED   1
 
#define XED_IFORM_NOP_GPRv_0F18r5_DEFINED   1
 
#define XED_IFORM_NOP_GPRv_0F18r6_DEFINED   1
 
#define XED_IFORM_NOP_GPRv_0F18r7_DEFINED   1
 
#define XED_IFORM_NOP_GPRv_0F1F_DEFINED   1
 
#define XED_IFORM_NOP_GPRv_GPRv_0F0D_DEFINED   1
 
#define XED_IFORM_NOP_GPRv_GPRv_0F19_DEFINED   1
 
#define XED_IFORM_NOP_GPRv_GPRv_0F1A_DEFINED   1
 
#define XED_IFORM_NOP_GPRv_GPRv_0F1B_DEFINED   1
 
#define XED_IFORM_NOP_GPRv_GPRv_0F1C_DEFINED   1
 
#define XED_IFORM_NOP_GPRv_GPRv_0F1D_DEFINED   1
 
#define XED_IFORM_NOP_GPRv_GPRv_0F1E_DEFINED   1
 
#define XED_IFORM_NOP_GPRv_MEM_0F1B_DEFINED   1
 
#define XED_IFORM_NOP_GPRv_MEMv_0F1A_DEFINED   1
 
#define XED_IFORM_NOP_MEMv_0F18r4_DEFINED   1
 
#define XED_IFORM_NOP_MEMv_0F18r5_DEFINED   1
 
#define XED_IFORM_NOP_MEMv_0F18r6_DEFINED   1
 
#define XED_IFORM_NOP_MEMv_0F18r7_DEFINED   1
 
#define XED_IFORM_NOP_MEMv_0F1F_DEFINED   1
 
#define XED_IFORM_NOP_MEMv_GPRv_0F19_DEFINED   1
 
#define XED_IFORM_NOP_MEMv_GPRv_0F1C_DEFINED   1
 
#define XED_IFORM_NOP_MEMv_GPRv_0F1D_DEFINED   1
 
#define XED_IFORM_NOP_MEMv_GPRv_0F1E_DEFINED   1
 
#define XED_IFORM_NOT_GPR8_DEFINED   1
 
#define XED_IFORM_NOT_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_NOT_GPR8i8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_NOT_GPR8i8_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_NOT_GPRv_APX_DEFINED   1
 
#define XED_IFORM_NOT_GPRv_DEFINED   1
 
#define XED_IFORM_NOT_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_NOT_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_NOT_LOCK_MEMb_DEFINED   1
 
#define XED_IFORM_NOT_LOCK_MEMv_DEFINED   1
 
#define XED_IFORM_NOT_MEMb_DEFINED   1
 
#define XED_IFORM_NOT_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_NOT_MEMv_APX_DEFINED   1
 
#define XED_IFORM_NOT_MEMv_DEFINED   1
 
#define XED_IFORM_OR_AL_IMMb_DEFINED   1
 
#define XED_IFORM_OR_GPR8_GPR8_08_DEFINED   1
 
#define XED_IFORM_OR_GPR8_GPR8_0A_DEFINED   1
 
#define XED_IFORM_OR_GPR8_IMMb_80r1_DEFINED   1
 
#define XED_IFORM_OR_GPR8_IMMb_82r1_DEFINED   1
 
#define XED_IFORM_OR_GPR8_MEMb_DEFINED   1
 
#define XED_IFORM_OR_GPR8i8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_OR_GPR8i8_GPR8i8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_OR_GPR8i8_GPR8i8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_OR_GPR8i8_GPR8i8_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_OR_GPR8i8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_OR_GPR8i8_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_OR_GPR8i8_MEMi8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_OR_GPR8i8_MEMi8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_OR_GPRv_GPRv_09_DEFINED   1
 
#define XED_IFORM_OR_GPRv_GPRv_0B_DEFINED   1
 
#define XED_IFORM_OR_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_OR_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_OR_GPRv_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_OR_GPRv_GPRv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_OR_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_OR_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_OR_GPRv_IMMb_DEFINED   1
 
#define XED_IFORM_OR_GPRv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_OR_GPRv_IMMz_DEFINED   1
 
#define XED_IFORM_OR_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_OR_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_OR_GPRv_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_OR_GPRv_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_OR_GPRv_MEMv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_OR_LOCK_MEMb_GPR8_DEFINED   1
 
#define XED_IFORM_OR_LOCK_MEMb_IMMb_80r1_DEFINED   1
 
#define XED_IFORM_OR_LOCK_MEMb_IMMb_82r1_DEFINED   1
 
#define XED_IFORM_OR_LOCK_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_OR_LOCK_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_OR_LOCK_MEMv_IMMz_DEFINED   1
 
#define XED_IFORM_OR_MEMb_GPR8_DEFINED   1
 
#define XED_IFORM_OR_MEMb_IMMb_80r1_DEFINED   1
 
#define XED_IFORM_OR_MEMb_IMMb_82r1_DEFINED   1
 
#define XED_IFORM_OR_MEMi8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_OR_MEMi8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_OR_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_OR_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_OR_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_OR_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_OR_MEMv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_OR_MEMv_IMMz_DEFINED   1
 
#define XED_IFORM_OR_OrAX_IMMz_DEFINED   1
 
#define XED_IFORM_ORPD_XMMxuq_MEMxuq_DEFINED   1
 
#define XED_IFORM_ORPD_XMMxuq_XMMxuq_DEFINED   1
 
#define XED_IFORM_ORPS_XMMxud_MEMxud_DEFINED   1
 
#define XED_IFORM_ORPS_XMMxud_XMMxud_DEFINED   1
 
#define XED_IFORM_OUT_DX_AL_DEFINED   1
 
#define XED_IFORM_OUT_DX_OeAX_DEFINED   1
 
#define XED_IFORM_OUT_IMMb_AL_DEFINED   1
 
#define XED_IFORM_OUT_IMMb_OeAX_DEFINED   1
 
#define XED_IFORM_OUTSB_DEFINED   1
 
#define XED_IFORM_OUTSD_DEFINED   1
 
#define XED_IFORM_OUTSW_DEFINED   1
 
#define XED_IFORM_PABSB_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PABSB_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PABSB_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PABSB_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PABSD_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PABSD_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PABSD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PABSD_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PABSW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PABSW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PABSW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PABSW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PACKSSDW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PACKSSDW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PACKSSDW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PACKSSDW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PACKSSWB_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PACKSSWB_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PACKSSWB_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PACKSSWB_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PACKUSDW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PACKUSDW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PACKUSWB_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PACKUSWB_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PACKUSWB_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PACKUSWB_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PADDB_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PADDB_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PADDB_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PADDB_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PADDD_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PADDD_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PADDD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PADDD_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PADDQ_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PADDQ_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PADDQ_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PADDQ_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PADDSB_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PADDSB_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PADDSB_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PADDSB_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PADDSW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PADDSW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PADDSW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PADDSW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PADDUSB_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PADDUSB_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PADDUSB_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PADDUSB_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PADDUSW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PADDUSW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PADDUSW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PADDUSW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PADDW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PADDW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PADDW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PADDW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PALIGNR_MMXq_MEMq_IMMb_DEFINED   1
 
#define XED_IFORM_PALIGNR_MMXq_MMXq_IMMb_DEFINED   1
 
#define XED_IFORM_PALIGNR_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PAND_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PAND_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PAND_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PAND_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PANDN_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PANDN_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PANDN_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PANDN_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PAUSE_DEFINED   1
 
#define XED_IFORM_PAVGB_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PAVGB_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PAVGB_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PAVGB_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PAVGUSB_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PAVGUSB_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PAVGW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PAVGW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PAVGW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PAVGW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PBLENDVB_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PBLENDVB_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PBLENDW_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PBNDKB_DEFINED   1
 
#define XED_IFORM_PCLMULQDQ_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PCMPEQB_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PCMPEQB_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PCMPEQB_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PCMPEQB_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PCMPEQD_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PCMPEQD_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PCMPEQD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PCMPEQD_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PCMPEQQ_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PCMPEQQ_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PCMPEQW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PCMPEQW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PCMPEQW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PCMPEQW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PCMPESTRI64_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PCMPESTRI64_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PCMPESTRM64_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PCMPESTRM64_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PCMPGTB_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PCMPGTB_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PCMPGTB_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PCMPGTB_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PCMPGTD_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PCMPGTD_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PCMPGTD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PCMPGTD_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PCMPGTQ_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PCMPGTQ_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PCMPGTW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PCMPGTW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PCMPGTW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PCMPGTW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PCMPISTRI64_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PCMPISTRI64_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PCMPISTRM_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PCONFIG64_DEFINED   1
 
#define XED_IFORM_PCONFIG_DEFINED   1
 
#define XED_IFORM_PDEP_GPR32d_GPR32d_GPR32d_DEFINED   1
 
#define XED_IFORM_PDEP_GPR32d_GPR32d_MEMd_DEFINED   1
 
#define XED_IFORM_PDEP_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED   1
 
#define XED_IFORM_PDEP_GPR32i32_GPR32i32_MEMi32_APX_DEFINED   1
 
#define XED_IFORM_PDEP_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED   1
 
#define XED_IFORM_PDEP_GPR64i64_GPR64i64_MEMi64_APX_DEFINED   1
 
#define XED_IFORM_PDEP_GPR64q_GPR64q_GPR64q_DEFINED   1
 
#define XED_IFORM_PDEP_GPR64q_GPR64q_MEMq_DEFINED   1
 
#define XED_IFORM_PEXT_GPR32d_GPR32d_GPR32d_DEFINED   1
 
#define XED_IFORM_PEXT_GPR32d_GPR32d_MEMd_DEFINED   1
 
#define XED_IFORM_PEXT_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED   1
 
#define XED_IFORM_PEXT_GPR32i32_GPR32i32_MEMi32_APX_DEFINED   1
 
#define XED_IFORM_PEXT_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED   1
 
#define XED_IFORM_PEXT_GPR64i64_GPR64i64_MEMi64_APX_DEFINED   1
 
#define XED_IFORM_PEXT_GPR64q_GPR64q_GPR64q_DEFINED   1
 
#define XED_IFORM_PEXT_GPR64q_GPR64q_MEMq_DEFINED   1
 
#define XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PEXTRB_MEMb_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PEXTRD_MEMd_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PEXTRQ_MEMq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PEXTRW_GPR32_MMXq_IMMb_DEFINED   1
 
#define XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PEXTRW_SSE4_GPR32_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PEXTRW_SSE4_MEMw_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PF2ID_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PF2ID_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PF2IW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PF2IW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PFACC_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PFACC_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PFADD_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PFADD_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PFCMPEQ_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PFCMPEQ_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PFCMPGE_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PFCMPGE_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PFCMPGT_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PFCMPGT_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PFMAX_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PFMAX_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PFMIN_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PFMIN_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PFMUL_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PFMUL_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PFNACC_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PFNACC_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PFPNACC_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PFPNACC_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PFRCP_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PFRCP_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PFRCPIT1_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PFRCPIT1_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PFRCPIT2_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PFRCPIT2_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PFRSQIT1_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PFRSQIT1_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PFRSQRT_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PFRSQRT_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PFSUB_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PFSUB_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PFSUBR_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PFSUBR_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PHADDD_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PHADDD_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PHADDD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PHADDD_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PHADDSW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PHADDSW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PHADDSW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PHADDSW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PHADDW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PHADDW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PHADDW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PHADDW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PHMINPOSUW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PHMINPOSUW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PHSUBD_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PHSUBD_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PHSUBD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PHSUBD_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PHSUBSW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PHSUBSW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PHSUBSW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PHSUBSW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PHSUBW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PHSUBW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PHSUBW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PHSUBW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PI2FD_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PI2FD_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PI2FW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PI2FW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb_DEFINED   1
 
#define XED_IFORM_PINSRB_XMMdq_MEMb_IMMb_DEFINED   1
 
#define XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb_DEFINED   1
 
#define XED_IFORM_PINSRD_XMMdq_MEMd_IMMb_DEFINED   1
 
#define XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb_DEFINED   1
 
#define XED_IFORM_PINSRQ_XMMdq_MEMq_IMMb_DEFINED   1
 
#define XED_IFORM_PINSRW_MMXq_GPR32_IMMb_DEFINED   1
 
#define XED_IFORM_PINSRW_MMXq_MEMw_IMMb_DEFINED   1
 
#define XED_IFORM_PINSRW_XMMdq_GPR32_IMMb_DEFINED   1
 
#define XED_IFORM_PINSRW_XMMdq_MEMw_IMMb_DEFINED   1
 
#define XED_IFORM_PMADDUBSW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PMADDUBSW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PMADDUBSW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PMADDUBSW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PMADDWD_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PMADDWD_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PMADDWD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PMADDWD_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PMAXSB_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PMAXSB_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PMAXSD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PMAXSD_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PMAXSW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PMAXSW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PMAXSW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PMAXSW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PMAXUB_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PMAXUB_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PMAXUB_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PMAXUB_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PMAXUD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PMAXUD_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PMAXUW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PMAXUW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PMINSB_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PMINSB_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PMINSD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PMINSD_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PMINSW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PMINSW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PMINSW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PMINSW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PMINUB_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PMINUB_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PMINUB_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PMINUB_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PMINUD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PMINUD_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PMINUW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PMINUW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PMOVMSKB_GPR32_MMXq_DEFINED   1
 
#define XED_IFORM_PMOVMSKB_GPR32_XMMdq_DEFINED   1
 
#define XED_IFORM_PMOVSXBD_XMMdq_MEMd_DEFINED   1
 
#define XED_IFORM_PMOVSXBD_XMMdq_XMMd_DEFINED   1
 
#define XED_IFORM_PMOVSXBQ_XMMdq_MEMw_DEFINED   1
 
#define XED_IFORM_PMOVSXBQ_XMMdq_XMMw_DEFINED   1
 
#define XED_IFORM_PMOVSXBW_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_PMOVSXBW_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_PMOVSXDQ_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_PMOVSXDQ_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_PMOVSXWD_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_PMOVSXWD_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_PMOVSXWQ_XMMdq_MEMd_DEFINED   1
 
#define XED_IFORM_PMOVSXWQ_XMMdq_XMMd_DEFINED   1
 
#define XED_IFORM_PMOVZXBD_XMMdq_MEMd_DEFINED   1
 
#define XED_IFORM_PMOVZXBD_XMMdq_XMMd_DEFINED   1
 
#define XED_IFORM_PMOVZXBQ_XMMdq_MEMw_DEFINED   1
 
#define XED_IFORM_PMOVZXBQ_XMMdq_XMMw_DEFINED   1
 
#define XED_IFORM_PMOVZXBW_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_PMOVZXBW_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_PMOVZXDQ_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_PMOVZXDQ_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_PMOVZXWD_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_PMOVZXWD_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_PMOVZXWQ_XMMdq_MEMd_DEFINED   1
 
#define XED_IFORM_PMOVZXWQ_XMMdq_XMMd_DEFINED   1
 
#define XED_IFORM_PMULDQ_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PMULDQ_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PMULHRSW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PMULHRSW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PMULHRSW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PMULHRSW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PMULHRW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PMULHRW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PMULHUW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PMULHUW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PMULHUW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PMULHUW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PMULHW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PMULHW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PMULHW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PMULHW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PMULLD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PMULLD_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PMULLW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PMULLW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PMULLW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PMULLW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PMULUDQ_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PMULUDQ_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PMULUDQ_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PMULUDQ_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_POP2_GPR64u64_GPR64u64_APX_DEFINED   1
 
#define XED_IFORM_POP2P_GPR64u64_GPR64u64_APX_DEFINED   1
 
#define XED_IFORM_POP_DS_DEFINED   1
 
#define XED_IFORM_POP_ES_DEFINED   1
 
#define XED_IFORM_POP_FS_DEFINED   1
 
#define XED_IFORM_POP_GPRv_58_DEFINED   1
 
#define XED_IFORM_POP_GPRv_8F_DEFINED   1
 
#define XED_IFORM_POP_GS_DEFINED   1
 
#define XED_IFORM_POP_MEMv_DEFINED   1
 
#define XED_IFORM_POP_SS_DEFINED   1
 
#define XED_IFORM_POPA_DEFINED   1
 
#define XED_IFORM_POPAD_DEFINED   1
 
#define XED_IFORM_POPCNT_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_POPCNT_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_POPCNT_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_POPCNT_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_POPF_DEFINED   1
 
#define XED_IFORM_POPFD_DEFINED   1
 
#define XED_IFORM_POPFQ_DEFINED   1
 
#define XED_IFORM_POPP_GPR64_DEFINED   1
 
#define XED_IFORM_POR_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_POR_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_POR_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_POR_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PREFETCH_EXCLUSIVE_MEMmprefetch_DEFINED   1
 
#define XED_IFORM_PREFETCH_RESERVED_0F0Dr4_DEFINED   1
 
#define XED_IFORM_PREFETCH_RESERVED_0F0Dr5_DEFINED   1
 
#define XED_IFORM_PREFETCH_RESERVED_0F0Dr6_DEFINED   1
 
#define XED_IFORM_PREFETCH_RESERVED_0F0Dr7_DEFINED   1
 
#define XED_IFORM_PREFETCHIT0_MEMu8_DEFINED   1
 
#define XED_IFORM_PREFETCHIT1_MEMu8_DEFINED   1
 
#define XED_IFORM_PREFETCHNTA_MEMmprefetch_DEFINED   1
 
#define XED_IFORM_PREFETCHRST2_MEMu8_DEFINED   1
 
#define XED_IFORM_PREFETCHT0_MEMmprefetch_DEFINED   1
 
#define XED_IFORM_PREFETCHT1_MEMmprefetch_DEFINED   1
 
#define XED_IFORM_PREFETCHT2_MEMmprefetch_DEFINED   1
 
#define XED_IFORM_PREFETCHW_0F0Dr1_DEFINED   1
 
#define XED_IFORM_PREFETCHW_0F0Dr3_DEFINED   1
 
#define XED_IFORM_PREFETCHWT1_MEMu8_DEFINED   1
 
#define XED_IFORM_PSADBW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PSADBW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PSADBW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PSADBW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PSHUFB_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PSHUFB_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PSHUFB_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PSHUFB_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PSHUFD_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PSHUFHW_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PSHUFLW_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PSHUFW_MMXq_MEMq_IMMb_DEFINED   1
 
#define XED_IFORM_PSHUFW_MMXq_MMXq_IMMb_DEFINED   1
 
#define XED_IFORM_PSIGNB_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PSIGNB_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PSIGNB_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PSIGNB_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PSIGND_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PSIGND_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PSIGND_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PSIGND_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PSIGNW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PSIGNW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PSIGNW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PSIGNW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PSLLD_MMXq_IMMb_DEFINED   1
 
#define XED_IFORM_PSLLD_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PSLLD_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PSLLD_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PSLLD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PSLLD_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PSLLDQ_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PSLLQ_MMXq_IMMb_DEFINED   1
 
#define XED_IFORM_PSLLQ_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PSLLQ_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PSLLQ_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PSLLQ_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PSLLQ_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PSLLW_MMXq_IMMb_DEFINED   1
 
#define XED_IFORM_PSLLW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PSLLW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PSLLW_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PSLLW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PSLLW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PSMASH_RAX_DEFINED   1
 
#define XED_IFORM_PSRAD_MMXq_IMMb_DEFINED   1
 
#define XED_IFORM_PSRAD_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PSRAD_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PSRAD_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PSRAD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PSRAD_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PSRAW_MMXq_IMMb_DEFINED   1
 
#define XED_IFORM_PSRAW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PSRAW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PSRAW_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PSRAW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PSRAW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PSRLD_MMXq_IMMb_DEFINED   1
 
#define XED_IFORM_PSRLD_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PSRLD_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PSRLD_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PSRLD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PSRLD_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PSRLDQ_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PSRLQ_MMXq_IMMb_DEFINED   1
 
#define XED_IFORM_PSRLQ_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PSRLQ_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PSRLQ_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PSRLQ_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PSRLQ_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PSRLW_MMXq_IMMb_DEFINED   1
 
#define XED_IFORM_PSRLW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PSRLW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PSRLW_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_PSRLW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PSRLW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PSUBB_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PSUBB_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PSUBB_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PSUBB_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PSUBD_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PSUBD_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PSUBD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PSUBD_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PSUBQ_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PSUBQ_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PSUBQ_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PSUBQ_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PSUBSB_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PSUBSB_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PSUBSB_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PSUBSB_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PSUBSW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PSUBSW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PSUBSW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PSUBSW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PSUBUSB_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PSUBUSB_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PSUBUSB_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PSUBUSB_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PSUBUSW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PSUBUSW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PSUBUSW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PSUBUSW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PSUBW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PSUBW_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PSUBW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PSUBW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PSWAPD_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PSWAPD_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PTEST_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PTEST_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_PTWRITE_GPRy_DEFINED   1
 
#define XED_IFORM_PTWRITE_MEMy_DEFINED   1
 
#define XED_IFORM_PUNPCKHBW_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PUNPCKHBW_MMXq_MMXd_DEFINED   1
 
#define XED_IFORM_PUNPCKHBW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PUNPCKHBW_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_PUNPCKHDQ_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PUNPCKHDQ_MMXq_MMXd_DEFINED   1
 
#define XED_IFORM_PUNPCKHDQ_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PUNPCKHDQ_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_PUNPCKHQDQ_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PUNPCKHQDQ_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_PUNPCKHWD_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PUNPCKHWD_MMXq_MMXd_DEFINED   1
 
#define XED_IFORM_PUNPCKHWD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PUNPCKHWD_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_PUNPCKLBW_MMXq_MEMd_DEFINED   1
 
#define XED_IFORM_PUNPCKLBW_MMXq_MMXd_DEFINED   1
 
#define XED_IFORM_PUNPCKLBW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PUNPCKLBW_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_PUNPCKLDQ_MMXq_MEMd_DEFINED   1
 
#define XED_IFORM_PUNPCKLDQ_MMXq_MMXd_DEFINED   1
 
#define XED_IFORM_PUNPCKLDQ_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PUNPCKLDQ_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_PUNPCKLQDQ_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PUNPCKLQDQ_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_PUNPCKLWD_MMXq_MEMd_DEFINED   1
 
#define XED_IFORM_PUNPCKLWD_MMXq_MMXd_DEFINED   1
 
#define XED_IFORM_PUNPCKLWD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PUNPCKLWD_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_PUSH2_GPR64u64_GPR64u64_APX_DEFINED   1
 
#define XED_IFORM_PUSH2P_GPR64u64_GPR64u64_APX_DEFINED   1
 
#define XED_IFORM_PUSH_CS_DEFINED   1
 
#define XED_IFORM_PUSH_DS_DEFINED   1
 
#define XED_IFORM_PUSH_ES_DEFINED   1
 
#define XED_IFORM_PUSH_FS_DEFINED   1
 
#define XED_IFORM_PUSH_GPRv_50_DEFINED   1
 
#define XED_IFORM_PUSH_GPRv_FFr6_DEFINED   1
 
#define XED_IFORM_PUSH_GS_DEFINED   1
 
#define XED_IFORM_PUSH_IMMb_DEFINED   1
 
#define XED_IFORM_PUSH_IMMz_DEFINED   1
 
#define XED_IFORM_PUSH_MEMv_DEFINED   1
 
#define XED_IFORM_PUSH_SS_DEFINED   1
 
#define XED_IFORM_PUSHA_DEFINED   1
 
#define XED_IFORM_PUSHAD_DEFINED   1
 
#define XED_IFORM_PUSHF_DEFINED   1
 
#define XED_IFORM_PUSHFD_DEFINED   1
 
#define XED_IFORM_PUSHFQ_DEFINED   1
 
#define XED_IFORM_PUSHP_GPR64_DEFINED   1
 
#define XED_IFORM_PVALIDATE_RAX_ECX_EDX_DEFINED   1
 
#define XED_IFORM_PXOR_MMXq_MEMq_DEFINED   1
 
#define XED_IFORM_PXOR_MMXq_MMXq_DEFINED   1
 
#define XED_IFORM_PXOR_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_PXOR_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_RCL_GPR8_CL_DEFINED   1
 
#define XED_IFORM_RCL_GPR8_IMMb_DEFINED   1
 
#define XED_IFORM_RCL_GPR8_ONE_DEFINED   1
 
#define XED_IFORM_RCL_GPR8i8_CL_APX_DEFINED   1
 
#define XED_IFORM_RCL_GPR8i8_GPR8i8_CL_APX_DEFINED   1
 
#define XED_IFORM_RCL_GPR8i8_GPR8i8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_RCL_GPR8i8_GPR8i8_ONE_APX_DEFINED   1
 
#define XED_IFORM_RCL_GPR8i8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_RCL_GPR8i8_MEMi8_CL_APX_DEFINED   1
 
#define XED_IFORM_RCL_GPR8i8_MEMi8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_RCL_GPR8i8_MEMi8_ONE_APX_DEFINED   1
 
#define XED_IFORM_RCL_GPR8i8_ONE_APX_DEFINED   1
 
#define XED_IFORM_RCL_GPRv_CL_APX_DEFINED   1
 
#define XED_IFORM_RCL_GPRv_CL_DEFINED   1
 
#define XED_IFORM_RCL_GPRv_GPRv_CL_APX_DEFINED   1
 
#define XED_IFORM_RCL_GPRv_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_RCL_GPRv_GPRv_ONE_APX_DEFINED   1
 
#define XED_IFORM_RCL_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_RCL_GPRv_IMMb_DEFINED   1
 
#define XED_IFORM_RCL_GPRv_MEMv_CL_APX_DEFINED   1
 
#define XED_IFORM_RCL_GPRv_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_RCL_GPRv_MEMv_ONE_APX_DEFINED   1
 
#define XED_IFORM_RCL_GPRv_ONE_APX_DEFINED   1
 
#define XED_IFORM_RCL_GPRv_ONE_DEFINED   1
 
#define XED_IFORM_RCL_MEMb_CL_DEFINED   1
 
#define XED_IFORM_RCL_MEMb_IMMb_DEFINED   1
 
#define XED_IFORM_RCL_MEMb_ONE_DEFINED   1
 
#define XED_IFORM_RCL_MEMi8_CL_APX_DEFINED   1
 
#define XED_IFORM_RCL_MEMi8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_RCL_MEMi8_ONE_APX_DEFINED   1
 
#define XED_IFORM_RCL_MEMv_CL_APX_DEFINED   1
 
#define XED_IFORM_RCL_MEMv_CL_DEFINED   1
 
#define XED_IFORM_RCL_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_RCL_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_RCL_MEMv_ONE_APX_DEFINED   1
 
#define XED_IFORM_RCL_MEMv_ONE_DEFINED   1
 
#define XED_IFORM_RCPPS_XMMps_MEMps_DEFINED   1
 
#define XED_IFORM_RCPPS_XMMps_XMMps_DEFINED   1
 
#define XED_IFORM_RCPSS_XMMss_MEMss_DEFINED   1
 
#define XED_IFORM_RCPSS_XMMss_XMMss_DEFINED   1
 
#define XED_IFORM_RCR_GPR8_CL_DEFINED   1
 
#define XED_IFORM_RCR_GPR8_IMMb_DEFINED   1
 
#define XED_IFORM_RCR_GPR8_ONE_DEFINED   1
 
#define XED_IFORM_RCR_GPR8i8_CL_APX_DEFINED   1
 
#define XED_IFORM_RCR_GPR8i8_GPR8i8_CL_APX_DEFINED   1
 
#define XED_IFORM_RCR_GPR8i8_GPR8i8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_RCR_GPR8i8_GPR8i8_ONE_APX_DEFINED   1
 
#define XED_IFORM_RCR_GPR8i8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_RCR_GPR8i8_MEMi8_CL_APX_DEFINED   1
 
#define XED_IFORM_RCR_GPR8i8_MEMi8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_RCR_GPR8i8_MEMi8_ONE_APX_DEFINED   1
 
#define XED_IFORM_RCR_GPR8i8_ONE_APX_DEFINED   1
 
#define XED_IFORM_RCR_GPRv_CL_APX_DEFINED   1
 
#define XED_IFORM_RCR_GPRv_CL_DEFINED   1
 
#define XED_IFORM_RCR_GPRv_GPRv_CL_APX_DEFINED   1
 
#define XED_IFORM_RCR_GPRv_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_RCR_GPRv_GPRv_ONE_APX_DEFINED   1
 
#define XED_IFORM_RCR_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_RCR_GPRv_IMMb_DEFINED   1
 
#define XED_IFORM_RCR_GPRv_MEMv_CL_APX_DEFINED   1
 
#define XED_IFORM_RCR_GPRv_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_RCR_GPRv_MEMv_ONE_APX_DEFINED   1
 
#define XED_IFORM_RCR_GPRv_ONE_APX_DEFINED   1
 
#define XED_IFORM_RCR_GPRv_ONE_DEFINED   1
 
#define XED_IFORM_RCR_MEMb_CL_DEFINED   1
 
#define XED_IFORM_RCR_MEMb_IMMb_DEFINED   1
 
#define XED_IFORM_RCR_MEMb_ONE_DEFINED   1
 
#define XED_IFORM_RCR_MEMi8_CL_APX_DEFINED   1
 
#define XED_IFORM_RCR_MEMi8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_RCR_MEMi8_ONE_APX_DEFINED   1
 
#define XED_IFORM_RCR_MEMv_CL_APX_DEFINED   1
 
#define XED_IFORM_RCR_MEMv_CL_DEFINED   1
 
#define XED_IFORM_RCR_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_RCR_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_RCR_MEMv_ONE_APX_DEFINED   1
 
#define XED_IFORM_RCR_MEMv_ONE_DEFINED   1
 
#define XED_IFORM_RDFSBASE_GPRy_DEFINED   1
 
#define XED_IFORM_RDGSBASE_GPRy_DEFINED   1
 
#define XED_IFORM_RDMSR_DEFINED   1
 
#define XED_IFORM_RDMSR_GPR64u64_IMM32_APX_DEFINED   1
 
#define XED_IFORM_RDMSR_GPR64u64_IMM32_DEFINED   1
 
#define XED_IFORM_RDMSRLIST_DEFINED   1
 
#define XED_IFORM_RDPID_GPR32u32_DEFINED   1
 
#define XED_IFORM_RDPID_GPR64u64_DEFINED   1
 
#define XED_IFORM_RDPKRU_DEFINED   1
 
#define XED_IFORM_RDPMC_DEFINED   1
 
#define XED_IFORM_RDPRU_DEFINED   1
 
#define XED_IFORM_RDRAND_GPRv_DEFINED   1
 
#define XED_IFORM_RDSEED_GPRv_DEFINED   1
 
#define XED_IFORM_RDSSPD_GPR32u32_DEFINED   1
 
#define XED_IFORM_RDSSPQ_GPR64u64_DEFINED   1
 
#define XED_IFORM_RDTSC_DEFINED   1
 
#define XED_IFORM_RDTSCP_DEFINED   1
 
#define XED_IFORM_REP_INSB_DEFINED   1
 
#define XED_IFORM_REP_INSD_DEFINED   1
 
#define XED_IFORM_REP_INSW_DEFINED   1
 
#define XED_IFORM_REP_LODSB_DEFINED   1
 
#define XED_IFORM_REP_LODSD_DEFINED   1
 
#define XED_IFORM_REP_LODSQ_DEFINED   1
 
#define XED_IFORM_REP_LODSW_DEFINED   1
 
#define XED_IFORM_REP_MONTMUL_DEFINED   1
 
#define XED_IFORM_REP_MOVSB_DEFINED   1
 
#define XED_IFORM_REP_MOVSD_DEFINED   1
 
#define XED_IFORM_REP_MOVSQ_DEFINED   1
 
#define XED_IFORM_REP_MOVSW_DEFINED   1
 
#define XED_IFORM_REP_OUTSB_DEFINED   1
 
#define XED_IFORM_REP_OUTSD_DEFINED   1
 
#define XED_IFORM_REP_OUTSW_DEFINED   1
 
#define XED_IFORM_REP_STOSB_DEFINED   1
 
#define XED_IFORM_REP_STOSD_DEFINED   1
 
#define XED_IFORM_REP_STOSQ_DEFINED   1
 
#define XED_IFORM_REP_STOSW_DEFINED   1
 
#define XED_IFORM_REP_XCRYPTCBC_DEFINED   1
 
#define XED_IFORM_REP_XCRYPTCFB_DEFINED   1
 
#define XED_IFORM_REP_XCRYPTCTR_DEFINED   1
 
#define XED_IFORM_REP_XCRYPTECB_DEFINED   1
 
#define XED_IFORM_REP_XCRYPTOFB_DEFINED   1
 
#define XED_IFORM_REP_XSHA1_DEFINED   1
 
#define XED_IFORM_REP_XSHA256_DEFINED   1
 
#define XED_IFORM_REP_XSTORE_DEFINED   1
 
#define XED_IFORM_REPE_CMPSB_DEFINED   1
 
#define XED_IFORM_REPE_CMPSD_DEFINED   1
 
#define XED_IFORM_REPE_CMPSQ_DEFINED   1
 
#define XED_IFORM_REPE_CMPSW_DEFINED   1
 
#define XED_IFORM_REPE_SCASB_DEFINED   1
 
#define XED_IFORM_REPE_SCASD_DEFINED   1
 
#define XED_IFORM_REPE_SCASQ_DEFINED   1
 
#define XED_IFORM_REPE_SCASW_DEFINED   1
 
#define XED_IFORM_REPNE_CMPSB_DEFINED   1
 
#define XED_IFORM_REPNE_CMPSD_DEFINED   1
 
#define XED_IFORM_REPNE_CMPSQ_DEFINED   1
 
#define XED_IFORM_REPNE_CMPSW_DEFINED   1
 
#define XED_IFORM_REPNE_SCASB_DEFINED   1
 
#define XED_IFORM_REPNE_SCASD_DEFINED   1
 
#define XED_IFORM_REPNE_SCASQ_DEFINED   1
 
#define XED_IFORM_REPNE_SCASW_DEFINED   1
 
#define XED_IFORM_RET_FAR_DEFINED   1
 
#define XED_IFORM_RET_FAR_IMMw_DEFINED   1
 
#define XED_IFORM_RET_NEAR_DEFINED   1
 
#define XED_IFORM_RET_NEAR_IMMw_DEFINED   1
 
#define XED_IFORM_RMPADJUST_RAX_RCX_RDX_DEFINED   1
 
#define XED_IFORM_RMPUPDATE_RAX_RCX_DEFINED   1
 
#define XED_IFORM_ROL_GPR8_CL_DEFINED   1
 
#define XED_IFORM_ROL_GPR8_IMMb_DEFINED   1
 
#define XED_IFORM_ROL_GPR8_ONE_DEFINED   1
 
#define XED_IFORM_ROL_GPR8i8_CL_APX_DEFINED   1
 
#define XED_IFORM_ROL_GPR8i8_GPR8i8_CL_APX_DEFINED   1
 
#define XED_IFORM_ROL_GPR8i8_GPR8i8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ROL_GPR8i8_GPR8i8_ONE_APX_DEFINED   1
 
#define XED_IFORM_ROL_GPR8i8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ROL_GPR8i8_MEMi8_CL_APX_DEFINED   1
 
#define XED_IFORM_ROL_GPR8i8_MEMi8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ROL_GPR8i8_MEMi8_ONE_APX_DEFINED   1
 
#define XED_IFORM_ROL_GPR8i8_ONE_APX_DEFINED   1
 
#define XED_IFORM_ROL_GPRv_CL_APX_DEFINED   1
 
#define XED_IFORM_ROL_GPRv_CL_DEFINED   1
 
#define XED_IFORM_ROL_GPRv_GPRv_CL_APX_DEFINED   1
 
#define XED_IFORM_ROL_GPRv_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ROL_GPRv_GPRv_ONE_APX_DEFINED   1
 
#define XED_IFORM_ROL_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ROL_GPRv_IMMb_DEFINED   1
 
#define XED_IFORM_ROL_GPRv_MEMv_CL_APX_DEFINED   1
 
#define XED_IFORM_ROL_GPRv_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ROL_GPRv_MEMv_ONE_APX_DEFINED   1
 
#define XED_IFORM_ROL_GPRv_ONE_APX_DEFINED   1
 
#define XED_IFORM_ROL_GPRv_ONE_DEFINED   1
 
#define XED_IFORM_ROL_MEMb_CL_DEFINED   1
 
#define XED_IFORM_ROL_MEMb_IMMb_DEFINED   1
 
#define XED_IFORM_ROL_MEMb_ONE_DEFINED   1
 
#define XED_IFORM_ROL_MEMi8_CL_APX_DEFINED   1
 
#define XED_IFORM_ROL_MEMi8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ROL_MEMi8_ONE_APX_DEFINED   1
 
#define XED_IFORM_ROL_MEMv_CL_APX_DEFINED   1
 
#define XED_IFORM_ROL_MEMv_CL_DEFINED   1
 
#define XED_IFORM_ROL_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ROL_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_ROL_MEMv_ONE_APX_DEFINED   1
 
#define XED_IFORM_ROL_MEMv_ONE_DEFINED   1
 
#define XED_IFORM_ROR_GPR8_CL_DEFINED   1
 
#define XED_IFORM_ROR_GPR8_IMMb_DEFINED   1
 
#define XED_IFORM_ROR_GPR8_ONE_DEFINED   1
 
#define XED_IFORM_ROR_GPR8i8_CL_APX_DEFINED   1
 
#define XED_IFORM_ROR_GPR8i8_GPR8i8_CL_APX_DEFINED   1
 
#define XED_IFORM_ROR_GPR8i8_GPR8i8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ROR_GPR8i8_GPR8i8_ONE_APX_DEFINED   1
 
#define XED_IFORM_ROR_GPR8i8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ROR_GPR8i8_MEMi8_CL_APX_DEFINED   1
 
#define XED_IFORM_ROR_GPR8i8_MEMi8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ROR_GPR8i8_MEMi8_ONE_APX_DEFINED   1
 
#define XED_IFORM_ROR_GPR8i8_ONE_APX_DEFINED   1
 
#define XED_IFORM_ROR_GPRv_CL_APX_DEFINED   1
 
#define XED_IFORM_ROR_GPRv_CL_DEFINED   1
 
#define XED_IFORM_ROR_GPRv_GPRv_CL_APX_DEFINED   1
 
#define XED_IFORM_ROR_GPRv_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ROR_GPRv_GPRv_ONE_APX_DEFINED   1
 
#define XED_IFORM_ROR_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ROR_GPRv_IMMb_DEFINED   1
 
#define XED_IFORM_ROR_GPRv_MEMv_CL_APX_DEFINED   1
 
#define XED_IFORM_ROR_GPRv_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ROR_GPRv_MEMv_ONE_APX_DEFINED   1
 
#define XED_IFORM_ROR_GPRv_ONE_APX_DEFINED   1
 
#define XED_IFORM_ROR_GPRv_ONE_DEFINED   1
 
#define XED_IFORM_ROR_MEMb_CL_DEFINED   1
 
#define XED_IFORM_ROR_MEMb_IMMb_DEFINED   1
 
#define XED_IFORM_ROR_MEMb_ONE_DEFINED   1
 
#define XED_IFORM_ROR_MEMi8_CL_APX_DEFINED   1
 
#define XED_IFORM_ROR_MEMi8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ROR_MEMi8_ONE_APX_DEFINED   1
 
#define XED_IFORM_ROR_MEMv_CL_APX_DEFINED   1
 
#define XED_IFORM_ROR_MEMv_CL_DEFINED   1
 
#define XED_IFORM_ROR_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_ROR_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_ROR_MEMv_ONE_APX_DEFINED   1
 
#define XED_IFORM_ROR_MEMv_ONE_DEFINED   1
 
#define XED_IFORM_RORX_GPR32d_GPR32d_IMMb_DEFINED   1
 
#define XED_IFORM_RORX_GPR32d_MEMd_IMMb_DEFINED   1
 
#define XED_IFORM_RORX_GPR32i32_GPR32i32_IMM8_APX_DEFINED   1
 
#define XED_IFORM_RORX_GPR32i32_MEMi32_IMM8_APX_DEFINED   1
 
#define XED_IFORM_RORX_GPR64i64_GPR64i64_IMM8_APX_DEFINED   1
 
#define XED_IFORM_RORX_GPR64i64_MEMi64_IMM8_APX_DEFINED   1
 
#define XED_IFORM_RORX_GPR64q_GPR64q_IMMb_DEFINED   1
 
#define XED_IFORM_RORX_GPR64q_MEMq_IMMb_DEFINED   1
 
#define XED_IFORM_ROUNDPD_XMMpd_MEMpd_IMMb_DEFINED   1
 
#define XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb_DEFINED   1
 
#define XED_IFORM_ROUNDPS_XMMps_MEMps_IMMb_DEFINED   1
 
#define XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb_DEFINED   1
 
#define XED_IFORM_ROUNDSD_XMMq_MEMq_IMMb_DEFINED   1
 
#define XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb_DEFINED   1
 
#define XED_IFORM_ROUNDSS_XMMd_MEMd_IMMb_DEFINED   1
 
#define XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb_DEFINED   1
 
#define XED_IFORM_RSM_DEFINED   1
 
#define XED_IFORM_RSQRTPS_XMMps_MEMps_DEFINED   1
 
#define XED_IFORM_RSQRTPS_XMMps_XMMps_DEFINED   1
 
#define XED_IFORM_RSQRTSS_XMMss_MEMss_DEFINED   1
 
#define XED_IFORM_RSQRTSS_XMMss_XMMss_DEFINED   1
 
#define XED_IFORM_RSTORSSP_MEMu64_DEFINED   1
 
#define XED_IFORM_SAHF_DEFINED   1
 
#define XED_IFORM_SALC_DEFINED   1
 
#define XED_IFORM_SAR_GPR8_CL_DEFINED   1
 
#define XED_IFORM_SAR_GPR8_IMMb_DEFINED   1
 
#define XED_IFORM_SAR_GPR8_ONE_DEFINED   1
 
#define XED_IFORM_SAR_GPR8i8_CL_APX_DEFINED   1
 
#define XED_IFORM_SAR_GPR8i8_GPR8i8_CL_APX_DEFINED   1
 
#define XED_IFORM_SAR_GPR8i8_GPR8i8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SAR_GPR8i8_GPR8i8_ONE_APX_DEFINED   1
 
#define XED_IFORM_SAR_GPR8i8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SAR_GPR8i8_MEMi8_CL_APX_DEFINED   1
 
#define XED_IFORM_SAR_GPR8i8_MEMi8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SAR_GPR8i8_MEMi8_ONE_APX_DEFINED   1
 
#define XED_IFORM_SAR_GPR8i8_ONE_APX_DEFINED   1
 
#define XED_IFORM_SAR_GPRv_CL_APX_DEFINED   1
 
#define XED_IFORM_SAR_GPRv_CL_DEFINED   1
 
#define XED_IFORM_SAR_GPRv_GPRv_CL_APX_DEFINED   1
 
#define XED_IFORM_SAR_GPRv_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SAR_GPRv_GPRv_ONE_APX_DEFINED   1
 
#define XED_IFORM_SAR_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SAR_GPRv_IMMb_DEFINED   1
 
#define XED_IFORM_SAR_GPRv_MEMv_CL_APX_DEFINED   1
 
#define XED_IFORM_SAR_GPRv_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SAR_GPRv_MEMv_ONE_APX_DEFINED   1
 
#define XED_IFORM_SAR_GPRv_ONE_APX_DEFINED   1
 
#define XED_IFORM_SAR_GPRv_ONE_DEFINED   1
 
#define XED_IFORM_SAR_MEMb_CL_DEFINED   1
 
#define XED_IFORM_SAR_MEMb_IMMb_DEFINED   1
 
#define XED_IFORM_SAR_MEMb_ONE_DEFINED   1
 
#define XED_IFORM_SAR_MEMi8_CL_APX_DEFINED   1
 
#define XED_IFORM_SAR_MEMi8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SAR_MEMi8_ONE_APX_DEFINED   1
 
#define XED_IFORM_SAR_MEMv_CL_APX_DEFINED   1
 
#define XED_IFORM_SAR_MEMv_CL_DEFINED   1
 
#define XED_IFORM_SAR_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SAR_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_SAR_MEMv_ONE_APX_DEFINED   1
 
#define XED_IFORM_SAR_MEMv_ONE_DEFINED   1
 
#define XED_IFORM_SARX_GPR32d_GPR32d_GPR32d_DEFINED   1
 
#define XED_IFORM_SARX_GPR32d_MEMd_GPR32d_DEFINED   1
 
#define XED_IFORM_SARX_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED   1
 
#define XED_IFORM_SARX_GPR32i32_MEMi32_GPR32i32_APX_DEFINED   1
 
#define XED_IFORM_SARX_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED   1
 
#define XED_IFORM_SARX_GPR64i64_MEMi64_GPR64i64_APX_DEFINED   1
 
#define XED_IFORM_SARX_GPR64q_GPR64q_GPR64q_DEFINED   1
 
#define XED_IFORM_SARX_GPR64q_MEMq_GPR64q_DEFINED   1
 
#define XED_IFORM_SAVEPREVSSP_DEFINED   1
 
#define XED_IFORM_SBB_AL_IMMb_DEFINED   1
 
#define XED_IFORM_SBB_GPR8_GPR8_18_DEFINED   1
 
#define XED_IFORM_SBB_GPR8_GPR8_1A_DEFINED   1
 
#define XED_IFORM_SBB_GPR8_IMMb_80r3_DEFINED   1
 
#define XED_IFORM_SBB_GPR8_IMMb_82r3_DEFINED   1
 
#define XED_IFORM_SBB_GPR8_MEMb_DEFINED   1
 
#define XED_IFORM_SBB_GPR8i8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_SBB_GPR8i8_GPR8i8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_SBB_GPR8i8_GPR8i8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SBB_GPR8i8_GPR8i8_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_SBB_GPR8i8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SBB_GPR8i8_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_SBB_GPR8i8_MEMi8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_SBB_GPR8i8_MEMi8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SBB_GPRv_GPRv_19_DEFINED   1
 
#define XED_IFORM_SBB_GPRv_GPRv_1B_DEFINED   1
 
#define XED_IFORM_SBB_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_SBB_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_SBB_GPRv_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SBB_GPRv_GPRv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_SBB_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_SBB_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SBB_GPRv_IMMb_DEFINED   1
 
#define XED_IFORM_SBB_GPRv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_SBB_GPRv_IMMz_DEFINED   1
 
#define XED_IFORM_SBB_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_SBB_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_SBB_GPRv_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_SBB_GPRv_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SBB_GPRv_MEMv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_SBB_LOCK_MEMb_GPR8_DEFINED   1
 
#define XED_IFORM_SBB_LOCK_MEMb_IMMb_80r3_DEFINED   1
 
#define XED_IFORM_SBB_LOCK_MEMb_IMMb_82r3_DEFINED   1
 
#define XED_IFORM_SBB_LOCK_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_SBB_LOCK_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_SBB_LOCK_MEMv_IMMz_DEFINED   1
 
#define XED_IFORM_SBB_MEMb_GPR8_DEFINED   1
 
#define XED_IFORM_SBB_MEMb_IMMb_80r3_DEFINED   1
 
#define XED_IFORM_SBB_MEMb_IMMb_82r3_DEFINED   1
 
#define XED_IFORM_SBB_MEMi8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_SBB_MEMi8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SBB_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_SBB_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_SBB_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SBB_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_SBB_MEMv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_SBB_MEMv_IMMz_DEFINED   1
 
#define XED_IFORM_SBB_OrAX_IMMz_DEFINED   1
 
#define XED_IFORM_SCASB_DEFINED   1
 
#define XED_IFORM_SCASD_DEFINED   1
 
#define XED_IFORM_SCASQ_DEFINED   1
 
#define XED_IFORM_SCASW_DEFINED   1
 
#define XED_IFORM_SEAMCALL_DEFINED   1
 
#define XED_IFORM_SEAMOPS_DEFINED   1
 
#define XED_IFORM_SEAMRET_DEFINED   1
 
#define XED_IFORM_SENDUIPI_GPR64u32_DEFINED   1
 
#define XED_IFORM_SERIALIZE_DEFINED   1
 
#define XED_IFORM_SETB_GPR8_DEFINED   1
 
#define XED_IFORM_SETB_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_SETB_GPR8i8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETB_MEMb_DEFINED   1
 
#define XED_IFORM_SETB_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_SETB_MEMi8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETBE_GPR8_DEFINED   1
 
#define XED_IFORM_SETBE_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_SETBE_GPR8i8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETBE_MEMb_DEFINED   1
 
#define XED_IFORM_SETBE_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_SETBE_MEMi8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETL_GPR8_DEFINED   1
 
#define XED_IFORM_SETL_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_SETL_GPR8i8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETL_MEMb_DEFINED   1
 
#define XED_IFORM_SETL_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_SETL_MEMi8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETLE_GPR8_DEFINED   1
 
#define XED_IFORM_SETLE_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_SETLE_GPR8i8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETLE_MEMb_DEFINED   1
 
#define XED_IFORM_SETLE_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_SETLE_MEMi8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETNB_GPR8_DEFINED   1
 
#define XED_IFORM_SETNB_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_SETNB_GPR8i8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETNB_MEMb_DEFINED   1
 
#define XED_IFORM_SETNB_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_SETNB_MEMi8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETNBE_GPR8_DEFINED   1
 
#define XED_IFORM_SETNBE_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_SETNBE_GPR8i8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETNBE_MEMb_DEFINED   1
 
#define XED_IFORM_SETNBE_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_SETNBE_MEMi8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETNL_GPR8_DEFINED   1
 
#define XED_IFORM_SETNL_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_SETNL_GPR8i8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETNL_MEMb_DEFINED   1
 
#define XED_IFORM_SETNL_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_SETNL_MEMi8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETNLE_GPR8_DEFINED   1
 
#define XED_IFORM_SETNLE_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_SETNLE_GPR8i8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETNLE_MEMb_DEFINED   1
 
#define XED_IFORM_SETNLE_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_SETNLE_MEMi8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETNO_GPR8_DEFINED   1
 
#define XED_IFORM_SETNO_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_SETNO_GPR8i8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETNO_MEMb_DEFINED   1
 
#define XED_IFORM_SETNO_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_SETNO_MEMi8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETNP_GPR8_DEFINED   1
 
#define XED_IFORM_SETNP_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_SETNP_GPR8i8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETNP_MEMb_DEFINED   1
 
#define XED_IFORM_SETNP_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_SETNP_MEMi8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETNS_GPR8_DEFINED   1
 
#define XED_IFORM_SETNS_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_SETNS_GPR8i8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETNS_MEMb_DEFINED   1
 
#define XED_IFORM_SETNS_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_SETNS_MEMi8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETNZ_GPR8_DEFINED   1
 
#define XED_IFORM_SETNZ_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_SETNZ_GPR8i8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETNZ_MEMb_DEFINED   1
 
#define XED_IFORM_SETNZ_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_SETNZ_MEMi8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETO_GPR8_DEFINED   1
 
#define XED_IFORM_SETO_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_SETO_GPR8i8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETO_MEMb_DEFINED   1
 
#define XED_IFORM_SETO_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_SETO_MEMi8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETP_GPR8_DEFINED   1
 
#define XED_IFORM_SETP_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_SETP_GPR8i8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETP_MEMb_DEFINED   1
 
#define XED_IFORM_SETP_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_SETP_MEMi8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETS_GPR8_DEFINED   1
 
#define XED_IFORM_SETS_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_SETS_GPR8i8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETS_MEMb_DEFINED   1
 
#define XED_IFORM_SETS_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_SETS_MEMi8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETSSBSY_DEFINED   1
 
#define XED_IFORM_SETZ_GPR8_DEFINED   1
 
#define XED_IFORM_SETZ_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_SETZ_GPR8i8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SETZ_MEMb_DEFINED   1
 
#define XED_IFORM_SETZ_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_SETZ_MEMi8_APX_ZU_DEFINED   1
 
#define XED_IFORM_SFENCE_DEFINED   1
 
#define XED_IFORM_SGDT_MEMs64_DEFINED   1
 
#define XED_IFORM_SGDT_MEMs_DEFINED   1
 
#define XED_IFORM_SHA1MSG1_XMMi32_MEMi32_SHA_DEFINED   1
 
#define XED_IFORM_SHA1MSG1_XMMi32_XMMi32_SHA_DEFINED   1
 
#define XED_IFORM_SHA1MSG2_XMMi32_MEMi32_SHA_DEFINED   1
 
#define XED_IFORM_SHA1MSG2_XMMi32_XMMi32_SHA_DEFINED   1
 
#define XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_SHA_DEFINED   1
 
#define XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_SHA_DEFINED   1
 
#define XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA_DEFINED   1
 
#define XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA_DEFINED   1
 
#define XED_IFORM_SHA256MSG1_XMMi32_MEMi32_SHA_DEFINED   1
 
#define XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA_DEFINED   1
 
#define XED_IFORM_SHA256MSG2_XMMi32_MEMi32_SHA_DEFINED   1
 
#define XED_IFORM_SHA256MSG2_XMMi32_XMMi32_SHA_DEFINED   1
 
#define XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_SHA_DEFINED   1
 
#define XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_SHA_DEFINED   1
 
#define XED_IFORM_SHL_GPR8_CL_D2r4_DEFINED   1
 
#define XED_IFORM_SHL_GPR8_CL_D2r6_DEFINED   1
 
#define XED_IFORM_SHL_GPR8_IMMb_C0r4_DEFINED   1
 
#define XED_IFORM_SHL_GPR8_IMMb_C0r6_DEFINED   1
 
#define XED_IFORM_SHL_GPR8_ONE_D0r4_DEFINED   1
 
#define XED_IFORM_SHL_GPR8_ONE_D0r6_DEFINED   1
 
#define XED_IFORM_SHL_GPR8i8_CL_APX_DEFINED   1
 
#define XED_IFORM_SHL_GPR8i8_GPR8i8_CL_APX_DEFINED   1
 
#define XED_IFORM_SHL_GPR8i8_GPR8i8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SHL_GPR8i8_GPR8i8_ONE_APX_DEFINED   1
 
#define XED_IFORM_SHL_GPR8i8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SHL_GPR8i8_MEMi8_CL_APX_DEFINED   1
 
#define XED_IFORM_SHL_GPR8i8_MEMi8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SHL_GPR8i8_MEMi8_ONE_APX_DEFINED   1
 
#define XED_IFORM_SHL_GPR8i8_ONE_APX_DEFINED   1
 
#define XED_IFORM_SHL_GPRv_CL_APX_DEFINED   1
 
#define XED_IFORM_SHL_GPRv_CL_D3r4_DEFINED   1
 
#define XED_IFORM_SHL_GPRv_CL_D3r6_DEFINED   1
 
#define XED_IFORM_SHL_GPRv_GPRv_CL_APX_DEFINED   1
 
#define XED_IFORM_SHL_GPRv_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SHL_GPRv_GPRv_ONE_APX_DEFINED   1
 
#define XED_IFORM_SHL_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SHL_GPRv_IMMb_C1r4_DEFINED   1
 
#define XED_IFORM_SHL_GPRv_IMMb_C1r6_DEFINED   1
 
#define XED_IFORM_SHL_GPRv_MEMv_CL_APX_DEFINED   1
 
#define XED_IFORM_SHL_GPRv_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SHL_GPRv_MEMv_ONE_APX_DEFINED   1
 
#define XED_IFORM_SHL_GPRv_ONE_APX_DEFINED   1
 
#define XED_IFORM_SHL_GPRv_ONE_D1r4_DEFINED   1
 
#define XED_IFORM_SHL_GPRv_ONE_D1r6_DEFINED   1
 
#define XED_IFORM_SHL_MEMb_CL_D2r4_DEFINED   1
 
#define XED_IFORM_SHL_MEMb_CL_D2r6_DEFINED   1
 
#define XED_IFORM_SHL_MEMb_IMMb_C0r4_DEFINED   1
 
#define XED_IFORM_SHL_MEMb_IMMb_C0r6_DEFINED   1
 
#define XED_IFORM_SHL_MEMb_ONE_D0r4_DEFINED   1
 
#define XED_IFORM_SHL_MEMb_ONE_D0r6_DEFINED   1
 
#define XED_IFORM_SHL_MEMi8_CL_APX_DEFINED   1
 
#define XED_IFORM_SHL_MEMi8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SHL_MEMi8_ONE_APX_DEFINED   1
 
#define XED_IFORM_SHL_MEMv_CL_APX_DEFINED   1
 
#define XED_IFORM_SHL_MEMv_CL_D3r4_DEFINED   1
 
#define XED_IFORM_SHL_MEMv_CL_D3r6_DEFINED   1
 
#define XED_IFORM_SHL_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SHL_MEMv_IMMb_C1r4_DEFINED   1
 
#define XED_IFORM_SHL_MEMv_IMMb_C1r6_DEFINED   1
 
#define XED_IFORM_SHL_MEMv_ONE_APX_DEFINED   1
 
#define XED_IFORM_SHL_MEMv_ONE_D1r4_DEFINED   1
 
#define XED_IFORM_SHL_MEMv_ONE_D1r6_DEFINED   1
 
#define XED_IFORM_SHLD_GPRv_GPRv_CL_APX_DEFINED   1
 
#define XED_IFORM_SHLD_GPRv_GPRv_CL_DEFINED   1
 
#define XED_IFORM_SHLD_GPRv_GPRv_GPRv_CL_APX_DEFINED   1
 
#define XED_IFORM_SHLD_GPRv_GPRv_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SHLD_GPRv_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SHLD_GPRv_GPRv_IMMb_DEFINED   1
 
#define XED_IFORM_SHLD_GPRv_MEMv_GPRv_CL_APX_DEFINED   1
 
#define XED_IFORM_SHLD_GPRv_MEMv_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SHLD_MEMv_GPRv_CL_APX_DEFINED   1
 
#define XED_IFORM_SHLD_MEMv_GPRv_CL_DEFINED   1
 
#define XED_IFORM_SHLD_MEMv_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SHLD_MEMv_GPRv_IMMb_DEFINED   1
 
#define XED_IFORM_SHLX_GPR32d_GPR32d_GPR32d_DEFINED   1
 
#define XED_IFORM_SHLX_GPR32d_MEMd_GPR32d_DEFINED   1
 
#define XED_IFORM_SHLX_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED   1
 
#define XED_IFORM_SHLX_GPR32i32_MEMi32_GPR32i32_APX_DEFINED   1
 
#define XED_IFORM_SHLX_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED   1
 
#define XED_IFORM_SHLX_GPR64i64_MEMi64_GPR64i64_APX_DEFINED   1
 
#define XED_IFORM_SHLX_GPR64q_GPR64q_GPR64q_DEFINED   1
 
#define XED_IFORM_SHLX_GPR64q_MEMq_GPR64q_DEFINED   1
 
#define XED_IFORM_SHR_GPR8_CL_DEFINED   1
 
#define XED_IFORM_SHR_GPR8_IMMb_DEFINED   1
 
#define XED_IFORM_SHR_GPR8_ONE_DEFINED   1
 
#define XED_IFORM_SHR_GPR8i8_CL_APX_DEFINED   1
 
#define XED_IFORM_SHR_GPR8i8_GPR8i8_CL_APX_DEFINED   1
 
#define XED_IFORM_SHR_GPR8i8_GPR8i8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SHR_GPR8i8_GPR8i8_ONE_APX_DEFINED   1
 
#define XED_IFORM_SHR_GPR8i8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SHR_GPR8i8_MEMi8_CL_APX_DEFINED   1
 
#define XED_IFORM_SHR_GPR8i8_MEMi8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SHR_GPR8i8_MEMi8_ONE_APX_DEFINED   1
 
#define XED_IFORM_SHR_GPR8i8_ONE_APX_DEFINED   1
 
#define XED_IFORM_SHR_GPRv_CL_APX_DEFINED   1
 
#define XED_IFORM_SHR_GPRv_CL_DEFINED   1
 
#define XED_IFORM_SHR_GPRv_GPRv_CL_APX_DEFINED   1
 
#define XED_IFORM_SHR_GPRv_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SHR_GPRv_GPRv_ONE_APX_DEFINED   1
 
#define XED_IFORM_SHR_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SHR_GPRv_IMMb_DEFINED   1
 
#define XED_IFORM_SHR_GPRv_MEMv_CL_APX_DEFINED   1
 
#define XED_IFORM_SHR_GPRv_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SHR_GPRv_MEMv_ONE_APX_DEFINED   1
 
#define XED_IFORM_SHR_GPRv_ONE_APX_DEFINED   1
 
#define XED_IFORM_SHR_GPRv_ONE_DEFINED   1
 
#define XED_IFORM_SHR_MEMb_CL_DEFINED   1
 
#define XED_IFORM_SHR_MEMb_IMMb_DEFINED   1
 
#define XED_IFORM_SHR_MEMb_ONE_DEFINED   1
 
#define XED_IFORM_SHR_MEMi8_CL_APX_DEFINED   1
 
#define XED_IFORM_SHR_MEMi8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SHR_MEMi8_ONE_APX_DEFINED   1
 
#define XED_IFORM_SHR_MEMv_CL_APX_DEFINED   1
 
#define XED_IFORM_SHR_MEMv_CL_DEFINED   1
 
#define XED_IFORM_SHR_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SHR_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_SHR_MEMv_ONE_APX_DEFINED   1
 
#define XED_IFORM_SHR_MEMv_ONE_DEFINED   1
 
#define XED_IFORM_SHRD_GPRv_GPRv_CL_APX_DEFINED   1
 
#define XED_IFORM_SHRD_GPRv_GPRv_CL_DEFINED   1
 
#define XED_IFORM_SHRD_GPRv_GPRv_GPRv_CL_APX_DEFINED   1
 
#define XED_IFORM_SHRD_GPRv_GPRv_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SHRD_GPRv_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SHRD_GPRv_GPRv_IMMb_DEFINED   1
 
#define XED_IFORM_SHRD_GPRv_MEMv_GPRv_CL_APX_DEFINED   1
 
#define XED_IFORM_SHRD_GPRv_MEMv_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SHRD_MEMv_GPRv_CL_APX_DEFINED   1
 
#define XED_IFORM_SHRD_MEMv_GPRv_CL_DEFINED   1
 
#define XED_IFORM_SHRD_MEMv_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SHRD_MEMv_GPRv_IMMb_DEFINED   1
 
#define XED_IFORM_SHRX_GPR32d_GPR32d_GPR32d_DEFINED   1
 
#define XED_IFORM_SHRX_GPR32d_MEMd_GPR32d_DEFINED   1
 
#define XED_IFORM_SHRX_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED   1
 
#define XED_IFORM_SHRX_GPR32i32_MEMi32_GPR32i32_APX_DEFINED   1
 
#define XED_IFORM_SHRX_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED   1
 
#define XED_IFORM_SHRX_GPR64i64_MEMi64_GPR64i64_APX_DEFINED   1
 
#define XED_IFORM_SHRX_GPR64q_GPR64q_GPR64q_DEFINED   1
 
#define XED_IFORM_SHRX_GPR64q_MEMq_GPR64q_DEFINED   1
 
#define XED_IFORM_SHUFPD_XMMpd_MEMpd_IMMb_DEFINED   1
 
#define XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb_DEFINED   1
 
#define XED_IFORM_SHUFPS_XMMps_MEMps_IMMb_DEFINED   1
 
#define XED_IFORM_SHUFPS_XMMps_XMMps_IMMb_DEFINED   1
 
#define XED_IFORM_SIDT_MEMs64_DEFINED   1
 
#define XED_IFORM_SIDT_MEMs_DEFINED   1
 
#define XED_IFORM_SKINIT_EAX_DEFINED   1
 
#define XED_IFORM_SLDT_GPRv_DEFINED   1
 
#define XED_IFORM_SLDT_MEMw_DEFINED   1
 
#define XED_IFORM_SLWPCB_GPRyy_DEFINED   1
 
#define XED_IFORM_SMSW_GPRv_DEFINED   1
 
#define XED_IFORM_SMSW_MEMw_DEFINED   1
 
#define XED_IFORM_SQRTPD_XMMpd_MEMpd_DEFINED   1
 
#define XED_IFORM_SQRTPD_XMMpd_XMMpd_DEFINED   1
 
#define XED_IFORM_SQRTPS_XMMps_MEMps_DEFINED   1
 
#define XED_IFORM_SQRTPS_XMMps_XMMps_DEFINED   1
 
#define XED_IFORM_SQRTSD_XMMsd_MEMsd_DEFINED   1
 
#define XED_IFORM_SQRTSD_XMMsd_XMMsd_DEFINED   1
 
#define XED_IFORM_SQRTSS_XMMss_MEMss_DEFINED   1
 
#define XED_IFORM_SQRTSS_XMMss_XMMss_DEFINED   1
 
#define XED_IFORM_STAC_DEFINED   1
 
#define XED_IFORM_STC_DEFINED   1
 
#define XED_IFORM_STD_DEFINED   1
 
#define XED_IFORM_STGI_DEFINED   1
 
#define XED_IFORM_STI_DEFINED   1
 
#define XED_IFORM_STMXCSR_MEMd_DEFINED   1
 
#define XED_IFORM_STOSB_DEFINED   1
 
#define XED_IFORM_STOSD_DEFINED   1
 
#define XED_IFORM_STOSQ_DEFINED   1
 
#define XED_IFORM_STOSW_DEFINED   1
 
#define XED_IFORM_STR_GPRv_DEFINED   1
 
#define XED_IFORM_STR_MEMw_DEFINED   1
 
#define XED_IFORM_STTILECFG_MEM_APX_DEFINED   1
 
#define XED_IFORM_STTILECFG_MEM_DEFINED   1
 
#define XED_IFORM_STUI_DEFINED   1
 
#define XED_IFORM_SUB_AL_IMMb_DEFINED   1
 
#define XED_IFORM_SUB_GPR8_GPR8_28_DEFINED   1
 
#define XED_IFORM_SUB_GPR8_GPR8_2A_DEFINED   1
 
#define XED_IFORM_SUB_GPR8_IMMb_80r5_DEFINED   1
 
#define XED_IFORM_SUB_GPR8_IMMb_82r5_DEFINED   1
 
#define XED_IFORM_SUB_GPR8_MEMb_DEFINED   1
 
#define XED_IFORM_SUB_GPR8i8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_SUB_GPR8i8_GPR8i8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_SUB_GPR8i8_GPR8i8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SUB_GPR8i8_GPR8i8_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_SUB_GPR8i8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SUB_GPR8i8_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_SUB_GPR8i8_MEMi8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_SUB_GPR8i8_MEMi8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SUB_GPRv_GPRv_29_DEFINED   1
 
#define XED_IFORM_SUB_GPRv_GPRv_2B_DEFINED   1
 
#define XED_IFORM_SUB_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_SUB_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_SUB_GPRv_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SUB_GPRv_GPRv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_SUB_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_SUB_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SUB_GPRv_IMMb_DEFINED   1
 
#define XED_IFORM_SUB_GPRv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_SUB_GPRv_IMMz_DEFINED   1
 
#define XED_IFORM_SUB_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_SUB_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_SUB_GPRv_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_SUB_GPRv_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SUB_GPRv_MEMv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_SUB_LOCK_MEMb_GPR8_DEFINED   1
 
#define XED_IFORM_SUB_LOCK_MEMb_IMMb_80r5_DEFINED   1
 
#define XED_IFORM_SUB_LOCK_MEMb_IMMb_82r5_DEFINED   1
 
#define XED_IFORM_SUB_LOCK_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_SUB_LOCK_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_SUB_LOCK_MEMv_IMMz_DEFINED   1
 
#define XED_IFORM_SUB_MEMb_GPR8_DEFINED   1
 
#define XED_IFORM_SUB_MEMb_IMMb_80r5_DEFINED   1
 
#define XED_IFORM_SUB_MEMb_IMMb_82r5_DEFINED   1
 
#define XED_IFORM_SUB_MEMi8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_SUB_MEMi8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SUB_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_SUB_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_SUB_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_SUB_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_SUB_MEMv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_SUB_MEMv_IMMz_DEFINED   1
 
#define XED_IFORM_SUB_OrAX_IMMz_DEFINED   1
 
#define XED_IFORM_SUBPD_XMMpd_MEMpd_DEFINED   1
 
#define XED_IFORM_SUBPD_XMMpd_XMMpd_DEFINED   1
 
#define XED_IFORM_SUBPS_XMMps_MEMps_DEFINED   1
 
#define XED_IFORM_SUBPS_XMMps_XMMps_DEFINED   1
 
#define XED_IFORM_SUBSD_XMMsd_MEMsd_DEFINED   1
 
#define XED_IFORM_SUBSD_XMMsd_XMMsd_DEFINED   1
 
#define XED_IFORM_SUBSS_XMMss_MEMss_DEFINED   1
 
#define XED_IFORM_SUBSS_XMMss_XMMss_DEFINED   1
 
#define XED_IFORM_SWAPGS_DEFINED   1
 
#define XED_IFORM_SYSCALL_AMD_DEFINED   1
 
#define XED_IFORM_SYSCALL_DEFINED   1
 
#define XED_IFORM_SYSENTER_DEFINED   1
 
#define XED_IFORM_SYSEXIT_DEFINED   1
 
#define XED_IFORM_SYSRET64_DEFINED   1
 
#define XED_IFORM_SYSRET_AMD_DEFINED   1
 
#define XED_IFORM_SYSRET_DEFINED   1
 
#define XED_IFORM_T1MSKC_GPR32d_GPR32d_DEFINED   1
 
#define XED_IFORM_T1MSKC_GPR32d_MEMd_DEFINED   1
 
#define XED_IFORM_T1MSKC_GPRyy_GPRyy_DEFINED   1
 
#define XED_IFORM_T1MSKC_GPRyy_MEMy_DEFINED   1
 
#define XED_IFORM_T2RPNTLVWZ0_TMM2u16_MEMu16_APX_DEFINED   1
 
#define XED_IFORM_T2RPNTLVWZ0_TMM2u16_MEMu16_DEFINED   1
 
#define XED_IFORM_T2RPNTLVWZ0RS_TMM2u16_MEMu16_APX_DEFINED   1
 
#define XED_IFORM_T2RPNTLVWZ0RS_TMM2u16_MEMu16_DEFINED   1
 
#define XED_IFORM_T2RPNTLVWZ0RST1_TMM2u16_MEMu16_APX_DEFINED   1
 
#define XED_IFORM_T2RPNTLVWZ0RST1_TMM2u16_MEMu16_DEFINED   1
 
#define XED_IFORM_T2RPNTLVWZ0T1_TMM2u16_MEMu16_APX_DEFINED   1
 
#define XED_IFORM_T2RPNTLVWZ0T1_TMM2u16_MEMu16_DEFINED   1
 
#define XED_IFORM_T2RPNTLVWZ1_TMM2u16_MEMu16_APX_DEFINED   1
 
#define XED_IFORM_T2RPNTLVWZ1_TMM2u16_MEMu16_DEFINED   1
 
#define XED_IFORM_T2RPNTLVWZ1RS_TMM2u16_MEMu16_APX_DEFINED   1
 
#define XED_IFORM_T2RPNTLVWZ1RS_TMM2u16_MEMu16_DEFINED   1
 
#define XED_IFORM_T2RPNTLVWZ1RST1_TMM2u16_MEMu16_APX_DEFINED   1
 
#define XED_IFORM_T2RPNTLVWZ1RST1_TMM2u16_MEMu16_DEFINED   1
 
#define XED_IFORM_T2RPNTLVWZ1T1_TMM2u16_MEMu16_APX_DEFINED   1
 
#define XED_IFORM_T2RPNTLVWZ1T1_TMM2u16_MEMu16_DEFINED   1
 
#define XED_IFORM_TCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED   1
 
#define XED_IFORM_TCMMRLFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED   1
 
#define XED_IFORM_TCONJTCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED   1
 
#define XED_IFORM_TCONJTFP16_TMM2f16_TMM2f16_DEFINED   1
 
#define XED_IFORM_TCVTROWD2PS_ZMMf32_TMMu32_GPR32u32_DEFINED   1
 
#define XED_IFORM_TCVTROWD2PS_ZMMf32_TMMu32_IMM8_DEFINED   1
 
#define XED_IFORM_TCVTROWPS2BF16H_ZMMbf16_TMMf32_GPR32u32_DEFINED   1
 
#define XED_IFORM_TCVTROWPS2BF16H_ZMMbf16_TMMf32_IMM8_DEFINED   1
 
#define XED_IFORM_TCVTROWPS2BF16L_ZMMbf16_TMMf32_GPR32u32_DEFINED   1
 
#define XED_IFORM_TCVTROWPS2BF16L_ZMMbf16_TMMf32_IMM8_DEFINED   1
 
#define XED_IFORM_TCVTROWPS2PHH_ZMMf16_TMMf32_GPR32u32_DEFINED   1
 
#define XED_IFORM_TCVTROWPS2PHH_ZMMf16_TMMf32_IMM8_DEFINED   1
 
#define XED_IFORM_TCVTROWPS2PHL_ZMMf16_TMMf32_GPR32u32_DEFINED   1
 
#define XED_IFORM_TCVTROWPS2PHL_ZMMf16_TMMf32_IMM8_DEFINED   1
 
#define XED_IFORM_TDCALL_DEFINED   1
 
#define XED_IFORM_TDPBF16PS_TMMf32_TMM2bf16_TMM2bf16_DEFINED   1
 
#define XED_IFORM_TDPBF8PS_TMMf32_TMM4bf8_TMM4bf8_DEFINED   1
 
#define XED_IFORM_TDPBHF8PS_TMMf32_TMM4bf8_TMM4hf8_DEFINED   1
 
#define XED_IFORM_TDPBSSD_TMMi32_TMM4i8_TMM4i8_DEFINED   1
 
#define XED_IFORM_TDPBSUD_TMMi32_TMM4i8_TMM4u8_DEFINED   1
 
#define XED_IFORM_TDPBUSD_TMMi32_TMM4u8_TMM4i8_DEFINED   1
 
#define XED_IFORM_TDPBUUD_TMMu32_TMM4u8_TMM4u8_DEFINED   1
 
#define XED_IFORM_TDPFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED   1
 
#define XED_IFORM_TDPHBF8PS_TMMf32_TMM4hf8_TMM4bf8_DEFINED   1
 
#define XED_IFORM_TDPHF8PS_TMMf32_TMM4hf8_TMM4hf8_DEFINED   1
 
#define XED_IFORM_TEST_AL_IMMb_DEFINED   1
 
#define XED_IFORM_TEST_GPR8_GPR8_DEFINED   1
 
#define XED_IFORM_TEST_GPR8_IMMb_F6r0_DEFINED   1
 
#define XED_IFORM_TEST_GPR8_IMMb_F6r1_DEFINED   1
 
#define XED_IFORM_TEST_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_TEST_GPRv_IMMz_F7r0_DEFINED   1
 
#define XED_IFORM_TEST_GPRv_IMMz_F7r1_DEFINED   1
 
#define XED_IFORM_TEST_MEMb_GPR8_DEFINED   1
 
#define XED_IFORM_TEST_MEMb_IMMb_F6r0_DEFINED   1
 
#define XED_IFORM_TEST_MEMb_IMMb_F6r1_DEFINED   1
 
#define XED_IFORM_TEST_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_TEST_MEMv_IMMz_F7r0_DEFINED   1
 
#define XED_IFORM_TEST_MEMv_IMMz_F7r1_DEFINED   1
 
#define XED_IFORM_TEST_OrAX_IMMz_DEFINED   1
 
#define XED_IFORM_TESTUI_DEFINED   1
 
#define XED_IFORM_TILELOADD_TMMu32_MEMu32_APX_DEFINED   1
 
#define XED_IFORM_TILELOADD_TMMu32_MEMu32_DEFINED   1
 
#define XED_IFORM_TILELOADDRS_TMMu32_MEMu32_APX_DEFINED   1
 
#define XED_IFORM_TILELOADDRS_TMMu32_MEMu32_DEFINED   1
 
#define XED_IFORM_TILELOADDRST1_TMMu32_MEMu32_APX_DEFINED   1
 
#define XED_IFORM_TILELOADDRST1_TMMu32_MEMu32_DEFINED   1
 
#define XED_IFORM_TILELOADDT1_TMMu32_MEMu32_APX_DEFINED   1
 
#define XED_IFORM_TILELOADDT1_TMMu32_MEMu32_DEFINED   1
 
#define XED_IFORM_TILEMOVROW_ZMMu8_TMMu8_GPR32u32_DEFINED   1
 
#define XED_IFORM_TILEMOVROW_ZMMu8_TMMu8_IMM8_DEFINED   1
 
#define XED_IFORM_TILERELEASE_DEFINED   1
 
#define XED_IFORM_TILESTORED_MEMu32_TMMu32_APX_DEFINED   1
 
#define XED_IFORM_TILESTORED_MEMu32_TMMu32_DEFINED   1
 
#define XED_IFORM_TILEZERO_TMMu32_DEFINED   1
 
#define XED_IFORM_TLBSYNC_DEFINED   1
 
#define XED_IFORM_TMMULTF32PS_TMMf32_TMMf32_TMMf32_DEFINED   1
 
#define XED_IFORM_TPAUSE_GPR32u32_DEFINED   1
 
#define XED_IFORM_TTCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED   1
 
#define XED_IFORM_TTCMMRLFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED   1
 
#define XED_IFORM_TTDPBF16PS_TMMf32_TMMbf16_TMMbf16_DEFINED   1
 
#define XED_IFORM_TTDPFP16PS_TMMf32_TMMf16_TMMf16_DEFINED   1
 
#define XED_IFORM_TTMMULTF32PS_TMMf32_TMMf32_TMMf32_DEFINED   1
 
#define XED_IFORM_TTRANSPOSED_TMMu32_TMMu32_DEFINED   1
 
#define XED_IFORM_TZCNT_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_TZCNT_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_TZCNT_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_TZCNT_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_TZMSK_GPR32d_GPR32d_DEFINED   1
 
#define XED_IFORM_TZMSK_GPR32d_MEMd_DEFINED   1
 
#define XED_IFORM_TZMSK_GPRyy_GPRyy_DEFINED   1
 
#define XED_IFORM_TZMSK_GPRyy_MEMy_DEFINED   1
 
#define XED_IFORM_UCOMISD_XMMsd_MEMsd_DEFINED   1
 
#define XED_IFORM_UCOMISD_XMMsd_XMMsd_DEFINED   1
 
#define XED_IFORM_UCOMISS_XMMss_MEMss_DEFINED   1
 
#define XED_IFORM_UCOMISS_XMMss_XMMss_DEFINED   1
 
#define XED_IFORM_UD0_DEFINED   1
 
#define XED_IFORM_UD0_GPR32_GPR32_DEFINED   1
 
#define XED_IFORM_UD0_GPR32_MEMd_DEFINED   1
 
#define XED_IFORM_UD1_GPR32_GPR32_DEFINED   1
 
#define XED_IFORM_UD1_GPR32_MEMd_DEFINED   1
 
#define XED_IFORM_UD2_DEFINED   1
 
#define XED_IFORM_UIRET_DEFINED   1
 
#define XED_IFORM_UMONITOR_GPRa_DEFINED   1
 
#define XED_IFORM_UMWAIT_GPR32_DEFINED   1
 
#define XED_IFORM_UNPCKHPD_XMMpd_MEMdq_DEFINED   1
 
#define XED_IFORM_UNPCKHPD_XMMpd_XMMq_DEFINED   1
 
#define XED_IFORM_UNPCKHPS_XMMps_MEMdq_DEFINED   1
 
#define XED_IFORM_UNPCKHPS_XMMps_XMMdq_DEFINED   1
 
#define XED_IFORM_UNPCKLPD_XMMpd_MEMdq_DEFINED   1
 
#define XED_IFORM_UNPCKLPD_XMMpd_XMMq_DEFINED   1
 
#define XED_IFORM_UNPCKLPS_XMMps_MEMdq_DEFINED   1
 
#define XED_IFORM_UNPCKLPS_XMMps_XMMq_DEFINED   1
 
#define XED_IFORM_URDMSR_GPR64u64_GPR64u64_APX_DEFINED   1
 
#define XED_IFORM_URDMSR_GPR64u64_GPR64u64_DEFINED   1
 
#define XED_IFORM_URDMSR_GPR64u64_IMM32_APX_DEFINED   1
 
#define XED_IFORM_URDMSR_GPR64u64_IMM32_DEFINED   1
 
#define XED_IFORM_UWRMSR_GPR64u64_GPR64u64_APX_DEFINED   1
 
#define XED_IFORM_UWRMSR_GPR64u64_GPR64u64_DEFINED   1
 
#define XED_IFORM_UWRMSR_IMM32_GPR64u64_APX_DEFINED   1
 
#define XED_IFORM_UWRMSR_IMM32_GPR64u64_DEFINED   1
 
#define XED_IFORM_V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VADDBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VADDBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VADDBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VADDBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VADDBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VADDBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VADDPS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VADDPS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VADDSD_XMMdq_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_VADDSD_XMMdq_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd_DEFINED   1
 
#define XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd_DEFINED   1
 
#define XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VADDSUBPD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VADDSUBPD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VADDSUBPS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VADDSUBPS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VADDSUBPS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VADDSUBPS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VAESDEC_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VAESDEC_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VAESDEC_XMMu128_XMMu128_MEMu128_AVX512_DEFINED   1
 
#define XED_IFORM_VAESDEC_XMMu128_XMMu128_XMMu128_AVX512_DEFINED   1
 
#define XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_AVX512_DEFINED   1
 
#define XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_DEFINED   1
 
#define XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_AVX512_DEFINED   1
 
#define XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_DEFINED   1
 
#define XED_IFORM_VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED   1
 
#define XED_IFORM_VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED   1
 
#define XED_IFORM_VAESDECLAST_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VAESDECLAST_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512_DEFINED   1
 
#define XED_IFORM_VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512_DEFINED   1
 
#define XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512_DEFINED   1
 
#define XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_DEFINED   1
 
#define XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512_DEFINED   1
 
#define XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_DEFINED   1
 
#define XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED   1
 
#define XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED   1
 
#define XED_IFORM_VAESENC_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VAESENC_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VAESENC_XMMu128_XMMu128_MEMu128_AVX512_DEFINED   1
 
#define XED_IFORM_VAESENC_XMMu128_XMMu128_XMMu128_AVX512_DEFINED   1
 
#define XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_AVX512_DEFINED   1
 
#define XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_DEFINED   1
 
#define XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_AVX512_DEFINED   1
 
#define XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_DEFINED   1
 
#define XED_IFORM_VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED   1
 
#define XED_IFORM_VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED   1
 
#define XED_IFORM_VAESENCLAST_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VAESENCLAST_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512_DEFINED   1
 
#define XED_IFORM_VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512_DEFINED   1
 
#define XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512_DEFINED   1
 
#define XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_DEFINED   1
 
#define XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512_DEFINED   1
 
#define XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_DEFINED   1
 
#define XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED   1
 
#define XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED   1
 
#define XED_IFORM_VAESIMC_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VAESIMC_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VAESKEYGENASSIST_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VAESKEYGENASSIST_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VANDNPD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VANDNPD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VANDNPD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VANDNPD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VANDNPS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VANDNPS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VANDNPS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VANDNPS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VANDPD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VANDPD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VANDPD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VANDPD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VANDPS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VANDPS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VANDPS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VANDPS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VBCSTNEBF162PS_XMMf32_MEMbf16_DEFINED   1
 
#define XED_IFORM_VBCSTNEBF162PS_YMMf32_MEMbf16_DEFINED   1
 
#define XED_IFORM_VBCSTNESH2PS_XMMf32_MEMf16_DEFINED   1
 
#define XED_IFORM_VBCSTNESH2PS_YMMf32_MEMf16_DEFINED   1
 
#define XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VBROADCASTF128_YMMqq_MEMdq_DEFINED   1
 
#define XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTI128_YMMqq_MEMdq_DEFINED   1
 
#define XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTSD_YMMqq_MEMq_DEFINED   1
 
#define XED_IFORM_VBROADCASTSD_YMMqq_XMMdq_DEFINED   1
 
#define XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTSS_XMMdq_MEMd_DEFINED   1
 
#define XED_IFORM_VBROADCASTSS_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTSS_YMMqq_MEMd_DEFINED   1
 
#define XED_IFORM_VBROADCASTSS_YMMqq_XMMdq_DEFINED   1
 
#define XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_XMMbf16_MEMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_XMMbf16_XMMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_YMMbf16_MEMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_YMMbf16_YMMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_ZMMbf16_MEMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_ZMMbf16_ZMMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VCMPPD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VCMPPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb_DEFINED   1
 
#define XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb_DEFINED   1
 
#define XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb_DEFINED   1
 
#define XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb_DEFINED   1
 
#define XED_IFORM_VCOMISBF16_XMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCOMISBF16_XMMbf16_XMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCOMISD_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCOMISD_XMMq_MEMq_DEFINED   1
 
#define XED_IFORM_VCOMISD_XMMq_XMMq_DEFINED   1
 
#define XED_IFORM_VCOMISH_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCOMISS_XMMd_MEMd_DEFINED   1
 
#define XED_IFORM_VCOMISS_XMMd_XMMd_DEFINED   1
 
#define XED_IFORM_VCOMISS_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCOMXSD_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCOMXSD_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCOMXSH_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCOMXSH_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCOMXSS_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCOMXSS_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PH2BF8_XMMbf8_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PH2BF8_XMMbf8_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PH2BF8_YMMbf8_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PH2BF8_YMMbf8_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PH2BF8_ZMMbf8_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PH2BF8_ZMMbf8_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PH2BF8S_XMMbf8_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PH2BF8S_XMMbf8_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PH2BF8S_YMMbf8_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PH2BF8S_YMMbf8_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PH2BF8S_ZMMbf8_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PH2BF8S_ZMMbf8_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PH2HF8_XMMhf8_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PH2HF8_XMMhf8_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PH2HF8_YMMhf8_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PH2HF8_YMMhf8_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PH2HF8_ZMMhf8_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PH2HF8_ZMMhf8_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PH2HF8S_XMMhf8_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PH2HF8S_XMMhf8_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PH2HF8S_YMMhf8_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PH2HF8S_YMMhf8_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PH2HF8S_ZMMhf8_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PH2HF8S_ZMMhf8_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PS2PHX_XMMf16_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PS2PHX_XMMf16_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PS2PHX_YMMf16_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PS2PHX_YMMf16_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PS2PHX_ZMMf16_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVT2PS2PHX_ZMMf16_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTBF162IBS_XMMi8_MASKmskw_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTBF162IBS_XMMi8_MASKmskw_XMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTBF162IBS_YMMi8_MASKmskw_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTBF162IBS_YMMi8_MASKmskw_YMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTBF162IBS_ZMMi8_MASKmskw_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTBF162IBS_ZMMi8_MASKmskw_ZMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTBF162IUBS_XMMu8_MASKmskw_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTBF162IUBS_XMMu8_MASKmskw_XMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTBF162IUBS_YMMu8_MASKmskw_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTBF162IUBS_YMMu8_MASKmskw_YMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTBF162IUBS_ZMMu8_MASKmskw_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTBF162IUBS_ZMMu8_MASKmskw_ZMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_XMM2i8_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_YMM2i8_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTBIASPH2BF8_YMMbf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTBIASPH2BF8_YMMbf8_MASKmskw_ZMM2i8_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_XMM2i8_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_YMM2i8_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTBIASPH2BF8S_YMMbf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTBIASPH2BF8S_YMMbf8_MASKmskw_ZMM2i8_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_XMM2i8_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_YMM2i8_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTBIASPH2HF8_YMMhf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTBIASPH2HF8_YMMhf8_MASKmskw_ZMM2i8_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_XMM2i8_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_YMM2i8_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTBIASPH2HF8S_YMMhf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTBIASPH2HF8S_YMMhf8_MASKmskw_ZMM2i8_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTDQ2PD_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_VCVTDQ2PD_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq_DEFINED   1
 
#define XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq_DEFINED   1
 
#define XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTDQ2PS_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VCVTDQ2PS_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTHF82PH_XMMf16_MASKmskw_MEMhf8_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTHF82PH_XMMf16_MASKmskw_XMMhf8_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTHF82PH_YMMf16_MASKmskw_MEMhf8_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTHF82PH_YMMf16_MASKmskw_XMMhf8_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTHF82PH_ZMMf16_MASKmskw_MEMhf8_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTHF82PH_ZMMf16_MASKmskw_YMMhf8_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTNEEBF162PS_XMMf32_MEM2bf16_DEFINED   1
 
#define XED_IFORM_VCVTNEEBF162PS_YMMf32_MEM2bf16_DEFINED   1
 
#define XED_IFORM_VCVTNEEPH2PS_XMMf32_MEM2f16_DEFINED   1
 
#define XED_IFORM_VCVTNEEPH2PS_YMMf32_MEM2f16_DEFINED   1
 
#define XED_IFORM_VCVTNEOBF162PS_XMMf32_MEM2bf16_DEFINED   1
 
#define XED_IFORM_VCVTNEOBF162PS_YMMf32_MEM2bf16_DEFINED   1
 
#define XED_IFORM_VCVTNEOPH2PS_XMMf32_MEM2f16_DEFINED   1
 
#define XED_IFORM_VCVTNEOPH2PS_YMMf32_MEM2f16_DEFINED   1
 
#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MEMf32_VL128_DEFINED   1
 
#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MEMf32_VL256_DEFINED   1
 
#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_XMMf32_DEFINED   1
 
#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_YMMf32_DEFINED   1
 
#define XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq_DEFINED   1
 
#define XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq_DEFINED   1
 
#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPD2PS_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VCVTPD2PS_XMMdq_MEMqq_DEFINED   1
 
#define XED_IFORM_VCVTPD2PS_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VCVTPD2PS_XMMdq_YMMqq_DEFINED   1
 
#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2BF8_XMMbf8_MASKmskw_MEMf16_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTPH2BF8_XMMbf8_MASKmskw_MEMf16_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTPH2BF8_XMMbf8_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2BF8_XMMbf8_MASKmskw_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2BF8_YMMbf8_MASKmskw_MEMf16_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTPH2BF8_YMMbf8_MASKmskw_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2BF8S_XMMbf8_MASKmskw_MEMf16_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTPH2BF8S_XMMbf8_MASKmskw_MEMf16_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTPH2BF8S_XMMbf8_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2BF8S_XMMbf8_MASKmskw_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2BF8S_YMMbf8_MASKmskw_MEMf16_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTPH2BF8S_YMMbf8_MASKmskw_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2HF8_XMMhf8_MASKmskw_MEMf16_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTPH2HF8_XMMhf8_MASKmskw_MEMf16_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTPH2HF8_XMMhf8_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2HF8_XMMhf8_MASKmskw_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2HF8_YMMhf8_MASKmskw_MEMf16_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTPH2HF8_YMMhf8_MASKmskw_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2HF8S_XMMhf8_MASKmskw_MEMf16_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTPH2HF8S_XMMhf8_MASKmskw_MEMf16_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTPH2HF8S_XMMhf8_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2HF8S_XMMhf8_MASKmskw_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2HF8S_YMMhf8_MASKmskw_MEMf16_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTPH2HF8S_YMMhf8_MASKmskw_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2IBS_XMMi8_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2IBS_XMMi8_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2IBS_YMMi8_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2IBS_YMMi8_MASKmskw_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2IBS_ZMMi8_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2IBS_ZMMi8_MASKmskw_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2IUBS_XMMu8_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2IUBS_XMMu8_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2IUBS_YMMu8_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2IUBS_YMMu8_MASKmskw_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2IUBS_ZMMu8_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2IUBS_ZMMu8_MASKmskw_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2PS_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_VCVTPH2PS_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2PS_YMMqq_MEMdq_DEFINED   1
 
#define XED_IFORM_VCVTPH2PS_YMMqq_XMMdq_DEFINED   1
 
#define XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2IBS_XMMi8_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2IBS_XMMi8_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2IBS_YMMi8_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2IBS_YMMi8_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2IBS_ZMMi8_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2IBS_ZMMi8_MASKmskw_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2IUBS_XMMu8_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2IUBS_XMMu8_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2IUBS_YMMu8_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2IUBS_YMMu8_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2IUBS_ZMMu8_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2IUBS_ZMMu8_MASKmskw_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2PD_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_VCVTPS2PD_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2PD_YMMqq_MEMdq_DEFINED   1
 
#define XED_IFORM_VCVTPS2PD_YMMqq_XMMdq_DEFINED   1
 
#define XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTQQ2PD_XMMf64_MASKmskw_MEMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTQQ2PD_XMMf64_MASKmskw_XMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTQQ2PD_YMMf64_MASKmskw_MEMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTQQ2PD_YMMf64_MASKmskw_YMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTQQ2PD_ZMMf64_MASKmskw_MEMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTQQ2PD_ZMMf64_MASKmskw_ZMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSD2SI_GPR32d_MEMq_DEFINED   1
 
#define XED_IFORM_VCVTSD2SI_GPR32d_XMMq_DEFINED   1
 
#define XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSD2SI_GPR64q_MEMq_DEFINED   1
 
#define XED_IFORM_VCVTSD2SI_GPR64q_XMMq_DEFINED   1
 
#define XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSH2SI_GPR32i32_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSH2SI_GPR64i64_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSH2USI_GPR32u32_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSH2USI_GPR64u64_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d_DEFINED   1
 
#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q_DEFINED   1
 
#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd_DEFINED   1
 
#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d_DEFINED   1
 
#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q_DEFINED   1
 
#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd_DEFINED   1
 
#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd_DEFINED   1
 
#define XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd_DEFINED   1
 
#define XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSS2SI_GPR32d_MEMd_DEFINED   1
 
#define XED_IFORM_VCVTSS2SI_GPR32d_XMMd_DEFINED   1
 
#define XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSS2SI_GPR64q_MEMd_DEFINED   1
 
#define XED_IFORM_VCVTSS2SI_GPR64q_XMMd_DEFINED   1
 
#define XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTBF162IBS_XMMi8_MASKmskw_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTBF162IBS_XMMi8_MASKmskw_XMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTBF162IBS_YMMi8_MASKmskw_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTBF162IBS_YMMi8_MASKmskw_YMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTBF162IBS_ZMMi8_MASKmskw_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTBF162IBS_ZMMi8_MASKmskw_ZMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTBF162IUBS_XMMu8_MASKmskw_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTBF162IUBS_XMMu8_MASKmskw_XMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTBF162IUBS_YMMu8_MASKmskw_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTBF162IUBS_YMMu8_MASKmskw_YMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTBF162IUBS_ZMMu8_MASKmskw_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTBF162IUBS_ZMMu8_MASKmskw_ZMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq_DEFINED   1
 
#define XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq_DEFINED   1
 
#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2DQS_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2DQS_YMMi32_MASKmskw_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2QQS_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2QQS_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2QQS_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2QQS_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2QQS_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2QQS_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2UDQS_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2UDQS_YMMu32_MASKmskw_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2UQQS_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2UQQS_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2UQQS_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2UQQS_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2UQQS_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPD2UQQS_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2IBS_XMMi8_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2IBS_XMMi8_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2IBS_YMMi8_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2IBS_YMMi8_MASKmskw_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2IBS_ZMMi8_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2IBS_ZMMi8_MASKmskw_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2IUBS_XMMu8_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2IUBS_XMMu8_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2IUBS_YMMu8_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2IUBS_YMMu8_MASKmskw_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2IUBS_ZMMu8_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2IUBS_ZMMu8_MASKmskw_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2DQS_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2DQS_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2DQS_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2DQS_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2DQS_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2DQS_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2IBS_XMMi8_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2IBS_XMMi8_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2IBS_YMMi8_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2IBS_YMMi8_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2IBS_ZMMi8_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2IBS_ZMMi8_MASKmskw_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2IUBS_XMMu8_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2IUBS_XMMu8_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2IUBS_YMMu8_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2IUBS_YMMu8_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2IUBS_ZMMu8_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2IUBS_ZMMu8_MASKmskw_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2QQS_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2QQS_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2QQS_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2QQS_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2QQS_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2QQS_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2UDQS_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2UDQS_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2UDQS_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2UDQS_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2UDQS_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2UDQS_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2UQQS_XMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2UQQS_XMMu64_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2UQQS_YMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2UQQS_YMMu64_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2UQQS_ZMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTPS2UQQS_ZMMu64_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSD2SI_GPR32d_MEMq_DEFINED   1
 
#define XED_IFORM_VCVTTSD2SI_GPR32d_XMMq_DEFINED   1
 
#define XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSD2SI_GPR64q_MEMq_DEFINED   1
 
#define XED_IFORM_VCVTTSD2SI_GPR64q_XMMq_DEFINED   1
 
#define XED_IFORM_VCVTTSD2SIS_GPR32i32_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSD2SIS_GPR32i32_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSD2SIS_GPR64i64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSD2SIS_GPR64i64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSD2USIS_GPR32u32_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSD2USIS_GPR32u32_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSD2USIS_GPR64u64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSD2USIS_GPR64u64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSH2SI_GPR32i32_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSH2SI_GPR64i64_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSH2USI_GPR32u32_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSH2USI_GPR64u64_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSS2SI_GPR32d_MEMd_DEFINED   1
 
#define XED_IFORM_VCVTTSS2SI_GPR32d_XMMd_DEFINED   1
 
#define XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSS2SI_GPR64q_MEMd_DEFINED   1
 
#define XED_IFORM_VCVTTSS2SI_GPR64q_XMMd_DEFINED   1
 
#define XED_IFORM_VCVTTSS2SIS_GPR32i32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSS2SIS_GPR32i32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSS2SIS_GPR64i64_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSS2SIS_GPR64i64_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSS2USIS_GPR32u32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSS2USIS_GPR32u32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSS2USIS_GPR64u64_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTTSS2USIS_GPR64u64_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVPS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VDIVPS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVSD_XMMdq_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_VDIVSD_XMMdq_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd_DEFINED   1
 
#define XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd_DEFINED   1
 
#define XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VDPPHPS_XMMf32_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VDPPHPS_XMMf32_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VDPPHPS_YMMf32_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VDPPHPS_YMMf32_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VDPPHPS_ZMMf32_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VDPPHPS_ZMMf32_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VERR_GPR16_DEFINED   1
 
#define XED_IFORM_VERR_MEMw_DEFINED   1
 
#define XED_IFORM_VERW_GPR16_DEFINED   1
 
#define XED_IFORM_VERW_MEMw_DEFINED   1
 
#define XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER_DEFINED   1
 
#define XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER_DEFINED   1
 
#define XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER_DEFINED   1
 
#define XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER_DEFINED   1
 
#define XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VEXTRACTF128_MEMdq_YMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VEXTRACTI128_MEMdq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VEXTRACTPS_GPR32_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VEXTRACTPS_MEMd_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132PS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMADD132PS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132SD_XMMdq_XMMq_MEMq_DEFINED   1
 
#define XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq_DEFINED   1
 
#define XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd_DEFINED   1
 
#define XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd_DEFINED   1
 
#define XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213PS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMADD213PS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213SD_XMMdq_XMMq_MEMq_DEFINED   1
 
#define XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq_DEFINED   1
 
#define XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd_DEFINED   1
 
#define XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd_DEFINED   1
 
#define XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231PS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMADD231PS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231SD_XMMdq_XMMq_MEMq_DEFINED   1
 
#define XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq_DEFINED   1
 
#define XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd_DEFINED   1
 
#define XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd_DEFINED   1
 
#define XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMADDSD_XMMdq_XMMq_MEMq_XMMq_DEFINED   1
 
#define XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_MEMq_DEFINED   1
 
#define XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_XMMq_DEFINED   1
 
#define XED_IFORM_VFMADDSS_XMMdq_XMMd_MEMd_XMMd_DEFINED   1
 
#define XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_MEMd_DEFINED   1
 
#define XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_XMMd_DEFINED   1
 
#define XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMSUB132BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132SD_XMMdq_XMMq_MEMq_DEFINED   1
 
#define XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq_DEFINED   1
 
#define XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd_DEFINED   1
 
#define XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd_DEFINED   1
 
#define XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213SD_XMMdq_XMMq_MEMq_DEFINED   1
 
#define XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq_DEFINED   1
 
#define XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd_DEFINED   1
 
#define XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd_DEFINED   1
 
#define XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231SD_XMMdq_XMMq_MEMq_DEFINED   1
 
#define XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq_DEFINED   1
 
#define XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd_DEFINED   1
 
#define XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd_DEFINED   1
 
#define XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFMSUBSD_XMMdq_XMMq_MEMq_XMMq_DEFINED   1
 
#define XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_MEMq_DEFINED   1
 
#define XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_XMMq_DEFINED   1
 
#define XED_IFORM_VFMSUBSS_XMMdq_XMMd_MEMd_XMMd_DEFINED   1
 
#define XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_MEMd_DEFINED   1
 
#define XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_XMMd_DEFINED   1
 
#define XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132SD_XMMdq_XMMq_MEMq_DEFINED   1
 
#define XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq_DEFINED   1
 
#define XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd_DEFINED   1
 
#define XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd_DEFINED   1
 
#define XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213SD_XMMdq_XMMq_MEMq_DEFINED   1
 
#define XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq_DEFINED   1
 
#define XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd_DEFINED   1
 
#define XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd_DEFINED   1
 
#define XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231SD_XMMdq_XMMq_MEMq_DEFINED   1
 
#define XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq_DEFINED   1
 
#define XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd_DEFINED   1
 
#define XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd_DEFINED   1
 
#define XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFNMADDSD_XMMdq_XMMq_MEMq_XMMq_DEFINED   1
 
#define XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_MEMq_DEFINED   1
 
#define XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_XMMq_DEFINED   1
 
#define XED_IFORM_VFNMADDSS_XMMdq_XMMd_MEMd_XMMd_DEFINED   1
 
#define XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_MEMd_DEFINED   1
 
#define XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd_DEFINED   1
 
#define XED_IFORM_VFNMSUB132BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_MEMq_DEFINED   1
 
#define XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq_DEFINED   1
 
#define XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd_DEFINED   1
 
#define XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd_DEFINED   1
 
#define XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_MEMq_DEFINED   1
 
#define XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq_DEFINED   1
 
#define XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd_DEFINED   1
 
#define XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd_DEFINED   1
 
#define XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_MEMq_DEFINED   1
 
#define XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq_DEFINED   1
 
#define XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd_DEFINED   1
 
#define XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd_DEFINED   1
 
#define XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq_DEFINED   1
 
#define XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq_DEFINED   1
 
#define XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq_DEFINED   1
 
#define XED_IFORM_VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd_DEFINED   1
 
#define XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd_DEFINED   1
 
#define XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd_DEFINED   1
 
#define XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_XMMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_YMMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_ZMMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VFRCZPD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFRCZPD_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFRCZPD_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFRCZPD_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFRCZPS_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VFRCZPS_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VFRCZPS_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VFRCZPS_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VFRCZSD_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_VFRCZSD_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_VFRCZSS_XMMdq_MEMd_DEFINED   1
 
#define XED_IFORM_VFRCZSS_XMMdq_XMMd_DEFINED   1
 
#define XED_IFORM_VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128_DEFINED   1
 
#define XED_IFORM_VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256_DEFINED   1
 
#define XED_IFORM_VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128_DEFINED   1
 
#define XED_IFORM_VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256_DEFINED   1
 
#define XED_IFORM_VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED   1
 
#define XED_IFORM_VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED   1
 
#define XED_IFORM_VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED   1
 
#define XED_IFORM_VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED   1
 
#define XED_IFORM_VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED   1
 
#define XED_IFORM_VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED   1
 
#define XED_IFORM_VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED   1
 
#define XED_IFORM_VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED   1
 
#define XED_IFORM_VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128_DEFINED   1
 
#define XED_IFORM_VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256_DEFINED   1
 
#define XED_IFORM_VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128_DEFINED   1
 
#define XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256_DEFINED   1
 
#define XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VGETEXPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8_DEFINED   1
 
#define XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8_DEFINED   1
 
#define XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8_DEFINED   1
 
#define XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8_DEFINED   1
 
#define XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8_DEFINED   1
 
#define XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8_DEFINED   1
 
#define XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8_DEFINED   1
 
#define XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8_DEFINED   1
 
#define XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_MEMu8_DEFINED   1
 
#define XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_XMMu8_DEFINED   1
 
#define XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_MEMu8_DEFINED   1
 
#define XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_YMMu8_DEFINED   1
 
#define XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VHADDPD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VHADDPD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VHADDPD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VHADDPD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VHADDPS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VHADDPS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VHADDPS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VHADDPS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VHSUBPD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VHSUBPD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VHSUBPD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VHSUBPD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VHSUBPS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VHSUBPS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VHSUBPS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VHSUBPS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VINSERTPS_XMMdq_XMMdq_MEMd_IMMb_DEFINED   1
 
#define XED_IFORM_VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VLDDQU_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VLDDQU_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VLDMXCSR_MEMd_DEFINED   1
 
#define XED_IFORM_VMASKMOVDQU_XMMxub_XMMxub_DEFINED   1
 
#define XED_IFORM_VMASKMOVPD_MEMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VMASKMOVPD_MEMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VMASKMOVPD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VMASKMOVPD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VMASKMOVPS_MEMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VMAXBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXPS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VMAXPS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXSD_XMMdq_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_VMAXSD_XMMdq_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd_DEFINED   1
 
#define XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd_DEFINED   1
 
#define XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMCALL_DEFINED   1
 
#define XED_IFORM_VMCLEAR_MEMq_DEFINED   1
 
#define XED_IFORM_VMFUNC_DEFINED   1
 
#define XED_IFORM_VMINBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMINBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMINBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMINBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMINBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMINBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMINPS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VMINPS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMINSD_XMMdq_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_VMINSD_XMMdq_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd_DEFINED   1
 
#define XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd_DEFINED   1
 
#define XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMLAUNCH_DEFINED   1
 
#define XED_IFORM_VMLOAD_ArAX_DEFINED   1
 
#define XED_IFORM_VMMCALL_DEFINED   1
 
#define XED_IFORM_VMOVAPD_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVAPD_MEMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VMOVAPD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VMOVAPD_XMMdq_XMMdq_28_DEFINED   1
 
#define XED_IFORM_VMOVAPD_XMMdq_XMMdq_29_DEFINED   1
 
#define XED_IFORM_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVAPD_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VMOVAPD_YMMqq_YMMqq_28_DEFINED   1
 
#define XED_IFORM_VMOVAPD_YMMqq_YMMqq_29_DEFINED   1
 
#define XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVAPS_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVAPS_MEMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VMOVAPS_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VMOVAPS_XMMdq_XMMdq_28_DEFINED   1
 
#define XED_IFORM_VMOVAPS_XMMdq_XMMdq_29_DEFINED   1
 
#define XED_IFORM_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVAPS_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VMOVAPS_YMMqq_YMMqq_28_DEFINED   1
 
#define XED_IFORM_VMOVAPS_YMMqq_YMMqq_29_DEFINED   1
 
#define XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVD_GPR32d_XMMd_DEFINED   1
 
#define XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVD_MEMd_XMMd_DEFINED   1
 
#define XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512_MOVZXC_DEFINED   1
 
#define XED_IFORM_VMOVD_XMMdq_GPR32d_DEFINED   1
 
#define XED_IFORM_VMOVD_XMMdq_MEMd_DEFINED   1
 
#define XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512_MOVZXC_DEFINED   1
 
#define XED_IFORM_VMOVD_XMMu32_XMMu32_AVX512_MOVZXC_DEFINED   1
 
#define XED_IFORM_VMOVDDUP_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_VMOVDDUP_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDDUP_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VMOVDDUP_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQA_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VMOVDQA_MEMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VMOVDQA_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VMOVDQA_XMMdq_XMMdq_6F_DEFINED   1
 
#define XED_IFORM_VMOVDQA_XMMdq_XMMdq_7F_DEFINED   1
 
#define XED_IFORM_VMOVDQA_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VMOVDQA_YMMqq_YMMqq_6F_DEFINED   1
 
#define XED_IFORM_VMOVDQA_YMMqq_YMMqq_7F_DEFINED   1
 
#define XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVDQU_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VMOVDQU_MEMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VMOVDQU_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VMOVDQU_XMMdq_XMMdq_6F_DEFINED   1
 
#define XED_IFORM_VMOVDQU_XMMdq_XMMdq_7F_DEFINED   1
 
#define XED_IFORM_VMOVDQU_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VMOVDQU_YMMqq_YMMqq_6F_DEFINED   1
 
#define XED_IFORM_VMOVDQU_YMMqq_YMMqq_7F_DEFINED   1
 
#define XED_IFORM_VMOVHLPS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVHPD_MEMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVHPD_MEMq_XMMdq_DEFINED   1
 
#define XED_IFORM_VMOVHPD_XMMdq_XMMq_MEMq_DEFINED   1
 
#define XED_IFORM_VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVHPS_MEMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVHPS_MEMq_XMMdq_DEFINED   1
 
#define XED_IFORM_VMOVHPS_XMMdq_XMMq_MEMq_DEFINED   1
 
#define XED_IFORM_VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVLHPS_XMMdq_XMMq_XMMq_DEFINED   1
 
#define XED_IFORM_VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVLPD_MEMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVLPD_MEMq_XMMq_DEFINED   1
 
#define XED_IFORM_VMOVLPD_XMMdq_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVLPS_MEMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVLPS_MEMq_XMMq_DEFINED   1
 
#define XED_IFORM_VMOVLPS_XMMdq_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVMSKPD_GPR32d_XMMdq_DEFINED   1
 
#define XED_IFORM_VMOVMSKPD_GPR32d_YMMqq_DEFINED   1
 
#define XED_IFORM_VMOVMSKPS_GPR32d_XMMdq_DEFINED   1
 
#define XED_IFORM_VMOVMSKPS_GPR32d_YMMqq_DEFINED   1
 
#define XED_IFORM_VMOVNTDQ_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VMOVNTDQ_MEMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VMOVNTDQ_MEMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVNTDQ_MEMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVNTDQ_MEMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVNTDQA_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VMOVNTDQA_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVNTDQA_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VMOVNTDQA_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVNTDQA_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVNTPD_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VMOVNTPD_MEMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVNTPD_MEMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVNTPD_MEMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVNTPD_MEMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VMOVNTPS_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VMOVNTPS_MEMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVNTPS_MEMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVNTPS_MEMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVNTPS_MEMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VMOVQ_GPR64q_XMMq_DEFINED   1
 
#define XED_IFORM_VMOVQ_GPR64u64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVQ_MEMq_XMMq_7E_DEFINED   1
 
#define XED_IFORM_VMOVQ_MEMq_XMMq_D6_DEFINED   1
 
#define XED_IFORM_VMOVQ_MEMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVQ_XMMdq_GPR64q_DEFINED   1
 
#define XED_IFORM_VMOVQ_XMMdq_MEMq_6E_DEFINED   1
 
#define XED_IFORM_VMOVQ_XMMdq_MEMq_7E_DEFINED   1
 
#define XED_IFORM_VMOVQ_XMMdq_XMMq_7E_DEFINED   1
 
#define XED_IFORM_VMOVQ_XMMdq_XMMq_D6_DEFINED   1
 
#define XED_IFORM_VMOVQ_XMMu64_GPR64u64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVRSB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVRSB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVRSB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVRSD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVRSD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVRSD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVRSQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVRSQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVRSQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVRSW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVRSW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVRSW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVSD_MEMq_XMMq_DEFINED   1
 
#define XED_IFORM_VMOVSD_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_10_DEFINED   1
 
#define XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_11_DEFINED   1
 
#define XED_IFORM_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVSHDUP_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VMOVSHDUP_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVSHDUP_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VMOVSHDUP_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVSLDUP_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VMOVSLDUP_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVSLDUP_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VMOVSLDUP_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVSS_MEMd_XMMd_DEFINED   1
 
#define XED_IFORM_VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVSS_XMMdq_MEMd_DEFINED   1
 
#define XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_10_DEFINED   1
 
#define XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_11_DEFINED   1
 
#define XED_IFORM_VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVUPD_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVUPD_MEMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VMOVUPD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VMOVUPD_XMMdq_XMMdq_10_DEFINED   1
 
#define XED_IFORM_VMOVUPD_XMMdq_XMMdq_11_DEFINED   1
 
#define XED_IFORM_VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVUPD_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VMOVUPD_YMMqq_YMMqq_10_DEFINED   1
 
#define XED_IFORM_VMOVUPD_YMMqq_YMMqq_11_DEFINED   1
 
#define XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVUPS_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVUPS_MEMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VMOVUPS_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VMOVUPS_XMMdq_XMMdq_10_DEFINED   1
 
#define XED_IFORM_VMOVUPS_XMMdq_XMMdq_11_DEFINED   1
 
#define XED_IFORM_VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVUPS_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VMOVUPS_YMMqq_YMMqq_10_DEFINED   1
 
#define XED_IFORM_VMOVUPS_YMMqq_YMMqq_11_DEFINED   1
 
#define XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVW_GPR32f16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVW_MEMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVW_MEMu16_XMMu16_AVX512_MOVZXC_DEFINED   1
 
#define XED_IFORM_VMOVW_XMMf16_GPR32f16_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVW_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMOVW_XMMu16_MEMu16_AVX512_MOVZXC_DEFINED   1
 
#define XED_IFORM_VMOVW_XMMu16_XMMu16_AVX512_MOVZXC_DEFINED   1
 
#define XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VMPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VMPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VMPTRLD_MEMq_DEFINED   1
 
#define XED_IFORM_VMPTRST_MEMq_DEFINED   1
 
#define XED_IFORM_VMREAD_GPR32_GPR32_DEFINED   1
 
#define XED_IFORM_VMREAD_GPR64_GPR64_DEFINED   1
 
#define XED_IFORM_VMREAD_MEMd_GPR32_DEFINED   1
 
#define XED_IFORM_VMREAD_MEMq_GPR64_DEFINED   1
 
#define XED_IFORM_VMRESUME_DEFINED   1
 
#define XED_IFORM_VMRUN_ArAX_DEFINED   1
 
#define XED_IFORM_VMSAVE_DEFINED   1
 
#define XED_IFORM_VMULBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMULBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMULBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMULBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMULBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMULBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMULPS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VMULPS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMULSD_XMMdq_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_VMULSD_XMMdq_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd_DEFINED   1
 
#define XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd_DEFINED   1
 
#define XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VMWRITE_GPR32_GPR32_DEFINED   1
 
#define XED_IFORM_VMWRITE_GPR32_MEMd_DEFINED   1
 
#define XED_IFORM_VMWRITE_GPR64_GPR64_DEFINED   1
 
#define XED_IFORM_VMWRITE_GPR64_MEMq_DEFINED   1
 
#define XED_IFORM_VMXOFF_DEFINED   1
 
#define XED_IFORM_VMXON_MEMq_DEFINED   1
 
#define XED_IFORM_VORPD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VORPD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VORPD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VORPD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VORPS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VORPS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VORPS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VORPS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPABSB_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPABSB_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPABSB_XMMi8_MASKmskw_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPABSB_YMMi8_MASKmskw_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPABSB_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPABSB_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPABSD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPABSD_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPABSD_XMMi32_MASKmskw_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPABSD_XMMi32_MASKmskw_XMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPABSD_YMMi32_MASKmskw_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPABSD_YMMi32_MASKmskw_YMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPABSD_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPABSD_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPABSW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPABSW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPABSW_XMMi16_MASKmskw_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPABSW_XMMi16_MASKmskw_XMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPABSW_YMMi16_MASKmskw_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPABSW_YMMi16_MASKmskw_YMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPABSW_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPABSW_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPACKSSDW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPACKSSDW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPACKSSDW_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPACKSSDW_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPACKSSWB_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPACKSSWB_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPACKSSWB_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPACKSSWB_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPACKUSDW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPACKUSDW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPACKUSDW_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPACKUSDW_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPACKUSWB_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPACKUSWB_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPACKUSWB_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPACKUSWB_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDB_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPADDB_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDB_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPADDB_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPADDD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPADDD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDQ_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPADDQ_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDQ_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPADDQ_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDSB_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPADDSB_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDSB_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPADDSB_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDSW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPADDSW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDSW_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPADDSW_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDUSB_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPADDUSB_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDUSB_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPADDUSB_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDUSW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPADDUSW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDUSW_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPADDUSW_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPADDW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDW_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPADDW_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPAND_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPAND_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPAND_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPAND_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPANDN_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPANDN_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPANDN_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPANDN_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPAVGB_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPAVGB_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPAVGB_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPAVGB_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPAVGW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPAVGW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPAVGW_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPAVGW_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPBROADCASTB_XMMdq_MEMb_DEFINED   1
 
#define XED_IFORM_VPBROADCASTB_XMMdq_XMMb_DEFINED   1
 
#define XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTB_YMMqq_MEMb_DEFINED   1
 
#define XED_IFORM_VPBROADCASTB_YMMqq_XMMb_DEFINED   1
 
#define XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTD_XMMdq_MEMd_DEFINED   1
 
#define XED_IFORM_VPBROADCASTD_XMMdq_XMMd_DEFINED   1
 
#define XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTD_YMMqq_MEMd_DEFINED   1
 
#define XED_IFORM_VPBROADCASTD_YMMqq_XMMd_DEFINED   1
 
#define XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD_DEFINED   1
 
#define XED_IFORM_VPBROADCASTMW2D_XMMu32_MASKu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTMW2D_YMMu32_MASKu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD_DEFINED   1
 
#define XED_IFORM_VPBROADCASTQ_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_VPBROADCASTQ_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTQ_YMMqq_MEMq_DEFINED   1
 
#define XED_IFORM_VPBROADCASTQ_YMMqq_XMMq_DEFINED   1
 
#define XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTW_XMMdq_MEMw_DEFINED   1
 
#define XED_IFORM_VPBROADCASTW_XMMdq_XMMw_DEFINED   1
 
#define XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTW_YMMqq_MEMw_DEFINED   1
 
#define XED_IFORM_VPBROADCASTW_YMMqq_XMMw_DEFINED   1
 
#define XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_DEFINED   1
 
#define XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_DEFINED   1
 
#define XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPEQB_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPCMPEQB_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPCMPEQB_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPCMPEQB_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPEQD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPCMPEQD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPCMPEQD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPCMPEQD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPEQW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPCMPEQW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPCMPEQW_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPCMPEQW_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPCMPESTRI64_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCMPESTRI64_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCMPESTRM64_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCMPESTRM64_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPGTB_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPCMPGTB_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPCMPGTB_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPCMPGTB_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPGTD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPCMPGTD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPCMPGTD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPCMPGTD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPGTW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPCMPGTW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPCMPGTW_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPCMPGTW_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPCMPISTRI64_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCMPISTRI64_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCMPISTRM_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCMPISTRM_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCOMB_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCOMB_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCOMD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCOMD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCOMW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCOMW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD_DEFINED   1
 
#define XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD_DEFINED   1
 
#define XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD_DEFINED   1
 
#define XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD_DEFINED   1
 
#define XED_IFORM_VPDPBSSD_XMMi32_MASKmskw_XMM4i8_MEM4i8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBSSD_XMMi32_MASKmskw_XMM4i8_XMM4i8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBSSD_XMMi32_XMM4i8_MEM4i8_DEFINED   1
 
#define XED_IFORM_VPDPBSSD_XMMi32_XMM4i8_XMM4i8_DEFINED   1
 
#define XED_IFORM_VPDPBSSD_YMMi32_MASKmskw_YMM4i8_MEM4i8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBSSD_YMMi32_MASKmskw_YMM4i8_YMM4i8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBSSD_YMMi32_YMM4i8_MEM4i8_DEFINED   1
 
#define XED_IFORM_VPDPBSSD_YMMi32_YMM4i8_YMM4i8_DEFINED   1
 
#define XED_IFORM_VPDPBSSD_ZMMi32_MASKmskw_ZMM4i8_MEM4i8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBSSD_ZMMi32_MASKmskw_ZMM4i8_ZMM4i8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBSSDS_XMMi32_MASKmskw_XMM4i8_MEM4i8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBSSDS_XMMi32_MASKmskw_XMM4i8_XMM4i8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBSSDS_XMMi32_XMM4i8_MEM4i8_DEFINED   1
 
#define XED_IFORM_VPDPBSSDS_XMMi32_XMM4i8_XMM4i8_DEFINED   1
 
#define XED_IFORM_VPDPBSSDS_YMMi32_MASKmskw_YMM4i8_MEM4i8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBSSDS_YMMi32_MASKmskw_YMM4i8_YMM4i8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBSSDS_YMMi32_YMM4i8_MEM4i8_DEFINED   1
 
#define XED_IFORM_VPDPBSSDS_YMMi32_YMM4i8_YMM4i8_DEFINED   1
 
#define XED_IFORM_VPDPBSSDS_ZMMi32_MASKmskw_ZMM4i8_MEM4i8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBSSDS_ZMMi32_MASKmskw_ZMM4i8_ZMM4i8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBSUD_XMMi32_MASKmskw_XMM4i8_MEM4u8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBSUD_XMMi32_MASKmskw_XMM4i8_XMM4u8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBSUD_XMMi32_XMM4i8_MEM4u8_DEFINED   1
 
#define XED_IFORM_VPDPBSUD_XMMi32_XMM4i8_XMM4u8_DEFINED   1
 
#define XED_IFORM_VPDPBSUD_YMMi32_MASKmskw_YMM4i8_MEM4u8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBSUD_YMMi32_MASKmskw_YMM4i8_YMM4u8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBSUD_YMMi32_YMM4i8_MEM4u8_DEFINED   1
 
#define XED_IFORM_VPDPBSUD_YMMi32_YMM4i8_YMM4u8_DEFINED   1
 
#define XED_IFORM_VPDPBSUD_ZMMi32_MASKmskw_ZMM4i8_MEM4u8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBSUD_ZMMi32_MASKmskw_ZMM4i8_ZMM4u8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBSUDS_XMMi32_MASKmskw_XMM4i8_MEM4u8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBSUDS_XMMi32_MASKmskw_XMM4i8_XMM4u8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBSUDS_XMMi32_XMM4i8_MEM4u8_DEFINED   1
 
#define XED_IFORM_VPDPBSUDS_XMMi32_XMM4i8_XMM4u8_DEFINED   1
 
#define XED_IFORM_VPDPBSUDS_YMMi32_MASKmskw_YMM4i8_MEM4u8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBSUDS_YMMi32_MASKmskw_YMM4i8_YMM4u8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBSUDS_YMMi32_YMM4i8_MEM4u8_DEFINED   1
 
#define XED_IFORM_VPDPBSUDS_YMMi32_YMM4i8_YMM4u8_DEFINED   1
 
#define XED_IFORM_VPDPBSUDS_ZMMi32_MASKmskw_ZMM4i8_MEM4u8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBSUDS_ZMMi32_MASKmskw_ZMM4i8_ZMM4u8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBUSD_XMMi32_XMMu32_MEMu32_DEFINED   1
 
#define XED_IFORM_VPDPBUSD_XMMi32_XMMu32_XMMu32_DEFINED   1
 
#define XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBUSD_YMMi32_YMMu32_MEMu32_DEFINED   1
 
#define XED_IFORM_VPDPBUSD_YMMi32_YMMu32_YMMu32_DEFINED   1
 
#define XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_MEMu32_DEFINED   1
 
#define XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_XMMu32_DEFINED   1
 
#define XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_MEMu32_DEFINED   1
 
#define XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_YMMu32_DEFINED   1
 
#define XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBUUD_XMMu32_MASKmskw_XMM4u8_MEM4u8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBUUD_XMMu32_MASKmskw_XMM4u8_XMM4u8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBUUD_XMMu32_XMM4u8_MEM4u8_DEFINED   1
 
#define XED_IFORM_VPDPBUUD_XMMu32_XMM4u8_XMM4u8_DEFINED   1
 
#define XED_IFORM_VPDPBUUD_YMMu32_MASKmskw_YMM4u8_MEM4u8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBUUD_YMMu32_MASKmskw_YMM4u8_YMM4u8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBUUD_YMMu32_YMM4u8_MEM4u8_DEFINED   1
 
#define XED_IFORM_VPDPBUUD_YMMu32_YMM4u8_YMM4u8_DEFINED   1
 
#define XED_IFORM_VPDPBUUD_ZMMu32_MASKmskw_ZMM4u8_MEM4u8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBUUD_ZMMu32_MASKmskw_ZMM4u8_ZMM4u8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBUUDS_XMMu32_MASKmskw_XMM4u8_MEM4u8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBUUDS_XMMu32_MASKmskw_XMM4u8_XMM4u8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBUUDS_XMMu32_XMM4u8_MEM4u8_DEFINED   1
 
#define XED_IFORM_VPDPBUUDS_XMMu32_XMM4u8_XMM4u8_DEFINED   1
 
#define XED_IFORM_VPDPBUUDS_YMMu32_MASKmskw_YMM4u8_MEM4u8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBUUDS_YMMu32_MASKmskw_YMM4u8_YMM4u8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBUUDS_YMMu32_YMM4u8_MEM4u8_DEFINED   1
 
#define XED_IFORM_VPDPBUUDS_YMMu32_YMM4u8_YMM4u8_DEFINED   1
 
#define XED_IFORM_VPDPBUUDS_ZMMu32_MASKmskw_ZMM4u8_MEM4u8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPBUUDS_ZMMu32_MASKmskw_ZMM4u8_ZMM4u8_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWSSD_XMMi32_XMMu32_MEMu32_DEFINED   1
 
#define XED_IFORM_VPDPWSSD_XMMi32_XMMu32_XMMu32_DEFINED   1
 
#define XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWSSD_YMMi32_YMMu32_MEMu32_DEFINED   1
 
#define XED_IFORM_VPDPWSSD_YMMi32_YMMu32_YMMu32_DEFINED   1
 
#define XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_MEMu32_DEFINED   1
 
#define XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_XMMu32_DEFINED   1
 
#define XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_MEMu32_DEFINED   1
 
#define XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_YMMu32_DEFINED   1
 
#define XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWSUD_XMMi32_MASKmskw_XMM2i16_MEM2u16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWSUD_XMMi32_MASKmskw_XMM2i16_XMM2u16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWSUD_XMMi32_XMM2i16_MEM2u16_DEFINED   1
 
#define XED_IFORM_VPDPWSUD_XMMi32_XMM2i16_XMM2u16_DEFINED   1
 
#define XED_IFORM_VPDPWSUD_YMMi32_MASKmskw_YMM2i16_MEM2u16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWSUD_YMMi32_MASKmskw_YMM2i16_YMM2u16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWSUD_YMMi32_YMM2i16_MEM2u16_DEFINED   1
 
#define XED_IFORM_VPDPWSUD_YMMi32_YMM2i16_YMM2u16_DEFINED   1
 
#define XED_IFORM_VPDPWSUD_ZMMi32_MASKmskw_ZMM2i16_MEM2u16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWSUD_ZMMi32_MASKmskw_ZMM2i16_ZMM2u16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWSUDS_XMMi32_MASKmskw_XMM2i16_MEM2u16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWSUDS_XMMi32_MASKmskw_XMM2i16_XMM2u16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWSUDS_XMMi32_XMM2i16_MEM2u16_DEFINED   1
 
#define XED_IFORM_VPDPWSUDS_XMMi32_XMM2i16_XMM2u16_DEFINED   1
 
#define XED_IFORM_VPDPWSUDS_YMMi32_MASKmskw_YMM2i16_MEM2u16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWSUDS_YMMi32_MASKmskw_YMM2i16_YMM2u16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWSUDS_YMMi32_YMM2i16_MEM2u16_DEFINED   1
 
#define XED_IFORM_VPDPWSUDS_YMMi32_YMM2i16_YMM2u16_DEFINED   1
 
#define XED_IFORM_VPDPWSUDS_ZMMi32_MASKmskw_ZMM2i16_MEM2u16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWSUDS_ZMMi32_MASKmskw_ZMM2i16_ZMM2u16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWUSD_XMMi32_MASKmskw_XMM2u16_MEM2i16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWUSD_XMMi32_MASKmskw_XMM2u16_XMM2i16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWUSD_XMMi32_XMM2u16_MEM2i16_DEFINED   1
 
#define XED_IFORM_VPDPWUSD_XMMi32_XMM2u16_XMM2i16_DEFINED   1
 
#define XED_IFORM_VPDPWUSD_YMMi32_MASKmskw_YMM2u16_MEM2i16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWUSD_YMMi32_MASKmskw_YMM2u16_YMM2i16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWUSD_YMMi32_YMM2u16_MEM2i16_DEFINED   1
 
#define XED_IFORM_VPDPWUSD_YMMi32_YMM2u16_YMM2i16_DEFINED   1
 
#define XED_IFORM_VPDPWUSD_ZMMi32_MASKmskw_ZMM2u16_MEM2i16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWUSD_ZMMi32_MASKmskw_ZMM2u16_ZMM2i16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWUSDS_XMMi32_MASKmskw_XMM2u16_MEM2i16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWUSDS_XMMi32_MASKmskw_XMM2u16_XMM2i16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWUSDS_XMMi32_XMM2u16_MEM2i16_DEFINED   1
 
#define XED_IFORM_VPDPWUSDS_XMMi32_XMM2u16_XMM2i16_DEFINED   1
 
#define XED_IFORM_VPDPWUSDS_YMMi32_MASKmskw_YMM2u16_MEM2i16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWUSDS_YMMi32_MASKmskw_YMM2u16_YMM2i16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWUSDS_YMMi32_YMM2u16_MEM2i16_DEFINED   1
 
#define XED_IFORM_VPDPWUSDS_YMMi32_YMM2u16_YMM2i16_DEFINED   1
 
#define XED_IFORM_VPDPWUSDS_ZMMi32_MASKmskw_ZMM2u16_MEM2i16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWUSDS_ZMMi32_MASKmskw_ZMM2u16_ZMM2i16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWUUD_XMMu32_MASKmskw_XMM2u16_MEM2u16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWUUD_XMMu32_MASKmskw_XMM2u16_XMM2u16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWUUD_XMMu32_XMM2u16_MEM2u16_DEFINED   1
 
#define XED_IFORM_VPDPWUUD_XMMu32_XMM2u16_XMM2u16_DEFINED   1
 
#define XED_IFORM_VPDPWUUD_YMMu32_MASKmskw_YMM2u16_MEM2u16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWUUD_YMMu32_MASKmskw_YMM2u16_YMM2u16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWUUD_YMMu32_YMM2u16_MEM2u16_DEFINED   1
 
#define XED_IFORM_VPDPWUUD_YMMu32_YMM2u16_YMM2u16_DEFINED   1
 
#define XED_IFORM_VPDPWUUD_ZMMu32_MASKmskw_ZMM2u16_MEM2u16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWUUD_ZMMu32_MASKmskw_ZMM2u16_ZMM2u16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWUUDS_XMMu32_MASKmskw_XMM2u16_MEM2u16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWUUDS_XMMu32_MASKmskw_XMM2u16_XMM2u16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWUUDS_XMMu32_XMM2u16_MEM2u16_DEFINED   1
 
#define XED_IFORM_VPDPWUUDS_XMMu32_XMM2u16_XMM2u16_DEFINED   1
 
#define XED_IFORM_VPDPWUUDS_YMMu32_MASKmskw_YMM2u16_MEM2u16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWUUDS_YMMu32_MASKmskw_YMM2u16_YMM2u16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWUUDS_YMMu32_YMM2u16_MEM2u16_DEFINED   1
 
#define XED_IFORM_VPDPWUUDS_YMMu32_YMM2u16_YMM2u16_DEFINED   1
 
#define XED_IFORM_VPDPWUUDS_ZMMu32_MASKmskw_ZMM2u16_MEM2u16_AVX512_DEFINED   1
 
#define XED_IFORM_VPDPWUUDS_ZMMu32_MASKmskw_ZMM2u16_ZMM2u16_AVX512_DEFINED   1
 
#define XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPERMD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPERMILPD_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPERMILPD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPERMILPD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMILPD_YMMqq_MEMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPERMILPD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPERMILPD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMILPS_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPERMILPS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPERMILPS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMILPS_YMMqq_MEMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPERMILPS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPERMILPS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMPD_YMMqq_MEMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMPS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPERMPS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMQ_YMMqq_MEMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXTRB_GPR32d_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXTRB_MEMb_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPEXTRB_MEMu8_XMMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXTRQ_GPR64q_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXTRQ_MEMq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_15_DEFINED   1
 
#define XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_C5_DEFINED   1
 
#define XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5_DEFINED   1
 
#define XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXTRW_MEMu16_XMMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPEXTRW_MEMw_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VPGATHERDD_XMMu32_MEMd_XMMi32_VL128_DEFINED   1
 
#define XED_IFORM_VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VPGATHERDD_YMMu32_MEMd_YMMi32_VL256_DEFINED   1
 
#define XED_IFORM_VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128_DEFINED   1
 
#define XED_IFORM_VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256_DEFINED   1
 
#define XED_IFORM_VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL128_DEFINED   1
 
#define XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL256_DEFINED   1
 
#define XED_IFORM_VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128_DEFINED   1
 
#define XED_IFORM_VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256_DEFINED   1
 
#define XED_IFORM_VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VPHADDBD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPHADDBD_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPHADDBQ_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPHADDBQ_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPHADDBW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPHADDBW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPHADDD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPHADDD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPHADDD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPHADDD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPHADDDQ_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPHADDDQ_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPHADDSW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPHADDSW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPHADDSW_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPHADDSW_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPHADDUBD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPHADDUBD_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPHADDUBQ_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPHADDUBQ_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPHADDUBW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPHADDUBW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPHADDUDQ_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPHADDUDQ_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPHADDUWD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPHADDUWD_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPHADDUWQ_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPHADDUWQ_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPHADDW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPHADDW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPHADDW_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPHADDW_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPHADDWD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPHADDWD_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPHADDWQ_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPHADDWQ_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPHMINPOSUW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPHMINPOSUW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPHSUBBW_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPHSUBBW_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPHSUBD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPHSUBD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPHSUBD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPHSUBD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPHSUBDQ_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPHSUBDQ_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPHSUBSW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPHSUBSW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPHSUBSW_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPHSUBSW_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPHSUBW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPHSUBW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPHSUBW_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPHSUBW_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPHSUBWD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPHSUBWD_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPINSRB_XMMdq_XMMdq_GPR32d_IMMb_DEFINED   1
 
#define XED_IFORM_VPINSRB_XMMdq_XMMdq_MEMb_IMMb_DEFINED   1
 
#define XED_IFORM_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb_DEFINED   1
 
#define XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb_DEFINED   1
 
#define XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb_DEFINED   1
 
#define XED_IFORM_VPINSRQ_XMMdq_XMMdq_MEMq_IMMb_DEFINED   1
 
#define XED_IFORM_VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPINSRW_XMMdq_XMMdq_GPR32d_IMMb_DEFINED   1
 
#define XED_IFORM_VPINSRW_XMMdq_XMMdq_MEMw_IMMb_DEFINED   1
 
#define XED_IFORM_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD_DEFINED   1
 
#define XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD_DEFINED   1
 
#define XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD_DEFINED   1
 
#define XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD_DEFINED   1
 
#define XED_IFORM_VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMADD52HUQ_XMMu64_XMMu64_MEMu64_DEFINED   1
 
#define XED_IFORM_VPMADD52HUQ_XMMu64_XMMu64_XMMu64_DEFINED   1
 
#define XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMADD52HUQ_YMMu64_YMMu64_MEMu64_DEFINED   1
 
#define XED_IFORM_VPMADD52HUQ_YMMu64_YMMu64_YMMu64_DEFINED   1
 
#define XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMADD52LUQ_XMMu64_XMMu64_MEMu64_DEFINED   1
 
#define XED_IFORM_VPMADD52LUQ_XMMu64_XMMu64_XMMu64_DEFINED   1
 
#define XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMADD52LUQ_YMMu64_YMMu64_MEMu64_DEFINED   1
 
#define XED_IFORM_VPMADD52LUQ_YMMu64_YMMu64_YMMu64_DEFINED   1
 
#define XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMADDWD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMADDWD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMADDWD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPMADDWD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMASKMOVD_MEMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMASKMOVD_MEMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMASKMOVD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPMASKMOVQ_MEMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMASKMOVQ_MEMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPMASKMOVQ_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMASKMOVQ_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPMAXSB_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMAXSB_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXSB_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPMAXSB_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXSD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMAXSD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXSD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPMAXSD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXSW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMAXSW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXSW_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPMAXSW_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXUB_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMAXUB_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXUB_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPMAXUB_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXUD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMAXUD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXUD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPMAXUD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXUW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMAXUW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXUW_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPMAXUW_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINSB_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMINSB_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINSB_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPMINSB_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINSD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMINSD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINSD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPMINSD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINSW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMINSW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINSW_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPMINSW_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINUB_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMINUB_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINUB_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPMINUB_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINUD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMINUD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINUD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPMINUD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINUW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMINUW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINUW_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPMINUW_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVB2M_MASKmskw_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVB2M_MASKmskw_YMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVB2M_MASKmskw_ZMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVD2M_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVD2M_MASKmskw_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVD2M_MASKmskw_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVM2B_XMMu8_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVM2B_YMMu8_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVM2B_ZMMu8_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVM2D_XMMu32_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVM2D_YMMu32_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVM2D_ZMMu32_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVM2Q_XMMu64_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVM2Q_YMMu64_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVM2Q_ZMMu64_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVM2W_XMMu16_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVM2W_YMMu16_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVM2W_ZMMu16_MASKmskw_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVMSKB_GPR32d_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMOVMSKB_GPR32d_YMMqq_DEFINED   1
 
#define XED_IFORM_VPMOVQ2M_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVQ2M_MASKmskw_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVQ2M_MASKmskw_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXBD_XMMdq_MEMd_DEFINED   1
 
#define XED_IFORM_VPMOVSXBD_XMMdq_XMMd_DEFINED   1
 
#define XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXBD_YMMqq_MEMq_DEFINED   1
 
#define XED_IFORM_VPMOVSXBD_YMMqq_XMMq_DEFINED   1
 
#define XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXBQ_XMMdq_MEMw_DEFINED   1
 
#define XED_IFORM_VPMOVSXBQ_XMMdq_XMMw_DEFINED   1
 
#define XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXBQ_YMMqq_MEMd_DEFINED   1
 
#define XED_IFORM_VPMOVSXBQ_YMMqq_XMMd_DEFINED   1
 
#define XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXBW_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_VPMOVSXBW_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXBW_YMMqq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMOVSXBW_YMMqq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXDQ_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_VPMOVSXDQ_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXDQ_YMMqq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMOVSXDQ_YMMqq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXWD_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_VPMOVSXWD_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXWD_YMMqq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMOVSXWD_YMMqq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXWQ_XMMdq_MEMd_DEFINED   1
 
#define XED_IFORM_VPMOVSXWQ_XMMdq_XMMd_DEFINED   1
 
#define XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXWQ_YMMqq_MEMq_DEFINED   1
 
#define XED_IFORM_VPMOVSXWQ_YMMqq_XMMq_DEFINED   1
 
#define XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVW2M_MASKmskw_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVW2M_MASKmskw_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVW2M_MASKmskw_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXBD_XMMdq_MEMd_DEFINED   1
 
#define XED_IFORM_VPMOVZXBD_XMMdq_XMMd_DEFINED   1
 
#define XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXBD_YMMqq_MEMq_DEFINED   1
 
#define XED_IFORM_VPMOVZXBD_YMMqq_XMMq_DEFINED   1
 
#define XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXBQ_XMMdq_MEMw_DEFINED   1
 
#define XED_IFORM_VPMOVZXBQ_XMMdq_XMMw_DEFINED   1
 
#define XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXBQ_YMMqq_MEMd_DEFINED   1
 
#define XED_IFORM_VPMOVZXBQ_YMMqq_XMMd_DEFINED   1
 
#define XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXBW_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_VPMOVZXBW_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXBW_YMMqq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMOVZXBW_YMMqq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXDQ_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_VPMOVZXDQ_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXDQ_YMMqq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMOVZXDQ_YMMqq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXWD_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_VPMOVZXWD_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXWD_YMMqq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMOVZXWD_YMMqq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXWQ_XMMdq_MEMd_DEFINED   1
 
#define XED_IFORM_VPMOVZXWQ_XMMdq_XMMd_DEFINED   1
 
#define XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXWQ_YMMqq_MEMq_DEFINED   1
 
#define XED_IFORM_VPMOVZXWQ_YMMqq_XMMq_DEFINED   1
 
#define XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULDQ_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMULDQ_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULDQ_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPMULDQ_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULHRSW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMULHRSW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULHRSW_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPMULHRSW_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULHUW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMULHUW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULHUW_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPMULHUW_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULHW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMULHW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULHW_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPMULHW_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULLD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMULLD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULLD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPMULLD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULLW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMULLW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULLW_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPMULLW_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULUDQ_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPMULUDQ_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULUDQ_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPMULUDQ_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPOR_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPOR_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPOR_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPOR_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPPERM_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPROTB_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPROTB_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPROTB_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPROTB_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPROTB_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPROTD_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPROTD_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPROTD_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPROTD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPROTD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPROTQ_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPROTQ_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPROTQ_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPROTQ_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPROTQ_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPROTW_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPROTW_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPROTW_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPROTW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPROTW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSADBW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSADBW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSADBW_XMMu16_XMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSADBW_XMMu16_XMMu8_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSADBW_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPSADBW_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPSADBW_YMMu16_YMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSADBW_YMMu16_YMMu8_YMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VPSHAB_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSHAB_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSHAB_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSHAD_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSHAD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSHAD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSHAQ_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSHAQ_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSHAQ_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSHAW_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSHAW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSHAW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSHLB_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSHLB_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSHLB_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSHLD_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSHLD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSHLD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHLQ_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSHLQ_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSHLQ_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSHLW_XMMdq_MEMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSHLW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSHLW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFB_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSHUFB_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFB_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPSHUFB_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFD_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSHUFD_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFD_YMMqq_MEMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFHW_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSHUFHW_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFHW_YMMqq_MEMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFLW_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSHUFLW_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFLW_YMMqq_MEMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSIGNB_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSIGNB_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSIGNB_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPSIGNB_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPSIGND_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSIGND_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSIGND_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPSIGND_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPSIGNW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSIGNW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSIGNW_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPSIGNW_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPSLLD_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSLLD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSLLD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSLLD_YMMqq_YMMqq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSLLD_YMMqq_YMMqq_XMMq_DEFINED   1
 
#define XED_IFORM_VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLDQ_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLQ_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSLLQ_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSLLQ_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSLLQ_YMMqq_YMMqq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSLLQ_YMMqq_YMMqq_XMMq_DEFINED   1
 
#define XED_IFORM_VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLVD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSLLVD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLVD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPSLLVD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLVQ_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSLLVQ_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLVQ_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPSLLVQ_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLW_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSLLW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSLLW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSLLW_YMMqq_YMMqq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSLLW_YMMqq_YMMqq_XMMq_DEFINED   1
 
#define XED_IFORM_VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAD_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSRAD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSRAD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSRAD_YMMqq_YMMqq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSRAD_YMMqq_YMMqq_XMMq_DEFINED   1
 
#define XED_IFORM_VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAVD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSRAVD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAVD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPSRAVD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAW_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSRAW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSRAW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSRAW_YMMqq_YMMqq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSRAW_YMMqq_YMMqq_XMMq_DEFINED   1
 
#define XED_IFORM_VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLD_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSRLD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSRLD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSRLD_YMMqq_YMMqq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSRLD_YMMqq_YMMqq_XMMq_DEFINED   1
 
#define XED_IFORM_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLDQ_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLQ_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSRLQ_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSRLQ_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSRLQ_YMMqq_YMMqq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSRLQ_YMMqq_YMMqq_XMMq_DEFINED   1
 
#define XED_IFORM_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLVD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSRLVD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLVD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPSRLVD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLVQ_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSRLVQ_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLVQ_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPSRLVQ_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLW_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSRLW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSRLW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VPSRLW_YMMqq_YMMqq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSRLW_YMMqq_YMMqq_XMMq_DEFINED   1
 
#define XED_IFORM_VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBB_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSUBB_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBB_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPSUBB_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSUBD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPSUBD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBQ_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSUBQ_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBQ_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPSUBQ_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBSB_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSUBSB_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBSB_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPSUBSB_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBSW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSUBSW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBSW_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPSUBSW_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBUSB_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSUBUSB_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBUSB_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPSUBUSB_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBUSW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSUBUSW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBUSW_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPSUBUSW_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPSUBW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBW_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPSUBW_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VPTEST_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPTEST_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPTEST_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPTEST_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1
 
#define XED_IFORM_VPXOR_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VPXOR_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VPXOR_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VPXOR_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER_DEFINED   1
 
#define XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER_DEFINED   1
 
#define XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER_DEFINED   1
 
#define XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER_DEFINED   1
 
#define XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER_DEFINED   1
 
#define XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER_DEFINED   1
 
#define XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER_DEFINED   1
 
#define XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER_DEFINED   1
 
#define XED_IFORM_VRCPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VRCPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VRCPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VRCPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VRCPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VRCPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VRCPPS_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VRCPPS_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VRCPPS_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VRCPPS_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VRCPSS_XMMdq_XMMdq_MEMd_DEFINED   1
 
#define XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd_DEFINED   1
 
#define XED_IFORM_VREDUCEBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCEBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCEBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCEBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCEBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCEBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALEBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALEBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALEBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALEBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALEBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALEBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VROUNDPS_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VROUNDPS_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VROUNDPS_YMMqq_MEMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VROUNDSD_XMMdq_XMMdq_MEMq_IMMb_DEFINED   1
 
#define XED_IFORM_VROUNDSD_XMMdq_XMMdq_XMMq_IMMb_DEFINED   1
 
#define XED_IFORM_VROUNDSS_XMMdq_XMMdq_MEMd_IMMb_DEFINED   1
 
#define XED_IFORM_VROUNDSS_XMMdq_XMMdq_XMMd_IMMb_DEFINED   1
 
#define XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER_DEFINED   1
 
#define XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER_DEFINED   1
 
#define XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER_DEFINED   1
 
#define XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER_DEFINED   1
 
#define XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER_DEFINED   1
 
#define XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER_DEFINED   1
 
#define XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER_DEFINED   1
 
#define XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER_DEFINED   1
 
#define XED_IFORM_VRSQRTBF16_XMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRTBF16_XMMbf16_MASKmskw_XMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRTBF16_YMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRTBF16_YMMbf16_MASKmskw_YMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRTBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRTBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRTPS_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VRSQRTPS_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VRSQRTPS_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VRSQRTPS_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VRSQRTSS_XMMdq_XMMdq_MEMd_DEFINED   1
 
#define XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd_DEFINED   1
 
#define XED_IFORM_VSCALEFBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED   1
 
#define XED_IFORM_VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED   1
 
#define XED_IFORM_VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED   1
 
#define XED_IFORM_VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED   1
 
#define XED_IFORM_VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED   1
 
#define XED_IFORM_VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED   1
 
#define XED_IFORM_VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED   1
 
#define XED_IFORM_VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED   1
 
#define XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128_DEFINED   1
 
#define XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256_DEFINED   1
 
#define XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512_DEFINED   1
 
#define XED_IFORM_VSHA512MSG1_YMMu64_XMMu64_DEFINED   1
 
#define XED_IFORM_VSHA512MSG2_YMMu64_YMMu64_DEFINED   1
 
#define XED_IFORM_VSHA512RNDS2_YMMu64_YMMu64_XMMu64_DEFINED   1
 
#define XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1
 
#define XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1
 
#define XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED   1
 
#define XED_IFORM_VSM3MSG1_XMMu32_XMMu32_MEMu32_DEFINED   1
 
#define XED_IFORM_VSM3MSG1_XMMu32_XMMu32_XMMu32_DEFINED   1
 
#define XED_IFORM_VSM3MSG2_XMMu32_XMMu32_MEMu32_DEFINED   1
 
#define XED_IFORM_VSM3MSG2_XMMu32_XMMu32_XMMu32_DEFINED   1
 
#define XED_IFORM_VSM3RNDS2_XMMu32_XMMu32_MEMu32_IMM8_DEFINED   1
 
#define XED_IFORM_VSM3RNDS2_XMMu32_XMMu32_XMMu32_IMM8_DEFINED   1
 
#define XED_IFORM_VSM4KEY4_XMMu32_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VSM4KEY4_XMMu32_XMMu32_MEMu32_DEFINED   1
 
#define XED_IFORM_VSM4KEY4_XMMu32_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VSM4KEY4_XMMu32_XMMu32_XMMu32_DEFINED   1
 
#define XED_IFORM_VSM4KEY4_YMMu32_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VSM4KEY4_YMMu32_YMMu32_MEMu32_DEFINED   1
 
#define XED_IFORM_VSM4KEY4_YMMu32_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VSM4KEY4_YMMu32_YMMu32_YMMu32_DEFINED   1
 
#define XED_IFORM_VSM4KEY4_ZMMu32_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VSM4KEY4_ZMMu32_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_MEMu32_DEFINED   1
 
#define XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_XMMu32_DEFINED   1
 
#define XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_MEMu32_DEFINED   1
 
#define XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_YMMu32_DEFINED   1
 
#define XED_IFORM_VSM4RNDS4_ZMMu32_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VSM4RNDS4_ZMMu32_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTBF16_XMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTBF16_XMMbf16_MASKmskw_XMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTBF16_YMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTBF16_YMMbf16_MASKmskw_YMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTPD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VSQRTPD_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTPD_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VSQRTPD_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTPS_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VSQRTPS_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTPS_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VSQRTPS_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTSD_XMMdq_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_VSQRTSD_XMMdq_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd_DEFINED   1
 
#define XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd_DEFINED   1
 
#define XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VSTMXCSR_MEMd_DEFINED   1
 
#define XED_IFORM_VSUBBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBPS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VSUBPS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBSD_XMMdq_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_VSUBSD_XMMdq_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd_DEFINED   1
 
#define XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd_DEFINED   1
 
#define XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VTESTPD_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VTESTPD_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VTESTPD_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VTESTPD_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VTESTPS_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VTESTPS_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VTESTPS_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VTESTPS_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VUCOMISD_XMMdq_MEMq_DEFINED   1
 
#define XED_IFORM_VUCOMISD_XMMdq_XMMq_DEFINED   1
 
#define XED_IFORM_VUCOMISD_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VUCOMISH_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VUCOMISS_XMMdq_MEMd_DEFINED   1
 
#define XED_IFORM_VUCOMISS_XMMdq_XMMd_DEFINED   1
 
#define XED_IFORM_VUCOMISS_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VUCOMXSD_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VUCOMXSD_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VUCOMXSH_XMMf16_MEMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VUCOMXSH_XMMf16_XMMf16_AVX512_DEFINED   1
 
#define XED_IFORM_VUCOMXSS_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VUCOMXSS_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1
 
#define XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1
 
#define XED_IFORM_VXORPD_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VXORPD_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VXORPD_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VXORPD_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1
 
#define XED_IFORM_VXORPS_XMMdq_XMMdq_MEMdq_DEFINED   1
 
#define XED_IFORM_VXORPS_XMMdq_XMMdq_XMMdq_DEFINED   1
 
#define XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VXORPS_YMMqq_YMMqq_MEMqq_DEFINED   1
 
#define XED_IFORM_VXORPS_YMMqq_YMMqq_YMMqq_DEFINED   1
 
#define XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1
 
#define XED_IFORM_VZEROALL_DEFINED   1
 
#define XED_IFORM_VZEROUPPER_DEFINED   1
 
#define XED_IFORM_WBINVD_DEFINED   1
 
#define XED_IFORM_WBNOINVD_DEFINED   1
 
#define XED_IFORM_WRFSBASE_GPRy_DEFINED   1
 
#define XED_IFORM_WRGSBASE_GPRy_DEFINED   1
 
#define XED_IFORM_WRMSR_DEFINED   1
 
#define XED_IFORM_WRMSRLIST_DEFINED   1
 
#define XED_IFORM_WRMSRNS_DEFINED   1
 
#define XED_IFORM_WRMSRNS_IMM32_GPR64u64_APX_DEFINED   1
 
#define XED_IFORM_WRMSRNS_IMM32_GPR64u64_DEFINED   1
 
#define XED_IFORM_WRPKRU_DEFINED   1
 
#define XED_IFORM_WRSSD_MEMu32_GPR32u32_APX_DEFINED   1
 
#define XED_IFORM_WRSSD_MEMu32_GPR32u32_DEFINED   1
 
#define XED_IFORM_WRSSQ_MEMu64_GPR64u64_APX_DEFINED   1
 
#define XED_IFORM_WRSSQ_MEMu64_GPR64u64_DEFINED   1
 
#define XED_IFORM_WRUSSD_MEMu32_GPR32u32_APX_DEFINED   1
 
#define XED_IFORM_WRUSSD_MEMu32_GPR32u32_DEFINED   1
 
#define XED_IFORM_WRUSSQ_MEMu64_GPR64u64_APX_DEFINED   1
 
#define XED_IFORM_WRUSSQ_MEMu64_GPR64u64_DEFINED   1
 
#define XED_IFORM_XABORT_IMMb_DEFINED   1
 
#define XED_IFORM_XADD_GPR8_GPR8_DEFINED   1
 
#define XED_IFORM_XADD_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_XADD_LOCK_MEMb_GPR8_DEFINED   1
 
#define XED_IFORM_XADD_LOCK_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_XADD_MEMb_GPR8_DEFINED   1
 
#define XED_IFORM_XADD_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_XBEGIN_RELBRz_DEFINED   1
 
#define XED_IFORM_XCHG_GPR8_GPR8_DEFINED   1
 
#define XED_IFORM_XCHG_GPRv_GPRv_DEFINED   1
 
#define XED_IFORM_XCHG_GPRv_OrAX_DEFINED   1
 
#define XED_IFORM_XCHG_MEMb_GPR8_DEFINED   1
 
#define XED_IFORM_XCHG_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_XEND_DEFINED   1
 
#define XED_IFORM_XGETBV_DEFINED   1
 
#define XED_IFORM_XLAT_DEFINED   1
 
#define XED_IFORM_XOR_AL_IMMb_DEFINED   1
 
#define XED_IFORM_XOR_GPR8_GPR8_30_DEFINED   1
 
#define XED_IFORM_XOR_GPR8_GPR8_32_DEFINED   1
 
#define XED_IFORM_XOR_GPR8_IMMb_80r6_DEFINED   1
 
#define XED_IFORM_XOR_GPR8_IMMb_82r6_DEFINED   1
 
#define XED_IFORM_XOR_GPR8_MEMb_DEFINED   1
 
#define XED_IFORM_XOR_GPR8i8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_XOR_GPR8i8_GPR8i8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_XOR_GPR8i8_GPR8i8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_XOR_GPR8i8_GPR8i8_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_XOR_GPR8i8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_XOR_GPR8i8_MEMi8_APX_DEFINED   1
 
#define XED_IFORM_XOR_GPR8i8_MEMi8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_XOR_GPR8i8_MEMi8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_XOR_GPRv_GPRv_31_DEFINED   1
 
#define XED_IFORM_XOR_GPRv_GPRv_33_DEFINED   1
 
#define XED_IFORM_XOR_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_XOR_GPRv_GPRv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_XOR_GPRv_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_XOR_GPRv_GPRv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_XOR_GPRv_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_XOR_GPRv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_XOR_GPRv_IMMb_DEFINED   1
 
#define XED_IFORM_XOR_GPRv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_XOR_GPRv_IMMz_DEFINED   1
 
#define XED_IFORM_XOR_GPRv_MEMv_APX_DEFINED   1
 
#define XED_IFORM_XOR_GPRv_MEMv_DEFINED   1
 
#define XED_IFORM_XOR_GPRv_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_XOR_GPRv_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_XOR_GPRv_MEMv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_XOR_LOCK_MEMb_GPR8_DEFINED   1
 
#define XED_IFORM_XOR_LOCK_MEMb_IMMb_80r6_DEFINED   1
 
#define XED_IFORM_XOR_LOCK_MEMb_IMMb_82r6_DEFINED   1
 
#define XED_IFORM_XOR_LOCK_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_XOR_LOCK_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_XOR_LOCK_MEMv_IMMz_DEFINED   1
 
#define XED_IFORM_XOR_MEMb_GPR8_DEFINED   1
 
#define XED_IFORM_XOR_MEMb_IMMb_80r6_DEFINED   1
 
#define XED_IFORM_XOR_MEMb_IMMb_82r6_DEFINED   1
 
#define XED_IFORM_XOR_MEMi8_GPR8i8_APX_DEFINED   1
 
#define XED_IFORM_XOR_MEMi8_IMM8_APX_DEFINED   1
 
#define XED_IFORM_XOR_MEMv_GPRv_APX_DEFINED   1
 
#define XED_IFORM_XOR_MEMv_GPRv_DEFINED   1
 
#define XED_IFORM_XOR_MEMv_IMM8_APX_DEFINED   1
 
#define XED_IFORM_XOR_MEMv_IMMb_DEFINED   1
 
#define XED_IFORM_XOR_MEMv_IMMz_APX_DEFINED   1
 
#define XED_IFORM_XOR_MEMv_IMMz_DEFINED   1
 
#define XED_IFORM_XOR_OrAX_IMMz_DEFINED   1
 
#define XED_IFORM_XORPD_XMMxuq_MEMxuq_DEFINED   1
 
#define XED_IFORM_XORPD_XMMxuq_XMMxuq_DEFINED   1
 
#define XED_IFORM_XORPS_XMMxud_MEMxud_DEFINED   1
 
#define XED_IFORM_XORPS_XMMxud_XMMxud_DEFINED   1
 
#define XED_IFORM_XRESLDTRK_DEFINED   1
 
#define XED_IFORM_XRSTOR64_MEMmxsave_DEFINED   1
 
#define XED_IFORM_XRSTOR_MEMmxsave_DEFINED   1
 
#define XED_IFORM_XRSTORS64_MEMmxsave_DEFINED   1
 
#define XED_IFORM_XRSTORS_MEMmxsave_DEFINED   1
 
#define XED_IFORM_XSAVE64_MEMmxsave_DEFINED   1
 
#define XED_IFORM_XSAVE_MEMmxsave_DEFINED   1
 
#define XED_IFORM_XSAVEC64_MEMmxsave_DEFINED   1
 
#define XED_IFORM_XSAVEC_MEMmxsave_DEFINED   1
 
#define XED_IFORM_XSAVEOPT64_MEMmxsave_DEFINED   1
 
#define XED_IFORM_XSAVEOPT_MEMmxsave_DEFINED   1
 
#define XED_IFORM_XSAVES64_MEMmxsave_DEFINED   1
 
#define XED_IFORM_XSAVES_MEMmxsave_DEFINED   1
 
#define XED_IFORM_XSETBV_DEFINED   1
 
#define XED_IFORM_XSTORE_DEFINED   1
 
#define XED_IFORM_XSUSLDTRK_DEFINED   1
 
#define XED_IFORM_XTEST_DEFINED   1
 

Enumerations

enum  xed_iform_enum_t {
  XED_IFORM_INVALID =0 ,
  XED_IFORM_AAA =1 ,
  XED_IFORM_AAD_IMMb =2 ,
  XED_IFORM_AADD_MEM32_GPR32 =3 ,
  XED_IFORM_AADD_MEM64_GPR64 =4 ,
  XED_IFORM_AADD_MEMi32_GPR32i32_APX =5 ,
  XED_IFORM_AADD_MEMi64_GPR64i64_APX =6 ,
  XED_IFORM_AAM_IMMb =7 ,
  XED_IFORM_AAND_MEM32_GPR32 =8 ,
  XED_IFORM_AAND_MEM64_GPR64 =9 ,
  XED_IFORM_AAND_MEMi32_GPR32i32_APX =10 ,
  XED_IFORM_AAND_MEMi64_GPR64i64_APX =11 ,
  XED_IFORM_AAS =12 ,
  XED_IFORM_ADC_AL_IMMb =13 ,
  XED_IFORM_ADC_GPR8_GPR8_10 =14 ,
  XED_IFORM_ADC_GPR8_GPR8_12 =15 ,
  XED_IFORM_ADC_GPR8_IMMb_80r2 =16 ,
  XED_IFORM_ADC_GPR8_IMMb_82r2 =17 ,
  XED_IFORM_ADC_GPR8_MEMb =18 ,
  XED_IFORM_ADC_GPR8i8_GPR8i8_APX =19 ,
  XED_IFORM_ADC_GPR8i8_GPR8i8_GPR8i8_APX =20 ,
  XED_IFORM_ADC_GPR8i8_GPR8i8_IMM8_APX =21 ,
  XED_IFORM_ADC_GPR8i8_GPR8i8_MEMi8_APX =22 ,
  XED_IFORM_ADC_GPR8i8_IMM8_APX =23 ,
  XED_IFORM_ADC_GPR8i8_MEMi8_APX =24 ,
  XED_IFORM_ADC_GPR8i8_MEMi8_GPR8i8_APX =25 ,
  XED_IFORM_ADC_GPR8i8_MEMi8_IMM8_APX =26 ,
  XED_IFORM_ADC_GPRv_GPRv_11 =27 ,
  XED_IFORM_ADC_GPRv_GPRv_13 =28 ,
  XED_IFORM_ADC_GPRv_GPRv_APX =29 ,
  XED_IFORM_ADC_GPRv_GPRv_GPRv_APX =30 ,
  XED_IFORM_ADC_GPRv_GPRv_IMM8_APX =31 ,
  XED_IFORM_ADC_GPRv_GPRv_IMMz_APX =32 ,
  XED_IFORM_ADC_GPRv_GPRv_MEMv_APX =33 ,
  XED_IFORM_ADC_GPRv_IMM8_APX =34 ,
  XED_IFORM_ADC_GPRv_IMMb =35 ,
  XED_IFORM_ADC_GPRv_IMMz =36 ,
  XED_IFORM_ADC_GPRv_IMMz_APX =37 ,
  XED_IFORM_ADC_GPRv_MEMv =38 ,
  XED_IFORM_ADC_GPRv_MEMv_APX =39 ,
  XED_IFORM_ADC_GPRv_MEMv_GPRv_APX =40 ,
  XED_IFORM_ADC_GPRv_MEMv_IMM8_APX =41 ,
  XED_IFORM_ADC_GPRv_MEMv_IMMz_APX =42 ,
  XED_IFORM_ADC_MEMb_GPR8 =43 ,
  XED_IFORM_ADC_MEMb_IMMb_80r2 =44 ,
  XED_IFORM_ADC_MEMb_IMMb_82r2 =45 ,
  XED_IFORM_ADC_MEMi8_GPR8i8_APX =46 ,
  XED_IFORM_ADC_MEMi8_IMM8_APX =47 ,
  XED_IFORM_ADC_MEMv_GPRv =48 ,
  XED_IFORM_ADC_MEMv_GPRv_APX =49 ,
  XED_IFORM_ADC_MEMv_IMM8_APX =50 ,
  XED_IFORM_ADC_MEMv_IMMb =51 ,
  XED_IFORM_ADC_MEMv_IMMz =52 ,
  XED_IFORM_ADC_MEMv_IMMz_APX =53 ,
  XED_IFORM_ADC_OrAX_IMMz =54 ,
  XED_IFORM_ADCX_GPR32d_GPR32d =55 ,
  XED_IFORM_ADCX_GPR32d_MEMd =56 ,
  XED_IFORM_ADCX_GPR32i32_GPR32i32_APX =57 ,
  XED_IFORM_ADCX_GPR32i32_GPR32i32_GPR32i32_APX =58 ,
  XED_IFORM_ADCX_GPR32i32_GPR32i32_MEMi32_APX =59 ,
  XED_IFORM_ADCX_GPR32i32_MEMi32_APX =60 ,
  XED_IFORM_ADCX_GPR64i64_GPR64i64_APX =61 ,
  XED_IFORM_ADCX_GPR64i64_GPR64i64_GPR64i64_APX =62 ,
  XED_IFORM_ADCX_GPR64i64_GPR64i64_MEMi64_APX =63 ,
  XED_IFORM_ADCX_GPR64i64_MEMi64_APX =64 ,
  XED_IFORM_ADCX_GPR64q_GPR64q =65 ,
  XED_IFORM_ADCX_GPR64q_MEMq =66 ,
  XED_IFORM_ADC_LOCK_MEMb_GPR8 =67 ,
  XED_IFORM_ADC_LOCK_MEMb_IMMb_80r2 =68 ,
  XED_IFORM_ADC_LOCK_MEMb_IMMb_82r2 =69 ,
  XED_IFORM_ADC_LOCK_MEMv_GPRv =70 ,
  XED_IFORM_ADC_LOCK_MEMv_IMMb =71 ,
  XED_IFORM_ADC_LOCK_MEMv_IMMz =72 ,
  XED_IFORM_ADD_AL_IMMb =73 ,
  XED_IFORM_ADD_GPR8_GPR8_00 =74 ,
  XED_IFORM_ADD_GPR8_GPR8_02 =75 ,
  XED_IFORM_ADD_GPR8_IMMb_80r0 =76 ,
  XED_IFORM_ADD_GPR8_IMMb_82r0 =77 ,
  XED_IFORM_ADD_GPR8_MEMb =78 ,
  XED_IFORM_ADD_GPR8i8_GPR8i8_APX =79 ,
  XED_IFORM_ADD_GPR8i8_GPR8i8_GPR8i8_APX =80 ,
  XED_IFORM_ADD_GPR8i8_GPR8i8_IMM8_APX =81 ,
  XED_IFORM_ADD_GPR8i8_GPR8i8_MEMi8_APX =82 ,
  XED_IFORM_ADD_GPR8i8_IMM8_APX =83 ,
  XED_IFORM_ADD_GPR8i8_MEMi8_APX =84 ,
  XED_IFORM_ADD_GPR8i8_MEMi8_GPR8i8_APX =85 ,
  XED_IFORM_ADD_GPR8i8_MEMi8_IMM8_APX =86 ,
  XED_IFORM_ADD_GPRv_GPRv_01 =87 ,
  XED_IFORM_ADD_GPRv_GPRv_03 =88 ,
  XED_IFORM_ADD_GPRv_GPRv_APX =89 ,
  XED_IFORM_ADD_GPRv_GPRv_GPRv_APX =90 ,
  XED_IFORM_ADD_GPRv_GPRv_IMM8_APX =91 ,
  XED_IFORM_ADD_GPRv_GPRv_IMMz_APX =92 ,
  XED_IFORM_ADD_GPRv_GPRv_MEMv_APX =93 ,
  XED_IFORM_ADD_GPRv_IMM8_APX =94 ,
  XED_IFORM_ADD_GPRv_IMMb =95 ,
  XED_IFORM_ADD_GPRv_IMMz =96 ,
  XED_IFORM_ADD_GPRv_IMMz_APX =97 ,
  XED_IFORM_ADD_GPRv_MEMv =98 ,
  XED_IFORM_ADD_GPRv_MEMv_APX =99 ,
  XED_IFORM_ADD_GPRv_MEMv_GPRv_APX =100 ,
  XED_IFORM_ADD_GPRv_MEMv_IMM8_APX =101 ,
  XED_IFORM_ADD_GPRv_MEMv_IMMz_APX =102 ,
  XED_IFORM_ADD_MEMb_GPR8 =103 ,
  XED_IFORM_ADD_MEMb_IMMb_80r0 =104 ,
  XED_IFORM_ADD_MEMb_IMMb_82r0 =105 ,
  XED_IFORM_ADD_MEMi8_GPR8i8_APX =106 ,
  XED_IFORM_ADD_MEMi8_IMM8_APX =107 ,
  XED_IFORM_ADD_MEMv_GPRv =108 ,
  XED_IFORM_ADD_MEMv_GPRv_APX =109 ,
  XED_IFORM_ADD_MEMv_IMM8_APX =110 ,
  XED_IFORM_ADD_MEMv_IMMb =111 ,
  XED_IFORM_ADD_MEMv_IMMz =112 ,
  XED_IFORM_ADD_MEMv_IMMz_APX =113 ,
  XED_IFORM_ADD_OrAX_IMMz =114 ,
  XED_IFORM_ADDPD_XMMpd_MEMpd =115 ,
  XED_IFORM_ADDPD_XMMpd_XMMpd =116 ,
  XED_IFORM_ADDPS_XMMps_MEMps =117 ,
  XED_IFORM_ADDPS_XMMps_XMMps =118 ,
  XED_IFORM_ADDSD_XMMsd_MEMsd =119 ,
  XED_IFORM_ADDSD_XMMsd_XMMsd =120 ,
  XED_IFORM_ADDSS_XMMss_MEMss =121 ,
  XED_IFORM_ADDSS_XMMss_XMMss =122 ,
  XED_IFORM_ADDSUBPD_XMMpd_MEMpd =123 ,
  XED_IFORM_ADDSUBPD_XMMpd_XMMpd =124 ,
  XED_IFORM_ADDSUBPS_XMMps_MEMps =125 ,
  XED_IFORM_ADDSUBPS_XMMps_XMMps =126 ,
  XED_IFORM_ADD_LOCK_MEMb_GPR8 =127 ,
  XED_IFORM_ADD_LOCK_MEMb_IMMb_80r0 =128 ,
  XED_IFORM_ADD_LOCK_MEMb_IMMb_82r0 =129 ,
  XED_IFORM_ADD_LOCK_MEMv_GPRv =130 ,
  XED_IFORM_ADD_LOCK_MEMv_IMMb =131 ,
  XED_IFORM_ADD_LOCK_MEMv_IMMz =132 ,
  XED_IFORM_ADOX_GPR32d_GPR32d =133 ,
  XED_IFORM_ADOX_GPR32d_MEMd =134 ,
  XED_IFORM_ADOX_GPR32i32_GPR32i32_APX =135 ,
  XED_IFORM_ADOX_GPR32i32_GPR32i32_GPR32i32_APX =136 ,
  XED_IFORM_ADOX_GPR32i32_GPR32i32_MEMi32_APX =137 ,
  XED_IFORM_ADOX_GPR32i32_MEMi32_APX =138 ,
  XED_IFORM_ADOX_GPR64i64_GPR64i64_APX =139 ,
  XED_IFORM_ADOX_GPR64i64_GPR64i64_GPR64i64_APX =140 ,
  XED_IFORM_ADOX_GPR64i64_GPR64i64_MEMi64_APX =141 ,
  XED_IFORM_ADOX_GPR64i64_MEMi64_APX =142 ,
  XED_IFORM_ADOX_GPR64q_GPR64q =143 ,
  XED_IFORM_ADOX_GPR64q_MEMq =144 ,
  XED_IFORM_AESDEC_XMMdq_MEMdq =145 ,
  XED_IFORM_AESDEC_XMMdq_XMMdq =146 ,
  XED_IFORM_AESDEC128KL_XMMu8_MEMu8 =147 ,
  XED_IFORM_AESDEC256KL_XMMu8_MEMu8 =148 ,
  XED_IFORM_AESDECLAST_XMMdq_MEMdq =149 ,
  XED_IFORM_AESDECLAST_XMMdq_XMMdq =150 ,
  XED_IFORM_AESDECWIDE128KL_MEMu8 =151 ,
  XED_IFORM_AESDECWIDE256KL_MEMu8 =152 ,
  XED_IFORM_AESENC_XMMdq_MEMdq =153 ,
  XED_IFORM_AESENC_XMMdq_XMMdq =154 ,
  XED_IFORM_AESENC128KL_XMMu8_MEMu8 =155 ,
  XED_IFORM_AESENC256KL_XMMu8_MEMu8 =156 ,
  XED_IFORM_AESENCLAST_XMMdq_MEMdq =157 ,
  XED_IFORM_AESENCLAST_XMMdq_XMMdq =158 ,
  XED_IFORM_AESENCWIDE128KL_MEMu8 =159 ,
  XED_IFORM_AESENCWIDE256KL_MEMu8 =160 ,
  XED_IFORM_AESIMC_XMMdq_MEMdq =161 ,
  XED_IFORM_AESIMC_XMMdq_XMMdq =162 ,
  XED_IFORM_AESKEYGENASSIST_XMMdq_MEMdq_IMMb =163 ,
  XED_IFORM_AESKEYGENASSIST_XMMdq_XMMdq_IMMb =164 ,
  XED_IFORM_AND_AL_IMMb =165 ,
  XED_IFORM_AND_GPR8_GPR8_20 =166 ,
  XED_IFORM_AND_GPR8_GPR8_22 =167 ,
  XED_IFORM_AND_GPR8_IMMb_80r4 =168 ,
  XED_IFORM_AND_GPR8_IMMb_82r4 =169 ,
  XED_IFORM_AND_GPR8_MEMb =170 ,
  XED_IFORM_AND_GPR8i8_GPR8i8_APX =171 ,
  XED_IFORM_AND_GPR8i8_GPR8i8_GPR8i8_APX =172 ,
  XED_IFORM_AND_GPR8i8_GPR8i8_IMM8_APX =173 ,
  XED_IFORM_AND_GPR8i8_GPR8i8_MEMi8_APX =174 ,
  XED_IFORM_AND_GPR8i8_IMM8_APX =175 ,
  XED_IFORM_AND_GPR8i8_MEMi8_APX =176 ,
  XED_IFORM_AND_GPR8i8_MEMi8_GPR8i8_APX =177 ,
  XED_IFORM_AND_GPR8i8_MEMi8_IMM8_APX =178 ,
  XED_IFORM_AND_GPRv_GPRv_21 =179 ,
  XED_IFORM_AND_GPRv_GPRv_23 =180 ,
  XED_IFORM_AND_GPRv_GPRv_APX =181 ,
  XED_IFORM_AND_GPRv_GPRv_GPRv_APX =182 ,
  XED_IFORM_AND_GPRv_GPRv_IMM8_APX =183 ,
  XED_IFORM_AND_GPRv_GPRv_IMMz_APX =184 ,
  XED_IFORM_AND_GPRv_GPRv_MEMv_APX =185 ,
  XED_IFORM_AND_GPRv_IMM8_APX =186 ,
  XED_IFORM_AND_GPRv_IMMb =187 ,
  XED_IFORM_AND_GPRv_IMMz =188 ,
  XED_IFORM_AND_GPRv_IMMz_APX =189 ,
  XED_IFORM_AND_GPRv_MEMv =190 ,
  XED_IFORM_AND_GPRv_MEMv_APX =191 ,
  XED_IFORM_AND_GPRv_MEMv_GPRv_APX =192 ,
  XED_IFORM_AND_GPRv_MEMv_IMM8_APX =193 ,
  XED_IFORM_AND_GPRv_MEMv_IMMz_APX =194 ,
  XED_IFORM_AND_MEMb_GPR8 =195 ,
  XED_IFORM_AND_MEMb_IMMb_80r4 =196 ,
  XED_IFORM_AND_MEMb_IMMb_82r4 =197 ,
  XED_IFORM_AND_MEMi8_GPR8i8_APX =198 ,
  XED_IFORM_AND_MEMi8_IMM8_APX =199 ,
  XED_IFORM_AND_MEMv_GPRv =200 ,
  XED_IFORM_AND_MEMv_GPRv_APX =201 ,
  XED_IFORM_AND_MEMv_IMM8_APX =202 ,
  XED_IFORM_AND_MEMv_IMMb =203 ,
  XED_IFORM_AND_MEMv_IMMz =204 ,
  XED_IFORM_AND_MEMv_IMMz_APX =205 ,
  XED_IFORM_AND_OrAX_IMMz =206 ,
  XED_IFORM_ANDN_GPR32d_GPR32d_GPR32d =207 ,
  XED_IFORM_ANDN_GPR32d_GPR32d_MEMd =208 ,
  XED_IFORM_ANDN_GPR32i32_GPR32i32_GPR32i32_APX =209 ,
  XED_IFORM_ANDN_GPR32i32_GPR32i32_MEMi32_APX =210 ,
  XED_IFORM_ANDN_GPR64i64_GPR64i64_GPR64i64_APX =211 ,
  XED_IFORM_ANDN_GPR64i64_GPR64i64_MEMi64_APX =212 ,
  XED_IFORM_ANDN_GPR64q_GPR64q_GPR64q =213 ,
  XED_IFORM_ANDN_GPR64q_GPR64q_MEMq =214 ,
  XED_IFORM_ANDNPD_XMMxuq_MEMxuq =215 ,
  XED_IFORM_ANDNPD_XMMxuq_XMMxuq =216 ,
  XED_IFORM_ANDNPS_XMMxud_MEMxud =217 ,
  XED_IFORM_ANDNPS_XMMxud_XMMxud =218 ,
  XED_IFORM_ANDPD_XMMxuq_MEMxuq =219 ,
  XED_IFORM_ANDPD_XMMxuq_XMMxuq =220 ,
  XED_IFORM_ANDPS_XMMxud_MEMxud =221 ,
  XED_IFORM_ANDPS_XMMxud_XMMxud =222 ,
  XED_IFORM_AND_LOCK_MEMb_GPR8 =223 ,
  XED_IFORM_AND_LOCK_MEMb_IMMb_80r4 =224 ,
  XED_IFORM_AND_LOCK_MEMb_IMMb_82r4 =225 ,
  XED_IFORM_AND_LOCK_MEMv_GPRv =226 ,
  XED_IFORM_AND_LOCK_MEMv_IMMb =227 ,
  XED_IFORM_AND_LOCK_MEMv_IMMz =228 ,
  XED_IFORM_AOR_MEM32_GPR32 =229 ,
  XED_IFORM_AOR_MEM64_GPR64 =230 ,
  XED_IFORM_AOR_MEMi32_GPR32i32_APX =231 ,
  XED_IFORM_AOR_MEMi64_GPR64i64_APX =232 ,
  XED_IFORM_ARPL_GPR16_GPR16 =233 ,
  XED_IFORM_ARPL_MEMw_GPR16 =234 ,
  XED_IFORM_AXOR_MEM32_GPR32 =235 ,
  XED_IFORM_AXOR_MEM64_GPR64 =236 ,
  XED_IFORM_AXOR_MEMi32_GPR32i32_APX =237 ,
  XED_IFORM_AXOR_MEMi64_GPR64i64_APX =238 ,
  XED_IFORM_BEXTR_GPR32d_GPR32d_GPR32d =239 ,
  XED_IFORM_BEXTR_GPR32d_MEMd_GPR32d =240 ,
  XED_IFORM_BEXTR_GPR32i32_GPR32i32_GPR32i32_APX =241 ,
  XED_IFORM_BEXTR_GPR32i32_MEMi32_GPR32i32_APX =242 ,
  XED_IFORM_BEXTR_GPR64i64_GPR64i64_GPR64i64_APX =243 ,
  XED_IFORM_BEXTR_GPR64i64_MEMi64_GPR64i64_APX =244 ,
  XED_IFORM_BEXTR_GPR64q_GPR64q_GPR64q =245 ,
  XED_IFORM_BEXTR_GPR64q_MEMq_GPR64q =246 ,
  XED_IFORM_BEXTR_XOP_GPR32d_GPR32d_IMMd =247 ,
  XED_IFORM_BEXTR_XOP_GPR32d_MEMd_IMMd =248 ,
  XED_IFORM_BEXTR_XOP_GPRyy_GPRyy_IMMd =249 ,
  XED_IFORM_BEXTR_XOP_GPRyy_MEMy_IMMd =250 ,
  XED_IFORM_BLCFILL_GPR32d_GPR32d =251 ,
  XED_IFORM_BLCFILL_GPR32d_MEMd =252 ,
  XED_IFORM_BLCFILL_GPRyy_GPRyy =253 ,
  XED_IFORM_BLCFILL_GPRyy_MEMy =254 ,
  XED_IFORM_BLCI_GPR32d_GPR32d =255 ,
  XED_IFORM_BLCI_GPR32d_MEMd =256 ,
  XED_IFORM_BLCI_GPRyy_GPRyy =257 ,
  XED_IFORM_BLCI_GPRyy_MEMy =258 ,
  XED_IFORM_BLCIC_GPR32d_GPR32d =259 ,
  XED_IFORM_BLCIC_GPR32d_MEMd =260 ,
  XED_IFORM_BLCIC_GPRyy_GPRyy =261 ,
  XED_IFORM_BLCIC_GPRyy_MEMy =262 ,
  XED_IFORM_BLCMSK_GPR32d_GPR32d =263 ,
  XED_IFORM_BLCMSK_GPR32d_MEMd =264 ,
  XED_IFORM_BLCMSK_GPRyy_GPRyy =265 ,
  XED_IFORM_BLCMSK_GPRyy_MEMy =266 ,
  XED_IFORM_BLCS_GPR32d_GPR32d =267 ,
  XED_IFORM_BLCS_GPR32d_MEMd =268 ,
  XED_IFORM_BLCS_GPRyy_GPRyy =269 ,
  XED_IFORM_BLCS_GPRyy_MEMy =270 ,
  XED_IFORM_BLENDPD_XMMdq_MEMdq_IMMb =271 ,
  XED_IFORM_BLENDPD_XMMdq_XMMdq_IMMb =272 ,
  XED_IFORM_BLENDPS_XMMdq_MEMdq_IMMb =273 ,
  XED_IFORM_BLENDPS_XMMdq_XMMdq_IMMb =274 ,
  XED_IFORM_BLENDVPD_XMMdq_MEMdq =275 ,
  XED_IFORM_BLENDVPD_XMMdq_XMMdq =276 ,
  XED_IFORM_BLENDVPS_XMMdq_MEMdq =277 ,
  XED_IFORM_BLENDVPS_XMMdq_XMMdq =278 ,
  XED_IFORM_BLSFILL_GPR32d_GPR32d =279 ,
  XED_IFORM_BLSFILL_GPR32d_MEMd =280 ,
  XED_IFORM_BLSFILL_GPRyy_GPRyy =281 ,
  XED_IFORM_BLSFILL_GPRyy_MEMy =282 ,
  XED_IFORM_BLSI_GPR32d_GPR32d =283 ,
  XED_IFORM_BLSI_GPR32d_MEMd =284 ,
  XED_IFORM_BLSI_GPR32i32_GPR32i32_APX =285 ,
  XED_IFORM_BLSI_GPR32i32_MEMi32_APX =286 ,
  XED_IFORM_BLSI_GPR64i64_GPR64i64_APX =287 ,
  XED_IFORM_BLSI_GPR64i64_MEMi64_APX =288 ,
  XED_IFORM_BLSI_GPR64q_GPR64q =289 ,
  XED_IFORM_BLSI_GPR64q_MEMq =290 ,
  XED_IFORM_BLSIC_GPR32d_GPR32d =291 ,
  XED_IFORM_BLSIC_GPR32d_MEMd =292 ,
  XED_IFORM_BLSIC_GPRyy_GPRyy =293 ,
  XED_IFORM_BLSIC_GPRyy_MEMy =294 ,
  XED_IFORM_BLSMSK_GPR32d_GPR32d =295 ,
  XED_IFORM_BLSMSK_GPR32d_MEMd =296 ,
  XED_IFORM_BLSMSK_GPR32i32_GPR32i32_APX =297 ,
  XED_IFORM_BLSMSK_GPR32i32_MEMi32_APX =298 ,
  XED_IFORM_BLSMSK_GPR64i64_GPR64i64_APX =299 ,
  XED_IFORM_BLSMSK_GPR64i64_MEMi64_APX =300 ,
  XED_IFORM_BLSMSK_GPR64q_GPR64q =301 ,
  XED_IFORM_BLSMSK_GPR64q_MEMq =302 ,
  XED_IFORM_BLSR_GPR32d_GPR32d =303 ,
  XED_IFORM_BLSR_GPR32d_MEMd =304 ,
  XED_IFORM_BLSR_GPR32i32_GPR32i32_APX =305 ,
  XED_IFORM_BLSR_GPR32i32_MEMi32_APX =306 ,
  XED_IFORM_BLSR_GPR64i64_GPR64i64_APX =307 ,
  XED_IFORM_BLSR_GPR64i64_MEMi64_APX =308 ,
  XED_IFORM_BLSR_GPR64q_GPR64q =309 ,
  XED_IFORM_BLSR_GPR64q_MEMq =310 ,
  XED_IFORM_BNDCL_BND_AGEN =311 ,
  XED_IFORM_BNDCL_BND_GPR32 =312 ,
  XED_IFORM_BNDCL_BND_GPR64 =313 ,
  XED_IFORM_BNDCN_BND_AGEN =314 ,
  XED_IFORM_BNDCN_BND_GPR32 =315 ,
  XED_IFORM_BNDCN_BND_GPR64 =316 ,
  XED_IFORM_BNDCU_BND_AGEN =317 ,
  XED_IFORM_BNDCU_BND_GPR32 =318 ,
  XED_IFORM_BNDCU_BND_GPR64 =319 ,
  XED_IFORM_BNDLDX_BND_MEMbnd32 =320 ,
  XED_IFORM_BNDLDX_BND_MEMbnd64 =321 ,
  XED_IFORM_BNDMK_BND_AGEN =322 ,
  XED_IFORM_BNDMOV_BND_BND =323 ,
  XED_IFORM_BNDMOV_BND_MEMdq =324 ,
  XED_IFORM_BNDMOV_BND_MEMq =325 ,
  XED_IFORM_BNDMOV_MEMdq_BND =326 ,
  XED_IFORM_BNDMOV_MEMq_BND =327 ,
  XED_IFORM_BNDSTX_MEMbnd32_BND =328 ,
  XED_IFORM_BNDSTX_MEMbnd64_BND =329 ,
  XED_IFORM_BOUND_GPR16_MEMa16 =330 ,
  XED_IFORM_BOUND_GPR32_MEMa32 =331 ,
  XED_IFORM_BSF_GPRv_GPRv =332 ,
  XED_IFORM_BSF_GPRv_MEMv =333 ,
  XED_IFORM_BSR_GPRv_GPRv =334 ,
  XED_IFORM_BSR_GPRv_MEMv =335 ,
  XED_IFORM_BSWAP_GPRv =336 ,
  XED_IFORM_BT_GPRv_GPRv =337 ,
  XED_IFORM_BT_GPRv_IMMb =338 ,
  XED_IFORM_BT_MEMv_GPRv =339 ,
  XED_IFORM_BT_MEMv_IMMb =340 ,
  XED_IFORM_BTC_GPRv_GPRv =341 ,
  XED_IFORM_BTC_GPRv_IMMb =342 ,
  XED_IFORM_BTC_MEMv_GPRv =343 ,
  XED_IFORM_BTC_MEMv_IMMb =344 ,
  XED_IFORM_BTC_LOCK_MEMv_GPRv =345 ,
  XED_IFORM_BTC_LOCK_MEMv_IMMb =346 ,
  XED_IFORM_BTR_GPRv_GPRv =347 ,
  XED_IFORM_BTR_GPRv_IMMb =348 ,
  XED_IFORM_BTR_MEMv_GPRv =349 ,
  XED_IFORM_BTR_MEMv_IMMb =350 ,
  XED_IFORM_BTR_LOCK_MEMv_GPRv =351 ,
  XED_IFORM_BTR_LOCK_MEMv_IMMb =352 ,
  XED_IFORM_BTS_GPRv_GPRv =353 ,
  XED_IFORM_BTS_GPRv_IMMb =354 ,
  XED_IFORM_BTS_MEMv_GPRv =355 ,
  XED_IFORM_BTS_MEMv_IMMb =356 ,
  XED_IFORM_BTS_LOCK_MEMv_GPRv =357 ,
  XED_IFORM_BTS_LOCK_MEMv_IMMb =358 ,
  XED_IFORM_BZHI_GPR32d_GPR32d_GPR32d =359 ,
  XED_IFORM_BZHI_GPR32d_MEMd_GPR32d =360 ,
  XED_IFORM_BZHI_GPR32i32_GPR32i32_GPR32i32_APX =361 ,
  XED_IFORM_BZHI_GPR32i32_MEMi32_GPR32i32_APX =362 ,
  XED_IFORM_BZHI_GPR64i64_GPR64i64_GPR64i64_APX =363 ,
  XED_IFORM_BZHI_GPR64i64_MEMi64_GPR64i64_APX =364 ,
  XED_IFORM_BZHI_GPR64q_GPR64q_GPR64q =365 ,
  XED_IFORM_BZHI_GPR64q_MEMq_GPR64q =366 ,
  XED_IFORM_CALL_FAR_MEMp2 =367 ,
  XED_IFORM_CALL_FAR_PTRp_IMMw =368 ,
  XED_IFORM_CALL_NEAR_GPRv =369 ,
  XED_IFORM_CALL_NEAR_MEMv =370 ,
  XED_IFORM_CALL_NEAR_RELBRd =371 ,
  XED_IFORM_CALL_NEAR_RELBRz =372 ,
  XED_IFORM_CBW =373 ,
  XED_IFORM_CCMPB_GPR8i8_GPR8i8_DFV_APX =374 ,
  XED_IFORM_CCMPB_GPR8i8_IMM8_DFV_APX =375 ,
  XED_IFORM_CCMPB_GPR8i8_MEMi8_DFV_APX =376 ,
  XED_IFORM_CCMPB_GPRv_GPRv_DFV_APX =377 ,
  XED_IFORM_CCMPB_GPRv_IMM8_DFV_APX =378 ,
  XED_IFORM_CCMPB_GPRv_IMMz_DFV_APX =379 ,
  XED_IFORM_CCMPB_GPRv_MEMv_DFV_APX =380 ,
  XED_IFORM_CCMPB_MEMi8_GPR8i8_DFV_APX =381 ,
  XED_IFORM_CCMPB_MEMi8_IMM8_DFV_APX =382 ,
  XED_IFORM_CCMPB_MEMv_GPRv_DFV_APX =383 ,
  XED_IFORM_CCMPB_MEMv_IMM8_DFV_APX =384 ,
  XED_IFORM_CCMPB_MEMv_IMMz_DFV_APX =385 ,
  XED_IFORM_CCMPBE_GPR8i8_GPR8i8_DFV_APX =386 ,
  XED_IFORM_CCMPBE_GPR8i8_IMM8_DFV_APX =387 ,
  XED_IFORM_CCMPBE_GPR8i8_MEMi8_DFV_APX =388 ,
  XED_IFORM_CCMPBE_GPRv_GPRv_DFV_APX =389 ,
  XED_IFORM_CCMPBE_GPRv_IMM8_DFV_APX =390 ,
  XED_IFORM_CCMPBE_GPRv_IMMz_DFV_APX =391 ,
  XED_IFORM_CCMPBE_GPRv_MEMv_DFV_APX =392 ,
  XED_IFORM_CCMPBE_MEMi8_GPR8i8_DFV_APX =393 ,
  XED_IFORM_CCMPBE_MEMi8_IMM8_DFV_APX =394 ,
  XED_IFORM_CCMPBE_MEMv_GPRv_DFV_APX =395 ,
  XED_IFORM_CCMPBE_MEMv_IMM8_DFV_APX =396 ,
  XED_IFORM_CCMPBE_MEMv_IMMz_DFV_APX =397 ,
  XED_IFORM_CCMPF_GPR8i8_GPR8i8_DFV_APX =398 ,
  XED_IFORM_CCMPF_GPR8i8_IMM8_DFV_APX =399 ,
  XED_IFORM_CCMPF_GPR8i8_MEMi8_DFV_APX =400 ,
  XED_IFORM_CCMPF_GPRv_GPRv_DFV_APX =401 ,
  XED_IFORM_CCMPF_GPRv_IMM8_DFV_APX =402 ,
  XED_IFORM_CCMPF_GPRv_IMMz_DFV_APX =403 ,
  XED_IFORM_CCMPF_GPRv_MEMv_DFV_APX =404 ,
  XED_IFORM_CCMPF_MEMi8_GPR8i8_DFV_APX =405 ,
  XED_IFORM_CCMPF_MEMi8_IMM8_DFV_APX =406 ,
  XED_IFORM_CCMPF_MEMv_GPRv_DFV_APX =407 ,
  XED_IFORM_CCMPF_MEMv_IMM8_DFV_APX =408 ,
  XED_IFORM_CCMPF_MEMv_IMMz_DFV_APX =409 ,
  XED_IFORM_CCMPL_GPR8i8_GPR8i8_DFV_APX =410 ,
  XED_IFORM_CCMPL_GPR8i8_IMM8_DFV_APX =411 ,
  XED_IFORM_CCMPL_GPR8i8_MEMi8_DFV_APX =412 ,
  XED_IFORM_CCMPL_GPRv_GPRv_DFV_APX =413 ,
  XED_IFORM_CCMPL_GPRv_IMM8_DFV_APX =414 ,
  XED_IFORM_CCMPL_GPRv_IMMz_DFV_APX =415 ,
  XED_IFORM_CCMPL_GPRv_MEMv_DFV_APX =416 ,
  XED_IFORM_CCMPL_MEMi8_GPR8i8_DFV_APX =417 ,
  XED_IFORM_CCMPL_MEMi8_IMM8_DFV_APX =418 ,
  XED_IFORM_CCMPL_MEMv_GPRv_DFV_APX =419 ,
  XED_IFORM_CCMPL_MEMv_IMM8_DFV_APX =420 ,
  XED_IFORM_CCMPL_MEMv_IMMz_DFV_APX =421 ,
  XED_IFORM_CCMPLE_GPR8i8_GPR8i8_DFV_APX =422 ,
  XED_IFORM_CCMPLE_GPR8i8_IMM8_DFV_APX =423 ,
  XED_IFORM_CCMPLE_GPR8i8_MEMi8_DFV_APX =424 ,
  XED_IFORM_CCMPLE_GPRv_GPRv_DFV_APX =425 ,
  XED_IFORM_CCMPLE_GPRv_IMM8_DFV_APX =426 ,
  XED_IFORM_CCMPLE_GPRv_IMMz_DFV_APX =427 ,
  XED_IFORM_CCMPLE_GPRv_MEMv_DFV_APX =428 ,
  XED_IFORM_CCMPLE_MEMi8_GPR8i8_DFV_APX =429 ,
  XED_IFORM_CCMPLE_MEMi8_IMM8_DFV_APX =430 ,
  XED_IFORM_CCMPLE_MEMv_GPRv_DFV_APX =431 ,
  XED_IFORM_CCMPLE_MEMv_IMM8_DFV_APX =432 ,
  XED_IFORM_CCMPLE_MEMv_IMMz_DFV_APX =433 ,
  XED_IFORM_CCMPNB_GPR8i8_GPR8i8_DFV_APX =434 ,
  XED_IFORM_CCMPNB_GPR8i8_IMM8_DFV_APX =435 ,
  XED_IFORM_CCMPNB_GPR8i8_MEMi8_DFV_APX =436 ,
  XED_IFORM_CCMPNB_GPRv_GPRv_DFV_APX =437 ,
  XED_IFORM_CCMPNB_GPRv_IMM8_DFV_APX =438 ,
  XED_IFORM_CCMPNB_GPRv_IMMz_DFV_APX =439 ,
  XED_IFORM_CCMPNB_GPRv_MEMv_DFV_APX =440 ,
  XED_IFORM_CCMPNB_MEMi8_GPR8i8_DFV_APX =441 ,
  XED_IFORM_CCMPNB_MEMi8_IMM8_DFV_APX =442 ,
  XED_IFORM_CCMPNB_MEMv_GPRv_DFV_APX =443 ,
  XED_IFORM_CCMPNB_MEMv_IMM8_DFV_APX =444 ,
  XED_IFORM_CCMPNB_MEMv_IMMz_DFV_APX =445 ,
  XED_IFORM_CCMPNBE_GPR8i8_GPR8i8_DFV_APX =446 ,
  XED_IFORM_CCMPNBE_GPR8i8_IMM8_DFV_APX =447 ,
  XED_IFORM_CCMPNBE_GPR8i8_MEMi8_DFV_APX =448 ,
  XED_IFORM_CCMPNBE_GPRv_GPRv_DFV_APX =449 ,
  XED_IFORM_CCMPNBE_GPRv_IMM8_DFV_APX =450 ,
  XED_IFORM_CCMPNBE_GPRv_IMMz_DFV_APX =451 ,
  XED_IFORM_CCMPNBE_GPRv_MEMv_DFV_APX =452 ,
  XED_IFORM_CCMPNBE_MEMi8_GPR8i8_DFV_APX =453 ,
  XED_IFORM_CCMPNBE_MEMi8_IMM8_DFV_APX =454 ,
  XED_IFORM_CCMPNBE_MEMv_GPRv_DFV_APX =455 ,
  XED_IFORM_CCMPNBE_MEMv_IMM8_DFV_APX =456 ,
  XED_IFORM_CCMPNBE_MEMv_IMMz_DFV_APX =457 ,
  XED_IFORM_CCMPNL_GPR8i8_GPR8i8_DFV_APX =458 ,
  XED_IFORM_CCMPNL_GPR8i8_IMM8_DFV_APX =459 ,
  XED_IFORM_CCMPNL_GPR8i8_MEMi8_DFV_APX =460 ,
  XED_IFORM_CCMPNL_GPRv_GPRv_DFV_APX =461 ,
  XED_IFORM_CCMPNL_GPRv_IMM8_DFV_APX =462 ,
  XED_IFORM_CCMPNL_GPRv_IMMz_DFV_APX =463 ,
  XED_IFORM_CCMPNL_GPRv_MEMv_DFV_APX =464 ,
  XED_IFORM_CCMPNL_MEMi8_GPR8i8_DFV_APX =465 ,
  XED_IFORM_CCMPNL_MEMi8_IMM8_DFV_APX =466 ,
  XED_IFORM_CCMPNL_MEMv_GPRv_DFV_APX =467 ,
  XED_IFORM_CCMPNL_MEMv_IMM8_DFV_APX =468 ,
  XED_IFORM_CCMPNL_MEMv_IMMz_DFV_APX =469 ,
  XED_IFORM_CCMPNLE_GPR8i8_GPR8i8_DFV_APX =470 ,
  XED_IFORM_CCMPNLE_GPR8i8_IMM8_DFV_APX =471 ,
  XED_IFORM_CCMPNLE_GPR8i8_MEMi8_DFV_APX =472 ,
  XED_IFORM_CCMPNLE_GPRv_GPRv_DFV_APX =473 ,
  XED_IFORM_CCMPNLE_GPRv_IMM8_DFV_APX =474 ,
  XED_IFORM_CCMPNLE_GPRv_IMMz_DFV_APX =475 ,
  XED_IFORM_CCMPNLE_GPRv_MEMv_DFV_APX =476 ,
  XED_IFORM_CCMPNLE_MEMi8_GPR8i8_DFV_APX =477 ,
  XED_IFORM_CCMPNLE_MEMi8_IMM8_DFV_APX =478 ,
  XED_IFORM_CCMPNLE_MEMv_GPRv_DFV_APX =479 ,
  XED_IFORM_CCMPNLE_MEMv_IMM8_DFV_APX =480 ,
  XED_IFORM_CCMPNLE_MEMv_IMMz_DFV_APX =481 ,
  XED_IFORM_CCMPNO_GPR8i8_GPR8i8_DFV_APX =482 ,
  XED_IFORM_CCMPNO_GPR8i8_IMM8_DFV_APX =483 ,
  XED_IFORM_CCMPNO_GPR8i8_MEMi8_DFV_APX =484 ,
  XED_IFORM_CCMPNO_GPRv_GPRv_DFV_APX =485 ,
  XED_IFORM_CCMPNO_GPRv_IMM8_DFV_APX =486 ,
  XED_IFORM_CCMPNO_GPRv_IMMz_DFV_APX =487 ,
  XED_IFORM_CCMPNO_GPRv_MEMv_DFV_APX =488 ,
  XED_IFORM_CCMPNO_MEMi8_GPR8i8_DFV_APX =489 ,
  XED_IFORM_CCMPNO_MEMi8_IMM8_DFV_APX =490 ,
  XED_IFORM_CCMPNO_MEMv_GPRv_DFV_APX =491 ,
  XED_IFORM_CCMPNO_MEMv_IMM8_DFV_APX =492 ,
  XED_IFORM_CCMPNO_MEMv_IMMz_DFV_APX =493 ,
  XED_IFORM_CCMPNS_GPR8i8_GPR8i8_DFV_APX =494 ,
  XED_IFORM_CCMPNS_GPR8i8_IMM8_DFV_APX =495 ,
  XED_IFORM_CCMPNS_GPR8i8_MEMi8_DFV_APX =496 ,
  XED_IFORM_CCMPNS_GPRv_GPRv_DFV_APX =497 ,
  XED_IFORM_CCMPNS_GPRv_IMM8_DFV_APX =498 ,
  XED_IFORM_CCMPNS_GPRv_IMMz_DFV_APX =499 ,
  XED_IFORM_CCMPNS_GPRv_MEMv_DFV_APX =500 ,
  XED_IFORM_CCMPNS_MEMi8_GPR8i8_DFV_APX =501 ,
  XED_IFORM_CCMPNS_MEMi8_IMM8_DFV_APX =502 ,
  XED_IFORM_CCMPNS_MEMv_GPRv_DFV_APX =503 ,
  XED_IFORM_CCMPNS_MEMv_IMM8_DFV_APX =504 ,
  XED_IFORM_CCMPNS_MEMv_IMMz_DFV_APX =505 ,
  XED_IFORM_CCMPNZ_GPR8i8_GPR8i8_DFV_APX =506 ,
  XED_IFORM_CCMPNZ_GPR8i8_IMM8_DFV_APX =507 ,
  XED_IFORM_CCMPNZ_GPR8i8_MEMi8_DFV_APX =508 ,
  XED_IFORM_CCMPNZ_GPRv_GPRv_DFV_APX =509 ,
  XED_IFORM_CCMPNZ_GPRv_IMM8_DFV_APX =510 ,
  XED_IFORM_CCMPNZ_GPRv_IMMz_DFV_APX =511 ,
  XED_IFORM_CCMPNZ_GPRv_MEMv_DFV_APX =512 ,
  XED_IFORM_CCMPNZ_MEMi8_GPR8i8_DFV_APX =513 ,
  XED_IFORM_CCMPNZ_MEMi8_IMM8_DFV_APX =514 ,
  XED_IFORM_CCMPNZ_MEMv_GPRv_DFV_APX =515 ,
  XED_IFORM_CCMPNZ_MEMv_IMM8_DFV_APX =516 ,
  XED_IFORM_CCMPNZ_MEMv_IMMz_DFV_APX =517 ,
  XED_IFORM_CCMPO_GPR8i8_GPR8i8_DFV_APX =518 ,
  XED_IFORM_CCMPO_GPR8i8_IMM8_DFV_APX =519 ,
  XED_IFORM_CCMPO_GPR8i8_MEMi8_DFV_APX =520 ,
  XED_IFORM_CCMPO_GPRv_GPRv_DFV_APX =521 ,
  XED_IFORM_CCMPO_GPRv_IMM8_DFV_APX =522 ,
  XED_IFORM_CCMPO_GPRv_IMMz_DFV_APX =523 ,
  XED_IFORM_CCMPO_GPRv_MEMv_DFV_APX =524 ,
  XED_IFORM_CCMPO_MEMi8_GPR8i8_DFV_APX =525 ,
  XED_IFORM_CCMPO_MEMi8_IMM8_DFV_APX =526 ,
  XED_IFORM_CCMPO_MEMv_GPRv_DFV_APX =527 ,
  XED_IFORM_CCMPO_MEMv_IMM8_DFV_APX =528 ,
  XED_IFORM_CCMPO_MEMv_IMMz_DFV_APX =529 ,
  XED_IFORM_CCMPS_GPR8i8_GPR8i8_DFV_APX =530 ,
  XED_IFORM_CCMPS_GPR8i8_IMM8_DFV_APX =531 ,
  XED_IFORM_CCMPS_GPR8i8_MEMi8_DFV_APX =532 ,
  XED_IFORM_CCMPS_GPRv_GPRv_DFV_APX =533 ,
  XED_IFORM_CCMPS_GPRv_IMM8_DFV_APX =534 ,
  XED_IFORM_CCMPS_GPRv_IMMz_DFV_APX =535 ,
  XED_IFORM_CCMPS_GPRv_MEMv_DFV_APX =536 ,
  XED_IFORM_CCMPS_MEMi8_GPR8i8_DFV_APX =537 ,
  XED_IFORM_CCMPS_MEMi8_IMM8_DFV_APX =538 ,
  XED_IFORM_CCMPS_MEMv_GPRv_DFV_APX =539 ,
  XED_IFORM_CCMPS_MEMv_IMM8_DFV_APX =540 ,
  XED_IFORM_CCMPS_MEMv_IMMz_DFV_APX =541 ,
  XED_IFORM_CCMPT_GPR8i8_GPR8i8_DFV_APX =542 ,
  XED_IFORM_CCMPT_GPR8i8_IMM8_DFV_APX =543 ,
  XED_IFORM_CCMPT_GPR8i8_MEMi8_DFV_APX =544 ,
  XED_IFORM_CCMPT_GPRv_GPRv_DFV_APX =545 ,
  XED_IFORM_CCMPT_GPRv_IMM8_DFV_APX =546 ,
  XED_IFORM_CCMPT_GPRv_IMMz_DFV_APX =547 ,
  XED_IFORM_CCMPT_GPRv_MEMv_DFV_APX =548 ,
  XED_IFORM_CCMPT_MEMi8_GPR8i8_DFV_APX =549 ,
  XED_IFORM_CCMPT_MEMi8_IMM8_DFV_APX =550 ,
  XED_IFORM_CCMPT_MEMv_GPRv_DFV_APX =551 ,
  XED_IFORM_CCMPT_MEMv_IMM8_DFV_APX =552 ,
  XED_IFORM_CCMPT_MEMv_IMMz_DFV_APX =553 ,
  XED_IFORM_CCMPZ_GPR8i8_GPR8i8_DFV_APX =554 ,
  XED_IFORM_CCMPZ_GPR8i8_IMM8_DFV_APX =555 ,
  XED_IFORM_CCMPZ_GPR8i8_MEMi8_DFV_APX =556 ,
  XED_IFORM_CCMPZ_GPRv_GPRv_DFV_APX =557 ,
  XED_IFORM_CCMPZ_GPRv_IMM8_DFV_APX =558 ,
  XED_IFORM_CCMPZ_GPRv_IMMz_DFV_APX =559 ,
  XED_IFORM_CCMPZ_GPRv_MEMv_DFV_APX =560 ,
  XED_IFORM_CCMPZ_MEMi8_GPR8i8_DFV_APX =561 ,
  XED_IFORM_CCMPZ_MEMi8_IMM8_DFV_APX =562 ,
  XED_IFORM_CCMPZ_MEMv_GPRv_DFV_APX =563 ,
  XED_IFORM_CCMPZ_MEMv_IMM8_DFV_APX =564 ,
  XED_IFORM_CCMPZ_MEMv_IMMz_DFV_APX =565 ,
  XED_IFORM_CDQ =566 ,
  XED_IFORM_CDQE =567 ,
  XED_IFORM_CFCMOVB_GPRv_GPRv_APX =568 ,
  XED_IFORM_CFCMOVB_GPRv_GPRv_GPRv_APX =569 ,
  XED_IFORM_CFCMOVB_GPRv_GPRv_MEMv_APX =570 ,
  XED_IFORM_CFCMOVB_GPRv_MEMv_APX =571 ,
  XED_IFORM_CFCMOVB_MEMv_GPRv_APX =572 ,
  XED_IFORM_CFCMOVBE_GPRv_GPRv_APX =573 ,
  XED_IFORM_CFCMOVBE_GPRv_GPRv_GPRv_APX =574 ,
  XED_IFORM_CFCMOVBE_GPRv_GPRv_MEMv_APX =575 ,
  XED_IFORM_CFCMOVBE_GPRv_MEMv_APX =576 ,
  XED_IFORM_CFCMOVBE_MEMv_GPRv_APX =577 ,
  XED_IFORM_CFCMOVL_GPRv_GPRv_APX =578 ,
  XED_IFORM_CFCMOVL_GPRv_GPRv_GPRv_APX =579 ,
  XED_IFORM_CFCMOVL_GPRv_GPRv_MEMv_APX =580 ,
  XED_IFORM_CFCMOVL_GPRv_MEMv_APX =581 ,
  XED_IFORM_CFCMOVL_MEMv_GPRv_APX =582 ,
  XED_IFORM_CFCMOVLE_GPRv_GPRv_APX =583 ,
  XED_IFORM_CFCMOVLE_GPRv_GPRv_GPRv_APX =584 ,
  XED_IFORM_CFCMOVLE_GPRv_GPRv_MEMv_APX =585 ,
  XED_IFORM_CFCMOVLE_GPRv_MEMv_APX =586 ,
  XED_IFORM_CFCMOVLE_MEMv_GPRv_APX =587 ,
  XED_IFORM_CFCMOVNB_GPRv_GPRv_APX =588 ,
  XED_IFORM_CFCMOVNB_GPRv_GPRv_GPRv_APX =589 ,
  XED_IFORM_CFCMOVNB_GPRv_GPRv_MEMv_APX =590 ,
  XED_IFORM_CFCMOVNB_GPRv_MEMv_APX =591 ,
  XED_IFORM_CFCMOVNB_MEMv_GPRv_APX =592 ,
  XED_IFORM_CFCMOVNBE_GPRv_GPRv_APX =593 ,
  XED_IFORM_CFCMOVNBE_GPRv_GPRv_GPRv_APX =594 ,
  XED_IFORM_CFCMOVNBE_GPRv_GPRv_MEMv_APX =595 ,
  XED_IFORM_CFCMOVNBE_GPRv_MEMv_APX =596 ,
  XED_IFORM_CFCMOVNBE_MEMv_GPRv_APX =597 ,
  XED_IFORM_CFCMOVNL_GPRv_GPRv_APX =598 ,
  XED_IFORM_CFCMOVNL_GPRv_GPRv_GPRv_APX =599 ,
  XED_IFORM_CFCMOVNL_GPRv_GPRv_MEMv_APX =600 ,
  XED_IFORM_CFCMOVNL_GPRv_MEMv_APX =601 ,
  XED_IFORM_CFCMOVNL_MEMv_GPRv_APX =602 ,
  XED_IFORM_CFCMOVNLE_GPRv_GPRv_APX =603 ,
  XED_IFORM_CFCMOVNLE_GPRv_GPRv_GPRv_APX =604 ,
  XED_IFORM_CFCMOVNLE_GPRv_GPRv_MEMv_APX =605 ,
  XED_IFORM_CFCMOVNLE_GPRv_MEMv_APX =606 ,
  XED_IFORM_CFCMOVNLE_MEMv_GPRv_APX =607 ,
  XED_IFORM_CFCMOVNO_GPRv_GPRv_APX =608 ,
  XED_IFORM_CFCMOVNO_GPRv_GPRv_GPRv_APX =609 ,
  XED_IFORM_CFCMOVNO_GPRv_GPRv_MEMv_APX =610 ,
  XED_IFORM_CFCMOVNO_GPRv_MEMv_APX =611 ,
  XED_IFORM_CFCMOVNO_MEMv_GPRv_APX =612 ,
  XED_IFORM_CFCMOVNP_GPRv_GPRv_APX =613 ,
  XED_IFORM_CFCMOVNP_GPRv_GPRv_GPRv_APX =614 ,
  XED_IFORM_CFCMOVNP_GPRv_GPRv_MEMv_APX =615 ,
  XED_IFORM_CFCMOVNP_GPRv_MEMv_APX =616 ,
  XED_IFORM_CFCMOVNP_MEMv_GPRv_APX =617 ,
  XED_IFORM_CFCMOVNS_GPRv_GPRv_APX =618 ,
  XED_IFORM_CFCMOVNS_GPRv_GPRv_GPRv_APX =619 ,
  XED_IFORM_CFCMOVNS_GPRv_GPRv_MEMv_APX =620 ,
  XED_IFORM_CFCMOVNS_GPRv_MEMv_APX =621 ,
  XED_IFORM_CFCMOVNS_MEMv_GPRv_APX =622 ,
  XED_IFORM_CFCMOVNZ_GPRv_GPRv_APX =623 ,
  XED_IFORM_CFCMOVNZ_GPRv_GPRv_GPRv_APX =624 ,
  XED_IFORM_CFCMOVNZ_GPRv_GPRv_MEMv_APX =625 ,
  XED_IFORM_CFCMOVNZ_GPRv_MEMv_APX =626 ,
  XED_IFORM_CFCMOVNZ_MEMv_GPRv_APX =627 ,
  XED_IFORM_CFCMOVO_GPRv_GPRv_APX =628 ,
  XED_IFORM_CFCMOVO_GPRv_GPRv_GPRv_APX =629 ,
  XED_IFORM_CFCMOVO_GPRv_GPRv_MEMv_APX =630 ,
  XED_IFORM_CFCMOVO_GPRv_MEMv_APX =631 ,
  XED_IFORM_CFCMOVO_MEMv_GPRv_APX =632 ,
  XED_IFORM_CFCMOVP_GPRv_GPRv_APX =633 ,
  XED_IFORM_CFCMOVP_GPRv_GPRv_GPRv_APX =634 ,
  XED_IFORM_CFCMOVP_GPRv_GPRv_MEMv_APX =635 ,
  XED_IFORM_CFCMOVP_GPRv_MEMv_APX =636 ,
  XED_IFORM_CFCMOVP_MEMv_GPRv_APX =637 ,
  XED_IFORM_CFCMOVS_GPRv_GPRv_APX =638 ,
  XED_IFORM_CFCMOVS_GPRv_GPRv_GPRv_APX =639 ,
  XED_IFORM_CFCMOVS_GPRv_GPRv_MEMv_APX =640 ,
  XED_IFORM_CFCMOVS_GPRv_MEMv_APX =641 ,
  XED_IFORM_CFCMOVS_MEMv_GPRv_APX =642 ,
  XED_IFORM_CFCMOVZ_GPRv_GPRv_APX =643 ,
  XED_IFORM_CFCMOVZ_GPRv_GPRv_GPRv_APX =644 ,
  XED_IFORM_CFCMOVZ_GPRv_GPRv_MEMv_APX =645 ,
  XED_IFORM_CFCMOVZ_GPRv_MEMv_APX =646 ,
  XED_IFORM_CFCMOVZ_MEMv_GPRv_APX =647 ,
  XED_IFORM_CLAC =648 ,
  XED_IFORM_CLC =649 ,
  XED_IFORM_CLD =650 ,
  XED_IFORM_CLDEMOTE_MEMu8 =651 ,
  XED_IFORM_CLFLUSH_MEMmprefetch =652 ,
  XED_IFORM_CLFLUSHOPT_MEMmprefetch =653 ,
  XED_IFORM_CLGI =654 ,
  XED_IFORM_CLI =655 ,
  XED_IFORM_CLRSSBSY_MEMu64 =656 ,
  XED_IFORM_CLTS =657 ,
  XED_IFORM_CLUI =658 ,
  XED_IFORM_CLWB_MEMmprefetch =659 ,
  XED_IFORM_CLZERO =660 ,
  XED_IFORM_CMC =661 ,
  XED_IFORM_CMOVB_GPRv_GPRv =662 ,
  XED_IFORM_CMOVB_GPRv_GPRv_GPRv_APX =663 ,
  XED_IFORM_CMOVB_GPRv_GPRv_MEMv_APX =664 ,
  XED_IFORM_CMOVB_GPRv_MEMv =665 ,
  XED_IFORM_CMOVBE_GPRv_GPRv =666 ,
  XED_IFORM_CMOVBE_GPRv_GPRv_GPRv_APX =667 ,
  XED_IFORM_CMOVBE_GPRv_GPRv_MEMv_APX =668 ,
  XED_IFORM_CMOVBE_GPRv_MEMv =669 ,
  XED_IFORM_CMOVL_GPRv_GPRv =670 ,
  XED_IFORM_CMOVL_GPRv_GPRv_GPRv_APX =671 ,
  XED_IFORM_CMOVL_GPRv_GPRv_MEMv_APX =672 ,
  XED_IFORM_CMOVL_GPRv_MEMv =673 ,
  XED_IFORM_CMOVLE_GPRv_GPRv =674 ,
  XED_IFORM_CMOVLE_GPRv_GPRv_GPRv_APX =675 ,
  XED_IFORM_CMOVLE_GPRv_GPRv_MEMv_APX =676 ,
  XED_IFORM_CMOVLE_GPRv_MEMv =677 ,
  XED_IFORM_CMOVNB_GPRv_GPRv =678 ,
  XED_IFORM_CMOVNB_GPRv_GPRv_GPRv_APX =679 ,
  XED_IFORM_CMOVNB_GPRv_GPRv_MEMv_APX =680 ,
  XED_IFORM_CMOVNB_GPRv_MEMv =681 ,
  XED_IFORM_CMOVNBE_GPRv_GPRv =682 ,
  XED_IFORM_CMOVNBE_GPRv_GPRv_GPRv_APX =683 ,
  XED_IFORM_CMOVNBE_GPRv_GPRv_MEMv_APX =684 ,
  XED_IFORM_CMOVNBE_GPRv_MEMv =685 ,
  XED_IFORM_CMOVNL_GPRv_GPRv =686 ,
  XED_IFORM_CMOVNL_GPRv_GPRv_GPRv_APX =687 ,
  XED_IFORM_CMOVNL_GPRv_GPRv_MEMv_APX =688 ,
  XED_IFORM_CMOVNL_GPRv_MEMv =689 ,
  XED_IFORM_CMOVNLE_GPRv_GPRv =690 ,
  XED_IFORM_CMOVNLE_GPRv_GPRv_GPRv_APX =691 ,
  XED_IFORM_CMOVNLE_GPRv_GPRv_MEMv_APX =692 ,
  XED_IFORM_CMOVNLE_GPRv_MEMv =693 ,
  XED_IFORM_CMOVNO_GPRv_GPRv =694 ,
  XED_IFORM_CMOVNO_GPRv_GPRv_GPRv_APX =695 ,
  XED_IFORM_CMOVNO_GPRv_GPRv_MEMv_APX =696 ,
  XED_IFORM_CMOVNO_GPRv_MEMv =697 ,
  XED_IFORM_CMOVNP_GPRv_GPRv =698 ,
  XED_IFORM_CMOVNP_GPRv_GPRv_GPRv_APX =699 ,
  XED_IFORM_CMOVNP_GPRv_GPRv_MEMv_APX =700 ,
  XED_IFORM_CMOVNP_GPRv_MEMv =701 ,
  XED_IFORM_CMOVNS_GPRv_GPRv =702 ,
  XED_IFORM_CMOVNS_GPRv_GPRv_GPRv_APX =703 ,
  XED_IFORM_CMOVNS_GPRv_GPRv_MEMv_APX =704 ,
  XED_IFORM_CMOVNS_GPRv_MEMv =705 ,
  XED_IFORM_CMOVNZ_GPRv_GPRv =706 ,
  XED_IFORM_CMOVNZ_GPRv_GPRv_GPRv_APX =707 ,
  XED_IFORM_CMOVNZ_GPRv_GPRv_MEMv_APX =708 ,
  XED_IFORM_CMOVNZ_GPRv_MEMv =709 ,
  XED_IFORM_CMOVO_GPRv_GPRv =710 ,
  XED_IFORM_CMOVO_GPRv_GPRv_GPRv_APX =711 ,
  XED_IFORM_CMOVO_GPRv_GPRv_MEMv_APX =712 ,
  XED_IFORM_CMOVO_GPRv_MEMv =713 ,
  XED_IFORM_CMOVP_GPRv_GPRv =714 ,
  XED_IFORM_CMOVP_GPRv_GPRv_GPRv_APX =715 ,
  XED_IFORM_CMOVP_GPRv_GPRv_MEMv_APX =716 ,
  XED_IFORM_CMOVP_GPRv_MEMv =717 ,
  XED_IFORM_CMOVS_GPRv_GPRv =718 ,
  XED_IFORM_CMOVS_GPRv_GPRv_GPRv_APX =719 ,
  XED_IFORM_CMOVS_GPRv_GPRv_MEMv_APX =720 ,
  XED_IFORM_CMOVS_GPRv_MEMv =721 ,
  XED_IFORM_CMOVZ_GPRv_GPRv =722 ,
  XED_IFORM_CMOVZ_GPRv_GPRv_GPRv_APX =723 ,
  XED_IFORM_CMOVZ_GPRv_GPRv_MEMv_APX =724 ,
  XED_IFORM_CMOVZ_GPRv_MEMv =725 ,
  XED_IFORM_CMP_AL_IMMb =726 ,
  XED_IFORM_CMP_GPR8_GPR8_38 =727 ,
  XED_IFORM_CMP_GPR8_GPR8_3A =728 ,
  XED_IFORM_CMP_GPR8_IMMb_80r7 =729 ,
  XED_IFORM_CMP_GPR8_IMMb_82r7 =730 ,
  XED_IFORM_CMP_GPR8_MEMb =731 ,
  XED_IFORM_CMP_GPRv_GPRv_39 =732 ,
  XED_IFORM_CMP_GPRv_GPRv_3B =733 ,
  XED_IFORM_CMP_GPRv_IMMb =734 ,
  XED_IFORM_CMP_GPRv_IMMz =735 ,
  XED_IFORM_CMP_GPRv_MEMv =736 ,
  XED_IFORM_CMP_MEMb_GPR8 =737 ,
  XED_IFORM_CMP_MEMb_IMMb_80r7 =738 ,
  XED_IFORM_CMP_MEMb_IMMb_82r7 =739 ,
  XED_IFORM_CMP_MEMv_GPRv =740 ,
  XED_IFORM_CMP_MEMv_IMMb =741 ,
  XED_IFORM_CMP_MEMv_IMMz =742 ,
  XED_IFORM_CMP_OrAX_IMMz =743 ,
  XED_IFORM_CMPBEXADD_MEMu32_GPR32u32_GPR32u32 =744 ,
  XED_IFORM_CMPBEXADD_MEMu32_GPR32u32_GPR32u32_APX =745 ,
  XED_IFORM_CMPBEXADD_MEMu64_GPR64u64_GPR64u64 =746 ,
  XED_IFORM_CMPBEXADD_MEMu64_GPR64u64_GPR64u64_APX =747 ,
  XED_IFORM_CMPBXADD_MEMu32_GPR32u32_GPR32u32 =748 ,
  XED_IFORM_CMPBXADD_MEMu32_GPR32u32_GPR32u32_APX =749 ,
  XED_IFORM_CMPBXADD_MEMu64_GPR64u64_GPR64u64 =750 ,
  XED_IFORM_CMPBXADD_MEMu64_GPR64u64_GPR64u64_APX =751 ,
  XED_IFORM_CMPLEXADD_MEMu32_GPR32u32_GPR32u32 =752 ,
  XED_IFORM_CMPLEXADD_MEMu32_GPR32u32_GPR32u32_APX =753 ,
  XED_IFORM_CMPLEXADD_MEMu64_GPR64u64_GPR64u64 =754 ,
  XED_IFORM_CMPLEXADD_MEMu64_GPR64u64_GPR64u64_APX =755 ,
  XED_IFORM_CMPLXADD_MEMu32_GPR32u32_GPR32u32 =756 ,
  XED_IFORM_CMPLXADD_MEMu32_GPR32u32_GPR32u32_APX =757 ,
  XED_IFORM_CMPLXADD_MEMu64_GPR64u64_GPR64u64 =758 ,
  XED_IFORM_CMPLXADD_MEMu64_GPR64u64_GPR64u64_APX =759 ,
  XED_IFORM_CMPNBEXADD_MEMu32_GPR32u32_GPR32u32 =760 ,
  XED_IFORM_CMPNBEXADD_MEMu32_GPR32u32_GPR32u32_APX =761 ,
  XED_IFORM_CMPNBEXADD_MEMu64_GPR64u64_GPR64u64 =762 ,
  XED_IFORM_CMPNBEXADD_MEMu64_GPR64u64_GPR64u64_APX =763 ,
  XED_IFORM_CMPNBXADD_MEMu32_GPR32u32_GPR32u32 =764 ,
  XED_IFORM_CMPNBXADD_MEMu32_GPR32u32_GPR32u32_APX =765 ,
  XED_IFORM_CMPNBXADD_MEMu64_GPR64u64_GPR64u64 =766 ,
  XED_IFORM_CMPNBXADD_MEMu64_GPR64u64_GPR64u64_APX =767 ,
  XED_IFORM_CMPNLEXADD_MEMu32_GPR32u32_GPR32u32 =768 ,
  XED_IFORM_CMPNLEXADD_MEMu32_GPR32u32_GPR32u32_APX =769 ,
  XED_IFORM_CMPNLEXADD_MEMu64_GPR64u64_GPR64u64 =770 ,
  XED_IFORM_CMPNLEXADD_MEMu64_GPR64u64_GPR64u64_APX =771 ,
  XED_IFORM_CMPNLXADD_MEMu32_GPR32u32_GPR32u32 =772 ,
  XED_IFORM_CMPNLXADD_MEMu32_GPR32u32_GPR32u32_APX =773 ,
  XED_IFORM_CMPNLXADD_MEMu64_GPR64u64_GPR64u64 =774 ,
  XED_IFORM_CMPNLXADD_MEMu64_GPR64u64_GPR64u64_APX =775 ,
  XED_IFORM_CMPNOXADD_MEMu32_GPR32u32_GPR32u32 =776 ,
  XED_IFORM_CMPNOXADD_MEMu32_GPR32u32_GPR32u32_APX =777 ,
  XED_IFORM_CMPNOXADD_MEMu64_GPR64u64_GPR64u64 =778 ,
  XED_IFORM_CMPNOXADD_MEMu64_GPR64u64_GPR64u64_APX =779 ,
  XED_IFORM_CMPNPXADD_MEMu32_GPR32u32_GPR32u32 =780 ,
  XED_IFORM_CMPNPXADD_MEMu32_GPR32u32_GPR32u32_APX =781 ,
  XED_IFORM_CMPNPXADD_MEMu64_GPR64u64_GPR64u64 =782 ,
  XED_IFORM_CMPNPXADD_MEMu64_GPR64u64_GPR64u64_APX =783 ,
  XED_IFORM_CMPNSXADD_MEMu32_GPR32u32_GPR32u32 =784 ,
  XED_IFORM_CMPNSXADD_MEMu32_GPR32u32_GPR32u32_APX =785 ,
  XED_IFORM_CMPNSXADD_MEMu64_GPR64u64_GPR64u64 =786 ,
  XED_IFORM_CMPNSXADD_MEMu64_GPR64u64_GPR64u64_APX =787 ,
  XED_IFORM_CMPNZXADD_MEMu32_GPR32u32_GPR32u32 =788 ,
  XED_IFORM_CMPNZXADD_MEMu32_GPR32u32_GPR32u32_APX =789 ,
  XED_IFORM_CMPNZXADD_MEMu64_GPR64u64_GPR64u64 =790 ,
  XED_IFORM_CMPNZXADD_MEMu64_GPR64u64_GPR64u64_APX =791 ,
  XED_IFORM_CMPOXADD_MEMu32_GPR32u32_GPR32u32 =792 ,
  XED_IFORM_CMPOXADD_MEMu32_GPR32u32_GPR32u32_APX =793 ,
  XED_IFORM_CMPOXADD_MEMu64_GPR64u64_GPR64u64 =794 ,
  XED_IFORM_CMPOXADD_MEMu64_GPR64u64_GPR64u64_APX =795 ,
  XED_IFORM_CMPPD_XMMpd_MEMpd_IMMb =796 ,
  XED_IFORM_CMPPD_XMMpd_XMMpd_IMMb =797 ,
  XED_IFORM_CMPPS_XMMps_MEMps_IMMb =798 ,
  XED_IFORM_CMPPS_XMMps_XMMps_IMMb =799 ,
  XED_IFORM_CMPPXADD_MEMu32_GPR32u32_GPR32u32 =800 ,
  XED_IFORM_CMPPXADD_MEMu32_GPR32u32_GPR32u32_APX =801 ,
  XED_IFORM_CMPPXADD_MEMu64_GPR64u64_GPR64u64 =802 ,
  XED_IFORM_CMPPXADD_MEMu64_GPR64u64_GPR64u64_APX =803 ,
  XED_IFORM_CMPSB =804 ,
  XED_IFORM_CMPSD =805 ,
  XED_IFORM_CMPSD_XMM_XMMsd_MEMsd_IMMb =806 ,
  XED_IFORM_CMPSD_XMM_XMMsd_XMMsd_IMMb =807 ,
  XED_IFORM_CMPSQ =808 ,
  XED_IFORM_CMPSS_XMMss_MEMss_IMMb =809 ,
  XED_IFORM_CMPSS_XMMss_XMMss_IMMb =810 ,
  XED_IFORM_CMPSW =811 ,
  XED_IFORM_CMPSXADD_MEMu32_GPR32u32_GPR32u32 =812 ,
  XED_IFORM_CMPSXADD_MEMu32_GPR32u32_GPR32u32_APX =813 ,
  XED_IFORM_CMPSXADD_MEMu64_GPR64u64_GPR64u64 =814 ,
  XED_IFORM_CMPSXADD_MEMu64_GPR64u64_GPR64u64_APX =815 ,
  XED_IFORM_CMPXCHG_GPR8_GPR8 =816 ,
  XED_IFORM_CMPXCHG_GPRv_GPRv =817 ,
  XED_IFORM_CMPXCHG_MEMb_GPR8 =818 ,
  XED_IFORM_CMPXCHG_MEMv_GPRv =819 ,
  XED_IFORM_CMPXCHG16B_MEMdq =820 ,
  XED_IFORM_CMPXCHG16B_LOCK_MEMdq =821 ,
  XED_IFORM_CMPXCHG8B_MEMq =822 ,
  XED_IFORM_CMPXCHG8B_LOCK_MEMq =823 ,
  XED_IFORM_CMPXCHG_LOCK_MEMb_GPR8 =824 ,
  XED_IFORM_CMPXCHG_LOCK_MEMv_GPRv =825 ,
  XED_IFORM_CMPZXADD_MEMu32_GPR32u32_GPR32u32 =826 ,
  XED_IFORM_CMPZXADD_MEMu32_GPR32u32_GPR32u32_APX =827 ,
  XED_IFORM_CMPZXADD_MEMu64_GPR64u64_GPR64u64 =828 ,
  XED_IFORM_CMPZXADD_MEMu64_GPR64u64_GPR64u64_APX =829 ,
  XED_IFORM_COMISD_XMMsd_MEMsd =830 ,
  XED_IFORM_COMISD_XMMsd_XMMsd =831 ,
  XED_IFORM_COMISS_XMMss_MEMss =832 ,
  XED_IFORM_COMISS_XMMss_XMMss =833 ,
  XED_IFORM_CPUID =834 ,
  XED_IFORM_CQO =835 ,
  XED_IFORM_CRC32_GPRy_GPR8i8_APX =836 ,
  XED_IFORM_CRC32_GPRy_GPRv_APX =837 ,
  XED_IFORM_CRC32_GPRy_MEMi8_APX =838 ,
  XED_IFORM_CRC32_GPRy_MEMv_APX =839 ,
  XED_IFORM_CRC32_GPRyy_GPR8b =840 ,
  XED_IFORM_CRC32_GPRyy_GPRv =841 ,
  XED_IFORM_CRC32_GPRyy_MEMb =842 ,
  XED_IFORM_CRC32_GPRyy_MEMv =843 ,
  XED_IFORM_CTESTB_GPR8i8_GPR8i8_DFV_APX =844 ,
  XED_IFORM_CTESTB_GPR8i8_IMM8_DFV_APX =845 ,
  XED_IFORM_CTESTB_GPRv_GPRv_DFV_APX =846 ,
  XED_IFORM_CTESTB_GPRv_IMMz_DFV_APX =847 ,
  XED_IFORM_CTESTB_MEMi8_GPR8i8_DFV_APX =848 ,
  XED_IFORM_CTESTB_MEMi8_IMM8_DFV_APX =849 ,
  XED_IFORM_CTESTB_MEMv_GPRv_DFV_APX =850 ,
  XED_IFORM_CTESTB_MEMv_IMMz_DFV_APX =851 ,
  XED_IFORM_CTESTBE_GPR8i8_GPR8i8_DFV_APX =852 ,
  XED_IFORM_CTESTBE_GPR8i8_IMM8_DFV_APX =853 ,
  XED_IFORM_CTESTBE_GPRv_GPRv_DFV_APX =854 ,
  XED_IFORM_CTESTBE_GPRv_IMMz_DFV_APX =855 ,
  XED_IFORM_CTESTBE_MEMi8_GPR8i8_DFV_APX =856 ,
  XED_IFORM_CTESTBE_MEMi8_IMM8_DFV_APX =857 ,
  XED_IFORM_CTESTBE_MEMv_GPRv_DFV_APX =858 ,
  XED_IFORM_CTESTBE_MEMv_IMMz_DFV_APX =859 ,
  XED_IFORM_CTESTF_GPR8i8_GPR8i8_DFV_APX =860 ,
  XED_IFORM_CTESTF_GPR8i8_IMM8_DFV_APX =861 ,
  XED_IFORM_CTESTF_GPRv_GPRv_DFV_APX =862 ,
  XED_IFORM_CTESTF_GPRv_IMMz_DFV_APX =863 ,
  XED_IFORM_CTESTF_MEMi8_GPR8i8_DFV_APX =864 ,
  XED_IFORM_CTESTF_MEMi8_IMM8_DFV_APX =865 ,
  XED_IFORM_CTESTF_MEMv_GPRv_DFV_APX =866 ,
  XED_IFORM_CTESTF_MEMv_IMMz_DFV_APX =867 ,
  XED_IFORM_CTESTL_GPR8i8_GPR8i8_DFV_APX =868 ,
  XED_IFORM_CTESTL_GPR8i8_IMM8_DFV_APX =869 ,
  XED_IFORM_CTESTL_GPRv_GPRv_DFV_APX =870 ,
  XED_IFORM_CTESTL_GPRv_IMMz_DFV_APX =871 ,
  XED_IFORM_CTESTL_MEMi8_GPR8i8_DFV_APX =872 ,
  XED_IFORM_CTESTL_MEMi8_IMM8_DFV_APX =873 ,
  XED_IFORM_CTESTL_MEMv_GPRv_DFV_APX =874 ,
  XED_IFORM_CTESTL_MEMv_IMMz_DFV_APX =875 ,
  XED_IFORM_CTESTLE_GPR8i8_GPR8i8_DFV_APX =876 ,
  XED_IFORM_CTESTLE_GPR8i8_IMM8_DFV_APX =877 ,
  XED_IFORM_CTESTLE_GPRv_GPRv_DFV_APX =878 ,
  XED_IFORM_CTESTLE_GPRv_IMMz_DFV_APX =879 ,
  XED_IFORM_CTESTLE_MEMi8_GPR8i8_DFV_APX =880 ,
  XED_IFORM_CTESTLE_MEMi8_IMM8_DFV_APX =881 ,
  XED_IFORM_CTESTLE_MEMv_GPRv_DFV_APX =882 ,
  XED_IFORM_CTESTLE_MEMv_IMMz_DFV_APX =883 ,
  XED_IFORM_CTESTNB_GPR8i8_GPR8i8_DFV_APX =884 ,
  XED_IFORM_CTESTNB_GPR8i8_IMM8_DFV_APX =885 ,
  XED_IFORM_CTESTNB_GPRv_GPRv_DFV_APX =886 ,
  XED_IFORM_CTESTNB_GPRv_IMMz_DFV_APX =887 ,
  XED_IFORM_CTESTNB_MEMi8_GPR8i8_DFV_APX =888 ,
  XED_IFORM_CTESTNB_MEMi8_IMM8_DFV_APX =889 ,
  XED_IFORM_CTESTNB_MEMv_GPRv_DFV_APX =890 ,
  XED_IFORM_CTESTNB_MEMv_IMMz_DFV_APX =891 ,
  XED_IFORM_CTESTNBE_GPR8i8_GPR8i8_DFV_APX =892 ,
  XED_IFORM_CTESTNBE_GPR8i8_IMM8_DFV_APX =893 ,
  XED_IFORM_CTESTNBE_GPRv_GPRv_DFV_APX =894 ,
  XED_IFORM_CTESTNBE_GPRv_IMMz_DFV_APX =895 ,
  XED_IFORM_CTESTNBE_MEMi8_GPR8i8_DFV_APX =896 ,
  XED_IFORM_CTESTNBE_MEMi8_IMM8_DFV_APX =897 ,
  XED_IFORM_CTESTNBE_MEMv_GPRv_DFV_APX =898 ,
  XED_IFORM_CTESTNBE_MEMv_IMMz_DFV_APX =899 ,
  XED_IFORM_CTESTNL_GPR8i8_GPR8i8_DFV_APX =900 ,
  XED_IFORM_CTESTNL_GPR8i8_IMM8_DFV_APX =901 ,
  XED_IFORM_CTESTNL_GPRv_GPRv_DFV_APX =902 ,
  XED_IFORM_CTESTNL_GPRv_IMMz_DFV_APX =903 ,
  XED_IFORM_CTESTNL_MEMi8_GPR8i8_DFV_APX =904 ,
  XED_IFORM_CTESTNL_MEMi8_IMM8_DFV_APX =905 ,
  XED_IFORM_CTESTNL_MEMv_GPRv_DFV_APX =906 ,
  XED_IFORM_CTESTNL_MEMv_IMMz_DFV_APX =907 ,
  XED_IFORM_CTESTNLE_GPR8i8_GPR8i8_DFV_APX =908 ,
  XED_IFORM_CTESTNLE_GPR8i8_IMM8_DFV_APX =909 ,
  XED_IFORM_CTESTNLE_GPRv_GPRv_DFV_APX =910 ,
  XED_IFORM_CTESTNLE_GPRv_IMMz_DFV_APX =911 ,
  XED_IFORM_CTESTNLE_MEMi8_GPR8i8_DFV_APX =912 ,
  XED_IFORM_CTESTNLE_MEMi8_IMM8_DFV_APX =913 ,
  XED_IFORM_CTESTNLE_MEMv_GPRv_DFV_APX =914 ,
  XED_IFORM_CTESTNLE_MEMv_IMMz_DFV_APX =915 ,
  XED_IFORM_CTESTNO_GPR8i8_GPR8i8_DFV_APX =916 ,
  XED_IFORM_CTESTNO_GPR8i8_IMM8_DFV_APX =917 ,
  XED_IFORM_CTESTNO_GPRv_GPRv_DFV_APX =918 ,
  XED_IFORM_CTESTNO_GPRv_IMMz_DFV_APX =919 ,
  XED_IFORM_CTESTNO_MEMi8_GPR8i8_DFV_APX =920 ,
  XED_IFORM_CTESTNO_MEMi8_IMM8_DFV_APX =921 ,
  XED_IFORM_CTESTNO_MEMv_GPRv_DFV_APX =922 ,
  XED_IFORM_CTESTNO_MEMv_IMMz_DFV_APX =923 ,
  XED_IFORM_CTESTNS_GPR8i8_GPR8i8_DFV_APX =924 ,
  XED_IFORM_CTESTNS_GPR8i8_IMM8_DFV_APX =925 ,
  XED_IFORM_CTESTNS_GPRv_GPRv_DFV_APX =926 ,
  XED_IFORM_CTESTNS_GPRv_IMMz_DFV_APX =927 ,
  XED_IFORM_CTESTNS_MEMi8_GPR8i8_DFV_APX =928 ,
  XED_IFORM_CTESTNS_MEMi8_IMM8_DFV_APX =929 ,
  XED_IFORM_CTESTNS_MEMv_GPRv_DFV_APX =930 ,
  XED_IFORM_CTESTNS_MEMv_IMMz_DFV_APX =931 ,
  XED_IFORM_CTESTNZ_GPR8i8_GPR8i8_DFV_APX =932 ,
  XED_IFORM_CTESTNZ_GPR8i8_IMM8_DFV_APX =933 ,
  XED_IFORM_CTESTNZ_GPRv_GPRv_DFV_APX =934 ,
  XED_IFORM_CTESTNZ_GPRv_IMMz_DFV_APX =935 ,
  XED_IFORM_CTESTNZ_MEMi8_GPR8i8_DFV_APX =936 ,
  XED_IFORM_CTESTNZ_MEMi8_IMM8_DFV_APX =937 ,
  XED_IFORM_CTESTNZ_MEMv_GPRv_DFV_APX =938 ,
  XED_IFORM_CTESTNZ_MEMv_IMMz_DFV_APX =939 ,
  XED_IFORM_CTESTO_GPR8i8_GPR8i8_DFV_APX =940 ,
  XED_IFORM_CTESTO_GPR8i8_IMM8_DFV_APX =941 ,
  XED_IFORM_CTESTO_GPRv_GPRv_DFV_APX =942 ,
  XED_IFORM_CTESTO_GPRv_IMMz_DFV_APX =943 ,
  XED_IFORM_CTESTO_MEMi8_GPR8i8_DFV_APX =944 ,
  XED_IFORM_CTESTO_MEMi8_IMM8_DFV_APX =945 ,
  XED_IFORM_CTESTO_MEMv_GPRv_DFV_APX =946 ,
  XED_IFORM_CTESTO_MEMv_IMMz_DFV_APX =947 ,
  XED_IFORM_CTESTS_GPR8i8_GPR8i8_DFV_APX =948 ,
  XED_IFORM_CTESTS_GPR8i8_IMM8_DFV_APX =949 ,
  XED_IFORM_CTESTS_GPRv_GPRv_DFV_APX =950 ,
  XED_IFORM_CTESTS_GPRv_IMMz_DFV_APX =951 ,
  XED_IFORM_CTESTS_MEMi8_GPR8i8_DFV_APX =952 ,
  XED_IFORM_CTESTS_MEMi8_IMM8_DFV_APX =953 ,
  XED_IFORM_CTESTS_MEMv_GPRv_DFV_APX =954 ,
  XED_IFORM_CTESTS_MEMv_IMMz_DFV_APX =955 ,
  XED_IFORM_CTESTT_GPR8i8_GPR8i8_DFV_APX =956 ,
  XED_IFORM_CTESTT_GPR8i8_IMM8_DFV_APX =957 ,
  XED_IFORM_CTESTT_GPRv_GPRv_DFV_APX =958 ,
  XED_IFORM_CTESTT_GPRv_IMMz_DFV_APX =959 ,
  XED_IFORM_CTESTT_MEMi8_GPR8i8_DFV_APX =960 ,
  XED_IFORM_CTESTT_MEMi8_IMM8_DFV_APX =961 ,
  XED_IFORM_CTESTT_MEMv_GPRv_DFV_APX =962 ,
  XED_IFORM_CTESTT_MEMv_IMMz_DFV_APX =963 ,
  XED_IFORM_CTESTZ_GPR8i8_GPR8i8_DFV_APX =964 ,
  XED_IFORM_CTESTZ_GPR8i8_IMM8_DFV_APX =965 ,
  XED_IFORM_CTESTZ_GPRv_GPRv_DFV_APX =966 ,
  XED_IFORM_CTESTZ_GPRv_IMMz_DFV_APX =967 ,
  XED_IFORM_CTESTZ_MEMi8_GPR8i8_DFV_APX =968 ,
  XED_IFORM_CTESTZ_MEMi8_IMM8_DFV_APX =969 ,
  XED_IFORM_CTESTZ_MEMv_GPRv_DFV_APX =970 ,
  XED_IFORM_CTESTZ_MEMv_IMMz_DFV_APX =971 ,
  XED_IFORM_CVTDQ2PD_XMMpd_MEMq =972 ,
  XED_IFORM_CVTDQ2PD_XMMpd_XMMq =973 ,
  XED_IFORM_CVTDQ2PS_XMMps_MEMdq =974 ,
  XED_IFORM_CVTDQ2PS_XMMps_XMMdq =975 ,
  XED_IFORM_CVTPD2DQ_XMMdq_MEMpd =976 ,
  XED_IFORM_CVTPD2DQ_XMMdq_XMMpd =977 ,
  XED_IFORM_CVTPD2PI_MMXq_MEMpd =978 ,
  XED_IFORM_CVTPD2PI_MMXq_XMMpd =979 ,
  XED_IFORM_CVTPD2PS_XMMps_MEMpd =980 ,
  XED_IFORM_CVTPD2PS_XMMps_XMMpd =981 ,
  XED_IFORM_CVTPI2PD_XMMpd_MEMq =982 ,
  XED_IFORM_CVTPI2PD_XMMpd_MMXq =983 ,
  XED_IFORM_CVTPI2PS_XMMq_MEMq =984 ,
  XED_IFORM_CVTPI2PS_XMMq_MMXq =985 ,
  XED_IFORM_CVTPS2DQ_XMMdq_MEMps =986 ,
  XED_IFORM_CVTPS2DQ_XMMdq_XMMps =987 ,
  XED_IFORM_CVTPS2PD_XMMpd_MEMq =988 ,
  XED_IFORM_CVTPS2PD_XMMpd_XMMq =989 ,
  XED_IFORM_CVTPS2PI_MMXq_MEMq =990 ,
  XED_IFORM_CVTPS2PI_MMXq_XMMq =991 ,
  XED_IFORM_CVTSD2SI_GPR32d_MEMsd =992 ,
  XED_IFORM_CVTSD2SI_GPR32d_XMMsd =993 ,
  XED_IFORM_CVTSD2SI_GPR64q_MEMsd =994 ,
  XED_IFORM_CVTSD2SI_GPR64q_XMMsd =995 ,
  XED_IFORM_CVTSD2SS_XMMss_MEMsd =996 ,
  XED_IFORM_CVTSD2SS_XMMss_XMMsd =997 ,
  XED_IFORM_CVTSI2SD_XMMsd_GPR32d =998 ,
  XED_IFORM_CVTSI2SD_XMMsd_GPR64q =999 ,
  XED_IFORM_CVTSI2SD_XMMsd_MEMd =1000 ,
  XED_IFORM_CVTSI2SD_XMMsd_MEMq =1001 ,
  XED_IFORM_CVTSI2SS_XMMss_GPR32d =1002 ,
  XED_IFORM_CVTSI2SS_XMMss_GPR64q =1003 ,
  XED_IFORM_CVTSI2SS_XMMss_MEMd =1004 ,
  XED_IFORM_CVTSI2SS_XMMss_MEMq =1005 ,
  XED_IFORM_CVTSS2SD_XMMsd_MEMss =1006 ,
  XED_IFORM_CVTSS2SD_XMMsd_XMMss =1007 ,
  XED_IFORM_CVTSS2SI_GPR32d_MEMss =1008 ,
  XED_IFORM_CVTSS2SI_GPR32d_XMMss =1009 ,
  XED_IFORM_CVTSS2SI_GPR64q_MEMss =1010 ,
  XED_IFORM_CVTSS2SI_GPR64q_XMMss =1011 ,
  XED_IFORM_CVTTPD2DQ_XMMdq_MEMpd =1012 ,
  XED_IFORM_CVTTPD2DQ_XMMdq_XMMpd =1013 ,
  XED_IFORM_CVTTPD2PI_MMXq_MEMpd =1014 ,
  XED_IFORM_CVTTPD2PI_MMXq_XMMpd =1015 ,
  XED_IFORM_CVTTPS2DQ_XMMdq_MEMps =1016 ,
  XED_IFORM_CVTTPS2DQ_XMMdq_XMMps =1017 ,
  XED_IFORM_CVTTPS2PI_MMXq_MEMq =1018 ,
  XED_IFORM_CVTTPS2PI_MMXq_XMMq =1019 ,
  XED_IFORM_CVTTSD2SI_GPR32d_MEMsd =1020 ,
  XED_IFORM_CVTTSD2SI_GPR32d_XMMsd =1021 ,
  XED_IFORM_CVTTSD2SI_GPR64q_MEMsd =1022 ,
  XED_IFORM_CVTTSD2SI_GPR64q_XMMsd =1023 ,
  XED_IFORM_CVTTSS2SI_GPR32d_MEMss =1024 ,
  XED_IFORM_CVTTSS2SI_GPR32d_XMMss =1025 ,
  XED_IFORM_CVTTSS2SI_GPR64q_MEMss =1026 ,
  XED_IFORM_CVTTSS2SI_GPR64q_XMMss =1027 ,
  XED_IFORM_CWD =1028 ,
  XED_IFORM_CWDE =1029 ,
  XED_IFORM_DAA =1030 ,
  XED_IFORM_DAS =1031 ,
  XED_IFORM_DEC_GPR8 =1032 ,
  XED_IFORM_DEC_GPR8i8_APX =1033 ,
  XED_IFORM_DEC_GPR8i8_GPR8i8_APX =1034 ,
  XED_IFORM_DEC_GPR8i8_MEMi8_APX =1035 ,
  XED_IFORM_DEC_GPRv_48 =1036 ,
  XED_IFORM_DEC_GPRv_APX =1037 ,
  XED_IFORM_DEC_GPRv_FFr1 =1038 ,
  XED_IFORM_DEC_GPRv_GPRv_APX =1039 ,
  XED_IFORM_DEC_GPRv_MEMv_APX =1040 ,
  XED_IFORM_DEC_MEMb =1041 ,
  XED_IFORM_DEC_MEMi8_APX =1042 ,
  XED_IFORM_DEC_MEMv =1043 ,
  XED_IFORM_DEC_MEMv_APX =1044 ,
  XED_IFORM_DEC_LOCK_MEMb =1045 ,
  XED_IFORM_DEC_LOCK_MEMv =1046 ,
  XED_IFORM_DIV_GPR8 =1047 ,
  XED_IFORM_DIV_GPR8i8_APX =1048 ,
  XED_IFORM_DIV_GPRv =1049 ,
  XED_IFORM_DIV_GPRv_APX =1050 ,
  XED_IFORM_DIV_MEMb =1051 ,
  XED_IFORM_DIV_MEMi8_APX =1052 ,
  XED_IFORM_DIV_MEMv =1053 ,
  XED_IFORM_DIV_MEMv_APX =1054 ,
  XED_IFORM_DIVPD_XMMpd_MEMpd =1055 ,
  XED_IFORM_DIVPD_XMMpd_XMMpd =1056 ,
  XED_IFORM_DIVPS_XMMps_MEMps =1057 ,
  XED_IFORM_DIVPS_XMMps_XMMps =1058 ,
  XED_IFORM_DIVSD_XMMsd_MEMsd =1059 ,
  XED_IFORM_DIVSD_XMMsd_XMMsd =1060 ,
  XED_IFORM_DIVSS_XMMss_MEMss =1061 ,
  XED_IFORM_DIVSS_XMMss_XMMss =1062 ,
  XED_IFORM_DPPD_XMMdq_MEMdq_IMMb =1063 ,
  XED_IFORM_DPPD_XMMdq_XMMdq_IMMb =1064 ,
  XED_IFORM_DPPS_XMMdq_MEMdq_IMMb =1065 ,
  XED_IFORM_DPPS_XMMdq_XMMdq_IMMb =1066 ,
  XED_IFORM_EMMS =1067 ,
  XED_IFORM_ENCLS =1068 ,
  XED_IFORM_ENCLU =1069 ,
  XED_IFORM_ENCLV =1070 ,
  XED_IFORM_ENCODEKEY128_GPR32u8_GPR32u8 =1071 ,
  XED_IFORM_ENCODEKEY256_GPR32u8_GPR32u8 =1072 ,
  XED_IFORM_ENDBR32 =1073 ,
  XED_IFORM_ENDBR64 =1074 ,
  XED_IFORM_ENQCMD_GPRa_MEMu32 =1075 ,
  XED_IFORM_ENQCMD_GPRav_MEMu32_APX =1076 ,
  XED_IFORM_ENQCMDS_GPRa_MEMu32 =1077 ,
  XED_IFORM_ENQCMDS_GPRav_MEMu32_APX =1078 ,
  XED_IFORM_ENTER_IMMw_IMMb =1079 ,
  XED_IFORM_ERETS =1080 ,
  XED_IFORM_ERETU =1081 ,
  XED_IFORM_EXTRACTPS_GPR32d_XMMdq_IMMb =1082 ,
  XED_IFORM_EXTRACTPS_MEMd_XMMps_IMMb =1083 ,
  XED_IFORM_EXTRQ_XMMq_IMMb_IMMb =1084 ,
  XED_IFORM_EXTRQ_XMMq_XMMdq =1085 ,
  XED_IFORM_F2XM1 =1086 ,
  XED_IFORM_FABS =1087 ,
  XED_IFORM_FADD_MEMm64real =1088 ,
  XED_IFORM_FADD_MEMmem32real =1089 ,
  XED_IFORM_FADD_ST0_X87 =1090 ,
  XED_IFORM_FADD_X87_ST0 =1091 ,
  XED_IFORM_FADDP_X87_ST0 =1092 ,
  XED_IFORM_FBLD_ST0_MEMmem80dec =1093 ,
  XED_IFORM_FBSTP_MEMmem80dec_ST0 =1094 ,
  XED_IFORM_FCHS =1095 ,
  XED_IFORM_FCMOVB_ST0_X87 =1096 ,
  XED_IFORM_FCMOVBE_ST0_X87 =1097 ,
  XED_IFORM_FCMOVE_ST0_X87 =1098 ,
  XED_IFORM_FCMOVNB_ST0_X87 =1099 ,
  XED_IFORM_FCMOVNBE_ST0_X87 =1100 ,
  XED_IFORM_FCMOVNE_ST0_X87 =1101 ,
  XED_IFORM_FCMOVNU_ST0_X87 =1102 ,
  XED_IFORM_FCMOVU_ST0_X87 =1103 ,
  XED_IFORM_FCOM_ST0_MEMm64real =1104 ,
  XED_IFORM_FCOM_ST0_MEMmem32real =1105 ,
  XED_IFORM_FCOM_ST0_X87 =1106 ,
  XED_IFORM_FCOM_ST0_X87_DCD0 =1107 ,
  XED_IFORM_FCOMI_ST0_X87 =1108 ,
  XED_IFORM_FCOMIP_ST0_X87 =1109 ,
  XED_IFORM_FCOMP_ST0_MEMm64real =1110 ,
  XED_IFORM_FCOMP_ST0_MEMmem32real =1111 ,
  XED_IFORM_FCOMP_ST0_X87 =1112 ,
  XED_IFORM_FCOMP_ST0_X87_DCD1 =1113 ,
  XED_IFORM_FCOMP_ST0_X87_DED0 =1114 ,
  XED_IFORM_FCOMPP =1115 ,
  XED_IFORM_FCOS =1116 ,
  XED_IFORM_FDECSTP =1117 ,
  XED_IFORM_FDISI8087_NOP =1118 ,
  XED_IFORM_FDIV_ST0_MEMm64real =1119 ,
  XED_IFORM_FDIV_ST0_MEMmem32real =1120 ,
  XED_IFORM_FDIV_ST0_X87 =1121 ,
  XED_IFORM_FDIV_X87_ST0 =1122 ,
  XED_IFORM_FDIVP_X87_ST0 =1123 ,
  XED_IFORM_FDIVR_ST0_MEMm64real =1124 ,
  XED_IFORM_FDIVR_ST0_MEMmem32real =1125 ,
  XED_IFORM_FDIVR_ST0_X87 =1126 ,
  XED_IFORM_FDIVR_X87_ST0 =1127 ,
  XED_IFORM_FDIVRP_X87_ST0 =1128 ,
  XED_IFORM_FEMMS =1129 ,
  XED_IFORM_FENI8087_NOP =1130 ,
  XED_IFORM_FFREE_X87 =1131 ,
  XED_IFORM_FFREEP_X87 =1132 ,
  XED_IFORM_FIADD_ST0_MEMmem16int =1133 ,
  XED_IFORM_FIADD_ST0_MEMmem32int =1134 ,
  XED_IFORM_FICOM_ST0_MEMmem16int =1135 ,
  XED_IFORM_FICOM_ST0_MEMmem32int =1136 ,
  XED_IFORM_FICOMP_ST0_MEMmem16int =1137 ,
  XED_IFORM_FICOMP_ST0_MEMmem32int =1138 ,
  XED_IFORM_FIDIV_ST0_MEMmem16int =1139 ,
  XED_IFORM_FIDIV_ST0_MEMmem32int =1140 ,
  XED_IFORM_FIDIVR_ST0_MEMmem16int =1141 ,
  XED_IFORM_FIDIVR_ST0_MEMmem32int =1142 ,
  XED_IFORM_FILD_ST0_MEMm64int =1143 ,
  XED_IFORM_FILD_ST0_MEMmem16int =1144 ,
  XED_IFORM_FILD_ST0_MEMmem32int =1145 ,
  XED_IFORM_FIMUL_ST0_MEMmem16int =1146 ,
  XED_IFORM_FIMUL_ST0_MEMmem32int =1147 ,
  XED_IFORM_FINCSTP =1148 ,
  XED_IFORM_FIST_MEMmem16int_ST0 =1149 ,
  XED_IFORM_FIST_MEMmem32int_ST0 =1150 ,
  XED_IFORM_FISTP_MEMm64int_ST0 =1151 ,
  XED_IFORM_FISTP_MEMmem16int_ST0 =1152 ,
  XED_IFORM_FISTP_MEMmem32int_ST0 =1153 ,
  XED_IFORM_FISTTP_MEMm64int_ST0 =1154 ,
  XED_IFORM_FISTTP_MEMmem16int_ST0 =1155 ,
  XED_IFORM_FISTTP_MEMmem32int_ST0 =1156 ,
  XED_IFORM_FISUB_ST0_MEMmem16int =1157 ,
  XED_IFORM_FISUB_ST0_MEMmem32int =1158 ,
  XED_IFORM_FISUBR_ST0_MEMmem16int =1159 ,
  XED_IFORM_FISUBR_ST0_MEMmem32int =1160 ,
  XED_IFORM_FLD_ST0_MEMm64real =1161 ,
  XED_IFORM_FLD_ST0_MEMmem32real =1162 ,
  XED_IFORM_FLD_ST0_MEMmem80real =1163 ,
  XED_IFORM_FLD_ST0_X87 =1164 ,
  XED_IFORM_FLD1 =1165 ,
  XED_IFORM_FLDCW_MEMmem16 =1166 ,
  XED_IFORM_FLDENV_MEMmem14 =1167 ,
  XED_IFORM_FLDENV_MEMmem28 =1168 ,
  XED_IFORM_FLDL2E =1169 ,
  XED_IFORM_FLDL2T =1170 ,
  XED_IFORM_FLDLG2 =1171 ,
  XED_IFORM_FLDLN2 =1172 ,
  XED_IFORM_FLDPI =1173 ,
  XED_IFORM_FLDZ =1174 ,
  XED_IFORM_FMUL_ST0_MEMm64real =1175 ,
  XED_IFORM_FMUL_ST0_MEMmem32real =1176 ,
  XED_IFORM_FMUL_ST0_X87 =1177 ,
  XED_IFORM_FMUL_X87_ST0 =1178 ,
  XED_IFORM_FMULP_X87_ST0 =1179 ,
  XED_IFORM_FNCLEX =1180 ,
  XED_IFORM_FNINIT =1181 ,
  XED_IFORM_FNOP =1182 ,
  XED_IFORM_FNSAVE_MEMmem108 =1183 ,
  XED_IFORM_FNSAVE_MEMmem94 =1184 ,
  XED_IFORM_FNSTCW_MEMmem16 =1185 ,
  XED_IFORM_FNSTENV_MEMmem14 =1186 ,
  XED_IFORM_FNSTENV_MEMmem28 =1187 ,
  XED_IFORM_FNSTSW_AX =1188 ,
  XED_IFORM_FNSTSW_MEMmem16 =1189 ,
  XED_IFORM_FPATAN =1190 ,
  XED_IFORM_FPREM =1191 ,
  XED_IFORM_FPREM1 =1192 ,
  XED_IFORM_FPTAN =1193 ,
  XED_IFORM_FRNDINT =1194 ,
  XED_IFORM_FRSTOR_MEMmem108 =1195 ,
  XED_IFORM_FRSTOR_MEMmem94 =1196 ,
  XED_IFORM_FSCALE =1197 ,
  XED_IFORM_FSETPM287_NOP =1198 ,
  XED_IFORM_FSIN =1199 ,
  XED_IFORM_FSINCOS =1200 ,
  XED_IFORM_FSQRT =1201 ,
  XED_IFORM_FST_MEMm64real_ST0 =1202 ,
  XED_IFORM_FST_MEMmem32real_ST0 =1203 ,
  XED_IFORM_FST_X87_ST0 =1204 ,
  XED_IFORM_FSTP_MEMm64real_ST0 =1205 ,
  XED_IFORM_FSTP_MEMmem32real_ST0 =1206 ,
  XED_IFORM_FSTP_MEMmem80real_ST0 =1207 ,
  XED_IFORM_FSTP_X87_ST0 =1208 ,
  XED_IFORM_FSTP_X87_ST0_DFD0 =1209 ,
  XED_IFORM_FSTP_X87_ST0_DFD1 =1210 ,
  XED_IFORM_FSTPNCE_X87_ST0 =1211 ,
  XED_IFORM_FSUB_ST0_MEMm64real =1212 ,
  XED_IFORM_FSUB_ST0_MEMmem32real =1213 ,
  XED_IFORM_FSUB_ST0_X87 =1214 ,
  XED_IFORM_FSUB_X87_ST0 =1215 ,
  XED_IFORM_FSUBP_X87_ST0 =1216 ,
  XED_IFORM_FSUBR_ST0_MEMm64real =1217 ,
  XED_IFORM_FSUBR_ST0_MEMmem32real =1218 ,
  XED_IFORM_FSUBR_ST0_X87 =1219 ,
  XED_IFORM_FSUBR_X87_ST0 =1220 ,
  XED_IFORM_FSUBRP_X87_ST0 =1221 ,
  XED_IFORM_FTST =1222 ,
  XED_IFORM_FUCOM_ST0_X87 =1223 ,
  XED_IFORM_FUCOMI_ST0_X87 =1224 ,
  XED_IFORM_FUCOMIP_ST0_X87 =1225 ,
  XED_IFORM_FUCOMP_ST0_X87 =1226 ,
  XED_IFORM_FUCOMPP =1227 ,
  XED_IFORM_FWAIT =1228 ,
  XED_IFORM_FXAM =1229 ,
  XED_IFORM_FXCH_ST0_X87 =1230 ,
  XED_IFORM_FXCH_ST0_X87_DDC1 =1231 ,
  XED_IFORM_FXCH_ST0_X87_DFC1 =1232 ,
  XED_IFORM_FXRSTOR_MEMmfpxenv =1233 ,
  XED_IFORM_FXRSTOR64_MEMmfpxenv =1234 ,
  XED_IFORM_FXSAVE_MEMmfpxenv =1235 ,
  XED_IFORM_FXSAVE64_MEMmfpxenv =1236 ,
  XED_IFORM_FXTRACT =1237 ,
  XED_IFORM_FYL2X =1238 ,
  XED_IFORM_FYL2XP1 =1239 ,
  XED_IFORM_GETSEC =1240 ,
  XED_IFORM_GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8 =1241 ,
  XED_IFORM_GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8 =1242 ,
  XED_IFORM_GF2P8AFFINEQB_XMMu8_MEMu64_IMM8 =1243 ,
  XED_IFORM_GF2P8AFFINEQB_XMMu8_XMMu64_IMM8 =1244 ,
  XED_IFORM_GF2P8MULB_XMMu8_MEMu8 =1245 ,
  XED_IFORM_GF2P8MULB_XMMu8_XMMu8 =1246 ,
  XED_IFORM_HADDPD_XMMpd_MEMpd =1247 ,
  XED_IFORM_HADDPD_XMMpd_XMMpd =1248 ,
  XED_IFORM_HADDPS_XMMps_MEMps =1249 ,
  XED_IFORM_HADDPS_XMMps_XMMps =1250 ,
  XED_IFORM_HLT =1251 ,
  XED_IFORM_HRESET_IMM8 =1252 ,
  XED_IFORM_HSUBPD_XMMpd_MEMpd =1253 ,
  XED_IFORM_HSUBPD_XMMpd_XMMpd =1254 ,
  XED_IFORM_HSUBPS_XMMps_MEMps =1255 ,
  XED_IFORM_HSUBPS_XMMps_XMMps =1256 ,
  XED_IFORM_IDIV_GPR8 =1257 ,
  XED_IFORM_IDIV_GPR8i8_APX =1258 ,
  XED_IFORM_IDIV_GPRv =1259 ,
  XED_IFORM_IDIV_GPRv_APX =1260 ,
  XED_IFORM_IDIV_MEMb =1261 ,
  XED_IFORM_IDIV_MEMi8_APX =1262 ,
  XED_IFORM_IDIV_MEMv =1263 ,
  XED_IFORM_IDIV_MEMv_APX =1264 ,
  XED_IFORM_IMUL_GPR8 =1265 ,
  XED_IFORM_IMUL_GPR8i8_APX =1266 ,
  XED_IFORM_IMUL_GPRv =1267 ,
  XED_IFORM_IMUL_GPRv_APX =1268 ,
  XED_IFORM_IMUL_GPRv_GPRv =1269 ,
  XED_IFORM_IMUL_GPRv_GPRv_APX =1270 ,
  XED_IFORM_IMUL_GPRv_GPRv_GPRv_APX =1271 ,
  XED_IFORM_IMUL_GPRv_GPRv_IMM8_APX =1272 ,
  XED_IFORM_IMUL_GPRv_GPRv_IMM8_APX_ZU =1273 ,
  XED_IFORM_IMUL_GPRv_GPRv_IMMb =1274 ,
  XED_IFORM_IMUL_GPRv_GPRv_IMMz =1275 ,
  XED_IFORM_IMUL_GPRv_GPRv_IMMz_APX =1276 ,
  XED_IFORM_IMUL_GPRv_GPRv_IMMz_APX_ZU =1277 ,
  XED_IFORM_IMUL_GPRv_GPRv_MEMv_APX =1278 ,
  XED_IFORM_IMUL_GPRv_MEMv =1279 ,
  XED_IFORM_IMUL_GPRv_MEMv_APX =1280 ,
  XED_IFORM_IMUL_GPRv_MEMv_IMM8_APX =1281 ,
  XED_IFORM_IMUL_GPRv_MEMv_IMM8_APX_ZU =1282 ,
  XED_IFORM_IMUL_GPRv_MEMv_IMMb =1283 ,
  XED_IFORM_IMUL_GPRv_MEMv_IMMz =1284 ,
  XED_IFORM_IMUL_GPRv_MEMv_IMMz_APX =1285 ,
  XED_IFORM_IMUL_GPRv_MEMv_IMMz_APX_ZU =1286 ,
  XED_IFORM_IMUL_MEMb =1287 ,
  XED_IFORM_IMUL_MEMi8_APX =1288 ,
  XED_IFORM_IMUL_MEMv =1289 ,
  XED_IFORM_IMUL_MEMv_APX =1290 ,
  XED_IFORM_IN_AL_DX =1291 ,
  XED_IFORM_IN_AL_IMMb =1292 ,
  XED_IFORM_IN_OeAX_DX =1293 ,
  XED_IFORM_IN_OeAX_IMMb =1294 ,
  XED_IFORM_INC_GPR8 =1295 ,
  XED_IFORM_INC_GPR8i8_APX =1296 ,
  XED_IFORM_INC_GPR8i8_GPR8i8_APX =1297 ,
  XED_IFORM_INC_GPR8i8_MEMi8_APX =1298 ,
  XED_IFORM_INC_GPRv_40 =1299 ,
  XED_IFORM_INC_GPRv_APX =1300 ,
  XED_IFORM_INC_GPRv_FFr0 =1301 ,
  XED_IFORM_INC_GPRv_GPRv_APX =1302 ,
  XED_IFORM_INC_GPRv_MEMv_APX =1303 ,
  XED_IFORM_INC_MEMb =1304 ,
  XED_IFORM_INC_MEMi8_APX =1305 ,
  XED_IFORM_INC_MEMv =1306 ,
  XED_IFORM_INC_MEMv_APX =1307 ,
  XED_IFORM_INCSSPD_GPR32u8 =1308 ,
  XED_IFORM_INCSSPQ_GPR64u8 =1309 ,
  XED_IFORM_INC_LOCK_MEMb =1310 ,
  XED_IFORM_INC_LOCK_MEMv =1311 ,
  XED_IFORM_INSB =1312 ,
  XED_IFORM_INSD =1313 ,
  XED_IFORM_INSERTPS_XMMps_MEMd_IMMb =1314 ,
  XED_IFORM_INSERTPS_XMMps_XMMps_IMMb =1315 ,
  XED_IFORM_INSERTQ_XMMq_XMMdq =1316 ,
  XED_IFORM_INSERTQ_XMMq_XMMq_IMMb_IMMb =1317 ,
  XED_IFORM_INSW =1318 ,
  XED_IFORM_INT_IMMb =1319 ,
  XED_IFORM_INT1 =1320 ,
  XED_IFORM_INT3 =1321 ,
  XED_IFORM_INTO =1322 ,
  XED_IFORM_INVD =1323 ,
  XED_IFORM_INVEPT_GPR32_MEMdq =1324 ,
  XED_IFORM_INVEPT_GPR64_MEMdq =1325 ,
  XED_IFORM_INVEPT_GPR64i64_MEMi128_APX =1326 ,
  XED_IFORM_INVLPG_MEMb =1327 ,
  XED_IFORM_INVLPGA_ArAX_ECX =1328 ,
  XED_IFORM_INVLPGB =1329 ,
  XED_IFORM_INVPCID_GPR32_MEMdq =1330 ,
  XED_IFORM_INVPCID_GPR64_MEMdq =1331 ,
  XED_IFORM_INVPCID_GPR64i64_MEMi128_APX =1332 ,
  XED_IFORM_INVVPID_GPR32_MEMdq =1333 ,
  XED_IFORM_INVVPID_GPR64_MEMdq =1334 ,
  XED_IFORM_INVVPID_GPR64i64_MEMi128_APX =1335 ,
  XED_IFORM_IRET =1336 ,
  XED_IFORM_IRETD =1337 ,
  XED_IFORM_IRETQ =1338 ,
  XED_IFORM_JB_RELBRb =1339 ,
  XED_IFORM_JB_RELBRd =1340 ,
  XED_IFORM_JB_RELBRz =1341 ,
  XED_IFORM_JBE_RELBRb =1342 ,
  XED_IFORM_JBE_RELBRd =1343 ,
  XED_IFORM_JBE_RELBRz =1344 ,
  XED_IFORM_JCXZ_RELBRb =1345 ,
  XED_IFORM_JECXZ_RELBRb =1346 ,
  XED_IFORM_JL_RELBRb =1347 ,
  XED_IFORM_JL_RELBRd =1348 ,
  XED_IFORM_JL_RELBRz =1349 ,
  XED_IFORM_JLE_RELBRb =1350 ,
  XED_IFORM_JLE_RELBRd =1351 ,
  XED_IFORM_JLE_RELBRz =1352 ,
  XED_IFORM_JMP_GPRv =1353 ,
  XED_IFORM_JMP_MEMv =1354 ,
  XED_IFORM_JMP_RELBRb =1355 ,
  XED_IFORM_JMP_RELBRd =1356 ,
  XED_IFORM_JMP_RELBRz =1357 ,
  XED_IFORM_JMPABS_ABSBRu64_APX =1358 ,
  XED_IFORM_JMP_FAR_MEMp2 =1359 ,
  XED_IFORM_JMP_FAR_PTRp_IMMw =1360 ,
  XED_IFORM_JNB_RELBRb =1361 ,
  XED_IFORM_JNB_RELBRd =1362 ,
  XED_IFORM_JNB_RELBRz =1363 ,
  XED_IFORM_JNBE_RELBRb =1364 ,
  XED_IFORM_JNBE_RELBRd =1365 ,
  XED_IFORM_JNBE_RELBRz =1366 ,
  XED_IFORM_JNL_RELBRb =1367 ,
  XED_IFORM_JNL_RELBRd =1368 ,
  XED_IFORM_JNL_RELBRz =1369 ,
  XED_IFORM_JNLE_RELBRb =1370 ,
  XED_IFORM_JNLE_RELBRd =1371 ,
  XED_IFORM_JNLE_RELBRz =1372 ,
  XED_IFORM_JNO_RELBRb =1373 ,
  XED_IFORM_JNO_RELBRd =1374 ,
  XED_IFORM_JNO_RELBRz =1375 ,
  XED_IFORM_JNP_RELBRb =1376 ,
  XED_IFORM_JNP_RELBRd =1377 ,
  XED_IFORM_JNP_RELBRz =1378 ,
  XED_IFORM_JNS_RELBRb =1379 ,
  XED_IFORM_JNS_RELBRd =1380 ,
  XED_IFORM_JNS_RELBRz =1381 ,
  XED_IFORM_JNZ_RELBRb =1382 ,
  XED_IFORM_JNZ_RELBRd =1383 ,
  XED_IFORM_JNZ_RELBRz =1384 ,
  XED_IFORM_JO_RELBRb =1385 ,
  XED_IFORM_JO_RELBRd =1386 ,
  XED_IFORM_JO_RELBRz =1387 ,
  XED_IFORM_JP_RELBRb =1388 ,
  XED_IFORM_JP_RELBRd =1389 ,
  XED_IFORM_JP_RELBRz =1390 ,
  XED_IFORM_JRCXZ_RELBRb =1391 ,
  XED_IFORM_JS_RELBRb =1392 ,
  XED_IFORM_JS_RELBRd =1393 ,
  XED_IFORM_JS_RELBRz =1394 ,
  XED_IFORM_JZ_RELBRb =1395 ,
  XED_IFORM_JZ_RELBRd =1396 ,
  XED_IFORM_JZ_RELBRz =1397 ,
  XED_IFORM_KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512 =1398 ,
  XED_IFORM_KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512 =1399 ,
  XED_IFORM_KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 =1400 ,
  XED_IFORM_KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512 =1401 ,
  XED_IFORM_KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512 =1402 ,
  XED_IFORM_KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512 =1403 ,
  XED_IFORM_KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512 =1404 ,
  XED_IFORM_KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512 =1405 ,
  XED_IFORM_KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512 =1406 ,
  XED_IFORM_KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512 =1407 ,
  XED_IFORM_KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 =1408 ,
  XED_IFORM_KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512 =1409 ,
  XED_IFORM_KMOVB_GPR32u32_MASKmskw_APX =1410 ,
  XED_IFORM_KMOVB_GPR32u32_MASKmskw_AVX512 =1411 ,
  XED_IFORM_KMOVB_MASKmskw_GPR32u32_APX =1412 ,
  XED_IFORM_KMOVB_MASKmskw_GPR32u32_AVX512 =1413 ,
  XED_IFORM_KMOVB_MASKmskw_MASKu8_APX =1414 ,
  XED_IFORM_KMOVB_MASKmskw_MASKu8_AVX512 =1415 ,
  XED_IFORM_KMOVB_MASKmskw_MEMu8_APX =1416 ,
  XED_IFORM_KMOVB_MASKmskw_MEMu8_AVX512 =1417 ,
  XED_IFORM_KMOVB_MEMu8_MASKmskw_APX =1418 ,
  XED_IFORM_KMOVB_MEMu8_MASKmskw_AVX512 =1419 ,
  XED_IFORM_KMOVD_GPR32u32_MASKmskw_APX =1420 ,
  XED_IFORM_KMOVD_GPR32u32_MASKmskw_AVX512 =1421 ,
  XED_IFORM_KMOVD_MASKmskw_GPR32u32_APX =1422 ,
  XED_IFORM_KMOVD_MASKmskw_GPR32u32_AVX512 =1423 ,
  XED_IFORM_KMOVD_MASKmskw_MASKu32_APX =1424 ,
  XED_IFORM_KMOVD_MASKmskw_MASKu32_AVX512 =1425 ,
  XED_IFORM_KMOVD_MASKmskw_MEMu32_APX =1426 ,
  XED_IFORM_KMOVD_MASKmskw_MEMu32_AVX512 =1427 ,
  XED_IFORM_KMOVD_MEMu32_MASKmskw_APX =1428 ,
  XED_IFORM_KMOVD_MEMu32_MASKmskw_AVX512 =1429 ,
  XED_IFORM_KMOVQ_GPR64u64_MASKmskw_APX =1430 ,
  XED_IFORM_KMOVQ_GPR64u64_MASKmskw_AVX512 =1431 ,
  XED_IFORM_KMOVQ_MASKmskw_GPR64u64_APX =1432 ,
  XED_IFORM_KMOVQ_MASKmskw_GPR64u64_AVX512 =1433 ,
  XED_IFORM_KMOVQ_MASKmskw_MASKu64_APX =1434 ,
  XED_IFORM_KMOVQ_MASKmskw_MASKu64_AVX512 =1435 ,
  XED_IFORM_KMOVQ_MASKmskw_MEMu64_APX =1436 ,
  XED_IFORM_KMOVQ_MASKmskw_MEMu64_AVX512 =1437 ,
  XED_IFORM_KMOVQ_MEMu64_MASKmskw_APX =1438 ,
  XED_IFORM_KMOVQ_MEMu64_MASKmskw_AVX512 =1439 ,
  XED_IFORM_KMOVW_GPR32u32_MASKmskw_APX =1440 ,
  XED_IFORM_KMOVW_GPR32u32_MASKmskw_AVX512 =1441 ,
  XED_IFORM_KMOVW_MASKmskw_GPR32u32_APX =1442 ,
  XED_IFORM_KMOVW_MASKmskw_GPR32u32_AVX512 =1443 ,
  XED_IFORM_KMOVW_MASKmskw_MASKu16_APX =1444 ,
  XED_IFORM_KMOVW_MASKmskw_MASKu16_AVX512 =1445 ,
  XED_IFORM_KMOVW_MASKmskw_MEMu16_APX =1446 ,
  XED_IFORM_KMOVW_MASKmskw_MEMu16_AVX512 =1447 ,
  XED_IFORM_KMOVW_MEMu16_MASKmskw_APX =1448 ,
  XED_IFORM_KMOVW_MEMu16_MASKmskw_AVX512 =1449 ,
  XED_IFORM_KNOTB_MASKmskw_MASKmskw_AVX512 =1450 ,
  XED_IFORM_KNOTD_MASKmskw_MASKmskw_AVX512 =1451 ,
  XED_IFORM_KNOTQ_MASKmskw_MASKmskw_AVX512 =1452 ,
  XED_IFORM_KNOTW_MASKmskw_MASKmskw_AVX512 =1453 ,
  XED_IFORM_KORB_MASKmskw_MASKmskw_MASKmskw_AVX512 =1454 ,
  XED_IFORM_KORD_MASKmskw_MASKmskw_MASKmskw_AVX512 =1455 ,
  XED_IFORM_KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 =1456 ,
  XED_IFORM_KORTESTB_MASKmskw_MASKmskw_AVX512 =1457 ,
  XED_IFORM_KORTESTD_MASKmskw_MASKmskw_AVX512 =1458 ,
  XED_IFORM_KORTESTQ_MASKmskw_MASKmskw_AVX512 =1459 ,
  XED_IFORM_KORTESTW_MASKmskw_MASKmskw_AVX512 =1460 ,
  XED_IFORM_KORW_MASKmskw_MASKmskw_MASKmskw_AVX512 =1461 ,
  XED_IFORM_KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512 =1462 ,
  XED_IFORM_KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512 =1463 ,
  XED_IFORM_KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512 =1464 ,
  XED_IFORM_KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512 =1465 ,
  XED_IFORM_KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512 =1466 ,
  XED_IFORM_KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512 =1467 ,
  XED_IFORM_KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512 =1468 ,
  XED_IFORM_KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512 =1469 ,
  XED_IFORM_KTESTB_MASKmskw_MASKmskw_AVX512 =1470 ,
  XED_IFORM_KTESTD_MASKmskw_MASKmskw_AVX512 =1471 ,
  XED_IFORM_KTESTQ_MASKmskw_MASKmskw_AVX512 =1472 ,
  XED_IFORM_KTESTW_MASKmskw_MASKmskw_AVX512 =1473 ,
  XED_IFORM_KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512 =1474 ,
  XED_IFORM_KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 =1475 ,
  XED_IFORM_KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512 =1476 ,
  XED_IFORM_KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512 =1477 ,
  XED_IFORM_KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512 =1478 ,
  XED_IFORM_KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 =1479 ,
  XED_IFORM_KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512 =1480 ,
  XED_IFORM_KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512 =1481 ,
  XED_IFORM_KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512 =1482 ,
  XED_IFORM_KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 =1483 ,
  XED_IFORM_KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512 =1484 ,
  XED_IFORM_LAHF =1485 ,
  XED_IFORM_LAR_GPRv_GPRv =1486 ,
  XED_IFORM_LAR_GPRv_MEMw =1487 ,
  XED_IFORM_LDDQU_XMMpd_MEMdq =1488 ,
  XED_IFORM_LDMXCSR_MEMd =1489 ,
  XED_IFORM_LDS_GPRz_MEMp =1490 ,
  XED_IFORM_LDTILECFG_MEM =1491 ,
  XED_IFORM_LDTILECFG_MEM_APX =1492 ,
  XED_IFORM_LEA_GPRv_AGEN =1493 ,
  XED_IFORM_LEAVE =1494 ,
  XED_IFORM_LES_GPRz_MEMp =1495 ,
  XED_IFORM_LFENCE =1496 ,
  XED_IFORM_LFS_GPRv_MEMp2 =1497 ,
  XED_IFORM_LGDT_MEMs =1498 ,
  XED_IFORM_LGDT_MEMs64 =1499 ,
  XED_IFORM_LGS_GPRv_MEMp2 =1500 ,
  XED_IFORM_LIDT_MEMs =1501 ,
  XED_IFORM_LIDT_MEMs64 =1502 ,
  XED_IFORM_LKGS_GPR16u16 =1503 ,
  XED_IFORM_LKGS_MEMu16 =1504 ,
  XED_IFORM_LLDT_GPR16 =1505 ,
  XED_IFORM_LLDT_MEMw =1506 ,
  XED_IFORM_LLWPCB_GPRyy =1507 ,
  XED_IFORM_LMSW_GPR16 =1508 ,
  XED_IFORM_LMSW_MEMw =1509 ,
  XED_IFORM_LOADIWKEY_XMMu8_XMMu8 =1510 ,
  XED_IFORM_LODSB =1511 ,
  XED_IFORM_LODSD =1512 ,
  XED_IFORM_LODSQ =1513 ,
  XED_IFORM_LODSW =1514 ,
  XED_IFORM_LOOP_RELBRb =1515 ,
  XED_IFORM_LOOPE_RELBRb =1516 ,
  XED_IFORM_LOOPNE_RELBRb =1517 ,
  XED_IFORM_LSL_GPRv_GPRz =1518 ,
  XED_IFORM_LSL_GPRv_MEMw =1519 ,
  XED_IFORM_LSS_GPRv_MEMp2 =1520 ,
  XED_IFORM_LTR_GPR16 =1521 ,
  XED_IFORM_LTR_MEMw =1522 ,
  XED_IFORM_LWPINS_GPRyy_GPR32d_IMMd =1523 ,
  XED_IFORM_LWPINS_GPRyy_MEMd_IMMd =1524 ,
  XED_IFORM_LWPVAL_GPRyy_GPR32d_IMMd =1525 ,
  XED_IFORM_LWPVAL_GPRyy_MEMd_IMMd =1526 ,
  XED_IFORM_LZCNT_GPRv_GPRv =1527 ,
  XED_IFORM_LZCNT_GPRv_GPRv_APX =1528 ,
  XED_IFORM_LZCNT_GPRv_MEMv =1529 ,
  XED_IFORM_LZCNT_GPRv_MEMv_APX =1530 ,
  XED_IFORM_MASKMOVDQU_XMMxub_XMMxub =1531 ,
  XED_IFORM_MASKMOVQ_MMXq_MMXq =1532 ,
  XED_IFORM_MAXPD_XMMpd_MEMpd =1533 ,
  XED_IFORM_MAXPD_XMMpd_XMMpd =1534 ,
  XED_IFORM_MAXPS_XMMps_MEMps =1535 ,
  XED_IFORM_MAXPS_XMMps_XMMps =1536 ,
  XED_IFORM_MAXSD_XMMsd_MEMsd =1537 ,
  XED_IFORM_MAXSD_XMMsd_XMMsd =1538 ,
  XED_IFORM_MAXSS_XMMss_MEMss =1539 ,
  XED_IFORM_MAXSS_XMMss_XMMss =1540 ,
  XED_IFORM_MCOMMIT =1541 ,
  XED_IFORM_MFENCE =1542 ,
  XED_IFORM_MINPD_XMMpd_MEMpd =1543 ,
  XED_IFORM_MINPD_XMMpd_XMMpd =1544 ,
  XED_IFORM_MINPS_XMMps_MEMps =1545 ,
  XED_IFORM_MINPS_XMMps_XMMps =1546 ,
  XED_IFORM_MINSD_XMMsd_MEMsd =1547 ,
  XED_IFORM_MINSD_XMMsd_XMMsd =1548 ,
  XED_IFORM_MINSS_XMMss_MEMss =1549 ,
  XED_IFORM_MINSS_XMMss_XMMss =1550 ,
  XED_IFORM_MONITOR =1551 ,
  XED_IFORM_MONITORX =1552 ,
  XED_IFORM_MOV_AL_MEMb =1553 ,
  XED_IFORM_MOV_GPR8_GPR8_88 =1554 ,
  XED_IFORM_MOV_GPR8_GPR8_8A =1555 ,
  XED_IFORM_MOV_GPR8_IMMb_B0 =1556 ,
  XED_IFORM_MOV_GPR8_IMMb_C6r0 =1557 ,
  XED_IFORM_MOV_GPR8_MEMb =1558 ,
  XED_IFORM_MOV_GPRv_GPRv_89 =1559 ,
  XED_IFORM_MOV_GPRv_GPRv_8B =1560 ,
  XED_IFORM_MOV_GPRv_IMMv =1561 ,
  XED_IFORM_MOV_GPRv_IMMz =1562 ,
  XED_IFORM_MOV_GPRv_MEMv =1563 ,
  XED_IFORM_MOV_GPRv_SEG =1564 ,
  XED_IFORM_MOV_MEMb_AL =1565 ,
  XED_IFORM_MOV_MEMb_GPR8 =1566 ,
  XED_IFORM_MOV_MEMb_IMMb =1567 ,
  XED_IFORM_MOV_MEMv_GPRv =1568 ,
  XED_IFORM_MOV_MEMv_IMMz =1569 ,
  XED_IFORM_MOV_MEMv_OrAX =1570 ,
  XED_IFORM_MOV_MEMw_SEG =1571 ,
  XED_IFORM_MOV_OrAX_MEMv =1572 ,
  XED_IFORM_MOV_SEG_GPR16 =1573 ,
  XED_IFORM_MOV_SEG_MEMw =1574 ,
  XED_IFORM_MOVAPD_MEMpd_XMMpd =1575 ,
  XED_IFORM_MOVAPD_XMMpd_MEMpd =1576 ,
  XED_IFORM_MOVAPD_XMMpd_XMMpd_0F28 =1577 ,
  XED_IFORM_MOVAPD_XMMpd_XMMpd_0F29 =1578 ,
  XED_IFORM_MOVAPS_MEMps_XMMps =1579 ,
  XED_IFORM_MOVAPS_XMMps_MEMps =1580 ,
  XED_IFORM_MOVAPS_XMMps_XMMps_0F28 =1581 ,
  XED_IFORM_MOVAPS_XMMps_XMMps_0F29 =1582 ,
  XED_IFORM_MOVBE_GPRv_GPRv_APX =1583 ,
  XED_IFORM_MOVBE_GPRv_MEMv =1584 ,
  XED_IFORM_MOVBE_GPRv_MEMv_APX =1585 ,
  XED_IFORM_MOVBE_MEMv_GPRv =1586 ,
  XED_IFORM_MOVBE_MEMv_GPRv_APX =1587 ,
  XED_IFORM_MOVD_GPR32_MMXd =1588 ,
  XED_IFORM_MOVD_GPR32_XMMd =1589 ,
  XED_IFORM_MOVD_MEMd_MMXd =1590 ,
  XED_IFORM_MOVD_MEMd_XMMd =1591 ,
  XED_IFORM_MOVD_MMXq_GPR32 =1592 ,
  XED_IFORM_MOVD_MMXq_MEMd =1593 ,
  XED_IFORM_MOVD_XMMdq_GPR32 =1594 ,
  XED_IFORM_MOVD_XMMdq_MEMd =1595 ,
  XED_IFORM_MOVDDUP_XMMdq_MEMq =1596 ,
  XED_IFORM_MOVDDUP_XMMdq_XMMq =1597 ,
  XED_IFORM_MOVDIR64B_GPRa_MEM =1598 ,
  XED_IFORM_MOVDIR64B_GPRav_MEMu32_APX =1599 ,
  XED_IFORM_MOVDIRI_MEMu32_GPR32u32 =1600 ,
  XED_IFORM_MOVDIRI_MEMu64_GPR64u64 =1601 ,
  XED_IFORM_MOVDIRI_MEMyu_GPRyu_APX =1602 ,
  XED_IFORM_MOVDQ2Q_MMXq_XMMq =1603 ,
  XED_IFORM_MOVDQA_MEMdq_XMMdq =1604 ,
  XED_IFORM_MOVDQA_XMMdq_MEMdq =1605 ,
  XED_IFORM_MOVDQA_XMMdq_XMMdq_0F6F =1606 ,
  XED_IFORM_MOVDQA_XMMdq_XMMdq_0F7F =1607 ,
  XED_IFORM_MOVDQU_MEMdq_XMMdq =1608 ,
  XED_IFORM_MOVDQU_XMMdq_MEMdq =1609 ,
  XED_IFORM_MOVDQU_XMMdq_XMMdq_0F6F =1610 ,
  XED_IFORM_MOVDQU_XMMdq_XMMdq_0F7F =1611 ,
  XED_IFORM_MOVHLPS_XMMq_XMMq =1612 ,
  XED_IFORM_MOVHPD_MEMq_XMMsd =1613 ,
  XED_IFORM_MOVHPD_XMMsd_MEMq =1614 ,
  XED_IFORM_MOVHPS_MEMq_XMMps =1615 ,
  XED_IFORM_MOVHPS_XMMq_MEMq =1616 ,
  XED_IFORM_MOVLHPS_XMMq_XMMq =1617 ,
  XED_IFORM_MOVLPD_MEMq_XMMsd =1618 ,
  XED_IFORM_MOVLPD_XMMsd_MEMq =1619 ,
  XED_IFORM_MOVLPS_MEMq_XMMq =1620 ,
  XED_IFORM_MOVLPS_XMMq_MEMq =1621 ,
  XED_IFORM_MOVMSKPD_GPR32_XMMpd =1622 ,
  XED_IFORM_MOVMSKPS_GPR32_XMMps =1623 ,
  XED_IFORM_MOVNTDQ_MEMdq_XMMdq =1624 ,
  XED_IFORM_MOVNTDQA_XMMdq_MEMdq =1625 ,
  XED_IFORM_MOVNTI_MEMd_GPR32 =1626 ,
  XED_IFORM_MOVNTI_MEMq_GPR64 =1627 ,
  XED_IFORM_MOVNTPD_MEMdq_XMMpd =1628 ,
  XED_IFORM_MOVNTPS_MEMdq_XMMps =1629 ,
  XED_IFORM_MOVNTQ_MEMq_MMXq =1630 ,
  XED_IFORM_MOVNTSD_MEMq_XMMq =1631 ,
  XED_IFORM_MOVNTSS_MEMd_XMMd =1632 ,
  XED_IFORM_MOVQ_GPR64_MMXq =1633 ,
  XED_IFORM_MOVQ_GPR64_XMMq =1634 ,
  XED_IFORM_MOVQ_MEMq_MMXq_0F7E =1635 ,
  XED_IFORM_MOVQ_MEMq_MMXq_0F7F =1636 ,
  XED_IFORM_MOVQ_MEMq_XMMq_0F7E =1637 ,
  XED_IFORM_MOVQ_MEMq_XMMq_0FD6 =1638 ,
  XED_IFORM_MOVQ_MMXq_GPR64 =1639 ,
  XED_IFORM_MOVQ_MMXq_MEMq_0F6E =1640 ,
  XED_IFORM_MOVQ_MMXq_MEMq_0F6F =1641 ,
  XED_IFORM_MOVQ_MMXq_MMXq_0F6F =1642 ,
  XED_IFORM_MOVQ_MMXq_MMXq_0F7F =1643 ,
  XED_IFORM_MOVQ_XMMdq_GPR64 =1644 ,
  XED_IFORM_MOVQ_XMMdq_MEMq_0F6E =1645 ,
  XED_IFORM_MOVQ_XMMdq_MEMq_0F7E =1646 ,
  XED_IFORM_MOVQ_XMMdq_XMMq_0F7E =1647 ,
  XED_IFORM_MOVQ_XMMdq_XMMq_0FD6 =1648 ,
  XED_IFORM_MOVQ2DQ_XMMdq_MMXq =1649 ,
  XED_IFORM_MOVRS_GPR8i8_MEMi8 =1650 ,
  XED_IFORM_MOVRS_GPR8i8_MEMi8_APX =1651 ,
  XED_IFORM_MOVRS_GPRv_MEMv =1652 ,
  XED_IFORM_MOVRS_GPRv_MEMv_APX =1653 ,
  XED_IFORM_MOVSB =1654 ,
  XED_IFORM_MOVSD =1655 ,
  XED_IFORM_MOVSD_XMM_MEMsd_XMMsd =1656 ,
  XED_IFORM_MOVSD_XMM_XMMdq_MEMsd =1657 ,
  XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F10 =1658 ,
  XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F11 =1659 ,
  XED_IFORM_MOVSHDUP_XMMps_MEMps =1660 ,
  XED_IFORM_MOVSHDUP_XMMps_XMMps =1661 ,
  XED_IFORM_MOVSLDUP_XMMps_MEMps =1662 ,
  XED_IFORM_MOVSLDUP_XMMps_XMMps =1663 ,
  XED_IFORM_MOVSQ =1664 ,
  XED_IFORM_MOVSS_MEMss_XMMss =1665 ,
  XED_IFORM_MOVSS_XMMdq_MEMss =1666 ,
  XED_IFORM_MOVSS_XMMss_XMMss_0F10 =1667 ,
  XED_IFORM_MOVSS_XMMss_XMMss_0F11 =1668 ,
  XED_IFORM_MOVSW =1669 ,
  XED_IFORM_MOVSX_GPR16_MEMw =1670 ,
  XED_IFORM_MOVSX_GPR32_MEMw =1671 ,
  XED_IFORM_MOVSX_GPR64_MEMw =1672 ,
  XED_IFORM_MOVSX_GPRv_GPR16 =1673 ,
  XED_IFORM_MOVSX_GPRv_GPR8 =1674 ,
  XED_IFORM_MOVSX_GPRv_MEMb =1675 ,
  XED_IFORM_MOVSX_GPRv_MEMw =1676 ,
  XED_IFORM_MOVSXD_GPR64_MEMd =1677 ,
  XED_IFORM_MOVSXD_GPRv_GPRz =1678 ,
  XED_IFORM_MOVSXD_GPRz_MEMz =1679 ,
  XED_IFORM_MOVUPD_MEMpd_XMMpd =1680 ,
  XED_IFORM_MOVUPD_XMMpd_MEMpd =1681 ,
  XED_IFORM_MOVUPD_XMMpd_XMMpd_0F10 =1682 ,
  XED_IFORM_MOVUPD_XMMpd_XMMpd_0F11 =1683 ,
  XED_IFORM_MOVUPS_MEMps_XMMps =1684 ,
  XED_IFORM_MOVUPS_XMMps_MEMps =1685 ,
  XED_IFORM_MOVUPS_XMMps_XMMps_0F10 =1686 ,
  XED_IFORM_MOVUPS_XMMps_XMMps_0F11 =1687 ,
  XED_IFORM_MOVZX_GPR16_MEMw =1688 ,
  XED_IFORM_MOVZX_GPR32_MEMw =1689 ,
  XED_IFORM_MOVZX_GPR64_MEMw =1690 ,
  XED_IFORM_MOVZX_GPRv_GPR16 =1691 ,
  XED_IFORM_MOVZX_GPRv_GPR8 =1692 ,
  XED_IFORM_MOVZX_GPRv_MEMb =1693 ,
  XED_IFORM_MOVZX_GPRv_MEMw =1694 ,
  XED_IFORM_MOV_CR_CR_GPR32 =1695 ,
  XED_IFORM_MOV_CR_CR_GPR64 =1696 ,
  XED_IFORM_MOV_CR_GPR32_CR =1697 ,
  XED_IFORM_MOV_CR_GPR64_CR =1698 ,
  XED_IFORM_MOV_DR_DR_GPR32 =1699 ,
  XED_IFORM_MOV_DR_DR_GPR64 =1700 ,
  XED_IFORM_MOV_DR_GPR32_DR =1701 ,
  XED_IFORM_MOV_DR_GPR64_DR =1702 ,
  XED_IFORM_MPSADBW_XMMdq_MEMdq_IMMb =1703 ,
  XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb =1704 ,
  XED_IFORM_MUL_GPR8 =1705 ,
  XED_IFORM_MUL_GPR8i8_APX =1706 ,
  XED_IFORM_MUL_GPRv =1707 ,
  XED_IFORM_MUL_GPRv_APX =1708 ,
  XED_IFORM_MUL_MEMb =1709 ,
  XED_IFORM_MUL_MEMi8_APX =1710 ,
  XED_IFORM_MUL_MEMv =1711 ,
  XED_IFORM_MUL_MEMv_APX =1712 ,
  XED_IFORM_MULPD_XMMpd_MEMpd =1713 ,
  XED_IFORM_MULPD_XMMpd_XMMpd =1714 ,
  XED_IFORM_MULPS_XMMps_MEMps =1715 ,
  XED_IFORM_MULPS_XMMps_XMMps =1716 ,
  XED_IFORM_MULSD_XMMsd_MEMsd =1717 ,
  XED_IFORM_MULSD_XMMsd_XMMsd =1718 ,
  XED_IFORM_MULSS_XMMss_MEMss =1719 ,
  XED_IFORM_MULSS_XMMss_XMMss =1720 ,
  XED_IFORM_MULX_GPR32d_GPR32d_GPR32d =1721 ,
  XED_IFORM_MULX_GPR32d_GPR32d_MEMd =1722 ,
  XED_IFORM_MULX_GPR32i32_GPR32i32_GPR32i32_APX =1723 ,
  XED_IFORM_MULX_GPR32i32_GPR32i32_MEMi32_APX =1724 ,
  XED_IFORM_MULX_GPR64i64_GPR64i64_GPR64i64_APX =1725 ,
  XED_IFORM_MULX_GPR64i64_GPR64i64_MEMi64_APX =1726 ,
  XED_IFORM_MULX_GPR64q_GPR64q_GPR64q =1727 ,
  XED_IFORM_MULX_GPR64q_GPR64q_MEMq =1728 ,
  XED_IFORM_MWAIT =1729 ,
  XED_IFORM_MWAITX =1730 ,
  XED_IFORM_NEG_GPR8 =1731 ,
  XED_IFORM_NEG_GPR8i8_APX =1732 ,
  XED_IFORM_NEG_GPR8i8_GPR8i8_APX =1733 ,
  XED_IFORM_NEG_GPR8i8_MEMi8_APX =1734 ,
  XED_IFORM_NEG_GPRv =1735 ,
  XED_IFORM_NEG_GPRv_APX =1736 ,
  XED_IFORM_NEG_GPRv_GPRv_APX =1737 ,
  XED_IFORM_NEG_GPRv_MEMv_APX =1738 ,
  XED_IFORM_NEG_MEMb =1739 ,
  XED_IFORM_NEG_MEMi8_APX =1740 ,
  XED_IFORM_NEG_MEMv =1741 ,
  XED_IFORM_NEG_MEMv_APX =1742 ,
  XED_IFORM_NEG_LOCK_MEMb =1743 ,
  XED_IFORM_NEG_LOCK_MEMv =1744 ,
  XED_IFORM_NOP_90 =1745 ,
  XED_IFORM_NOP_GPRv_0F18r0 =1746 ,
  XED_IFORM_NOP_GPRv_0F18r1 =1747 ,
  XED_IFORM_NOP_GPRv_0F18r2 =1748 ,
  XED_IFORM_NOP_GPRv_0F18r3 =1749 ,
  XED_IFORM_NOP_GPRv_0F18r4 =1750 ,
  XED_IFORM_NOP_GPRv_0F18r5 =1751 ,
  XED_IFORM_NOP_GPRv_0F18r6 =1752 ,
  XED_IFORM_NOP_GPRv_0F18r7 =1753 ,
  XED_IFORM_NOP_GPRv_0F1F =1754 ,
  XED_IFORM_NOP_GPRv_GPRv_0F0D =1755 ,
  XED_IFORM_NOP_GPRv_GPRv_0F19 =1756 ,
  XED_IFORM_NOP_GPRv_GPRv_0F1A =1757 ,
  XED_IFORM_NOP_GPRv_GPRv_0F1B =1758 ,
  XED_IFORM_NOP_GPRv_GPRv_0F1C =1759 ,
  XED_IFORM_NOP_GPRv_GPRv_0F1D =1760 ,
  XED_IFORM_NOP_GPRv_GPRv_0F1E =1761 ,
  XED_IFORM_NOP_GPRv_MEM_0F1B =1762 ,
  XED_IFORM_NOP_GPRv_MEMv_0F1A =1763 ,
  XED_IFORM_NOP_MEMv_0F18r4 =1764 ,
  XED_IFORM_NOP_MEMv_0F18r5 =1765 ,
  XED_IFORM_NOP_MEMv_0F18r6 =1766 ,
  XED_IFORM_NOP_MEMv_0F18r7 =1767 ,
  XED_IFORM_NOP_MEMv_0F1F =1768 ,
  XED_IFORM_NOP_MEMv_GPRv_0F19 =1769 ,
  XED_IFORM_NOP_MEMv_GPRv_0F1C =1770 ,
  XED_IFORM_NOP_MEMv_GPRv_0F1D =1771 ,
  XED_IFORM_NOP_MEMv_GPRv_0F1E =1772 ,
  XED_IFORM_NOT_GPR8 =1773 ,
  XED_IFORM_NOT_GPR8i8_APX =1774 ,
  XED_IFORM_NOT_GPR8i8_GPR8i8_APX =1775 ,
  XED_IFORM_NOT_GPR8i8_MEMi8_APX =1776 ,
  XED_IFORM_NOT_GPRv =1777 ,
  XED_IFORM_NOT_GPRv_APX =1778 ,
  XED_IFORM_NOT_GPRv_GPRv_APX =1779 ,
  XED_IFORM_NOT_GPRv_MEMv_APX =1780 ,
  XED_IFORM_NOT_MEMb =1781 ,
  XED_IFORM_NOT_MEMi8_APX =1782 ,
  XED_IFORM_NOT_MEMv =1783 ,
  XED_IFORM_NOT_MEMv_APX =1784 ,
  XED_IFORM_NOT_LOCK_MEMb =1785 ,
  XED_IFORM_NOT_LOCK_MEMv =1786 ,
  XED_IFORM_OR_AL_IMMb =1787 ,
  XED_IFORM_OR_GPR8_GPR8_08 =1788 ,
  XED_IFORM_OR_GPR8_GPR8_0A =1789 ,
  XED_IFORM_OR_GPR8_IMMb_80r1 =1790 ,
  XED_IFORM_OR_GPR8_IMMb_82r1 =1791 ,
  XED_IFORM_OR_GPR8_MEMb =1792 ,
  XED_IFORM_OR_GPR8i8_GPR8i8_APX =1793 ,
  XED_IFORM_OR_GPR8i8_GPR8i8_GPR8i8_APX =1794 ,
  XED_IFORM_OR_GPR8i8_GPR8i8_IMM8_APX =1795 ,
  XED_IFORM_OR_GPR8i8_GPR8i8_MEMi8_APX =1796 ,
  XED_IFORM_OR_GPR8i8_IMM8_APX =1797 ,
  XED_IFORM_OR_GPR8i8_MEMi8_APX =1798 ,
  XED_IFORM_OR_GPR8i8_MEMi8_GPR8i8_APX =1799 ,
  XED_IFORM_OR_GPR8i8_MEMi8_IMM8_APX =1800 ,
  XED_IFORM_OR_GPRv_GPRv_09 =1801 ,
  XED_IFORM_OR_GPRv_GPRv_0B =1802 ,
  XED_IFORM_OR_GPRv_GPRv_APX =1803 ,
  XED_IFORM_OR_GPRv_GPRv_GPRv_APX =1804 ,
  XED_IFORM_OR_GPRv_GPRv_IMM8_APX =1805 ,
  XED_IFORM_OR_GPRv_GPRv_IMMz_APX =1806 ,
  XED_IFORM_OR_GPRv_GPRv_MEMv_APX =1807 ,
  XED_IFORM_OR_GPRv_IMM8_APX =1808 ,
  XED_IFORM_OR_GPRv_IMMb =1809 ,
  XED_IFORM_OR_GPRv_IMMz =1810 ,
  XED_IFORM_OR_GPRv_IMMz_APX =1811 ,
  XED_IFORM_OR_GPRv_MEMv =1812 ,
  XED_IFORM_OR_GPRv_MEMv_APX =1813 ,
  XED_IFORM_OR_GPRv_MEMv_GPRv_APX =1814 ,
  XED_IFORM_OR_GPRv_MEMv_IMM8_APX =1815 ,
  XED_IFORM_OR_GPRv_MEMv_IMMz_APX =1816 ,
  XED_IFORM_OR_MEMb_GPR8 =1817 ,
  XED_IFORM_OR_MEMb_IMMb_80r1 =1818 ,
  XED_IFORM_OR_MEMb_IMMb_82r1 =1819 ,
  XED_IFORM_OR_MEMi8_GPR8i8_APX =1820 ,
  XED_IFORM_OR_MEMi8_IMM8_APX =1821 ,
  XED_IFORM_OR_MEMv_GPRv =1822 ,
  XED_IFORM_OR_MEMv_GPRv_APX =1823 ,
  XED_IFORM_OR_MEMv_IMM8_APX =1824 ,
  XED_IFORM_OR_MEMv_IMMb =1825 ,
  XED_IFORM_OR_MEMv_IMMz =1826 ,
  XED_IFORM_OR_MEMv_IMMz_APX =1827 ,
  XED_IFORM_OR_OrAX_IMMz =1828 ,
  XED_IFORM_ORPD_XMMxuq_MEMxuq =1829 ,
  XED_IFORM_ORPD_XMMxuq_XMMxuq =1830 ,
  XED_IFORM_ORPS_XMMxud_MEMxud =1831 ,
  XED_IFORM_ORPS_XMMxud_XMMxud =1832 ,
  XED_IFORM_OR_LOCK_MEMb_GPR8 =1833 ,
  XED_IFORM_OR_LOCK_MEMb_IMMb_80r1 =1834 ,
  XED_IFORM_OR_LOCK_MEMb_IMMb_82r1 =1835 ,
  XED_IFORM_OR_LOCK_MEMv_GPRv =1836 ,
  XED_IFORM_OR_LOCK_MEMv_IMMb =1837 ,
  XED_IFORM_OR_LOCK_MEMv_IMMz =1838 ,
  XED_IFORM_OUT_DX_AL =1839 ,
  XED_IFORM_OUT_DX_OeAX =1840 ,
  XED_IFORM_OUT_IMMb_AL =1841 ,
  XED_IFORM_OUT_IMMb_OeAX =1842 ,
  XED_IFORM_OUTSB =1843 ,
  XED_IFORM_OUTSD =1844 ,
  XED_IFORM_OUTSW =1845 ,
  XED_IFORM_PABSB_MMXq_MEMq =1846 ,
  XED_IFORM_PABSB_MMXq_MMXq =1847 ,
  XED_IFORM_PABSB_XMMdq_MEMdq =1848 ,
  XED_IFORM_PABSB_XMMdq_XMMdq =1849 ,
  XED_IFORM_PABSD_MMXq_MEMq =1850 ,
  XED_IFORM_PABSD_MMXq_MMXq =1851 ,
  XED_IFORM_PABSD_XMMdq_MEMdq =1852 ,
  XED_IFORM_PABSD_XMMdq_XMMdq =1853 ,
  XED_IFORM_PABSW_MMXq_MEMq =1854 ,
  XED_IFORM_PABSW_MMXq_MMXq =1855 ,
  XED_IFORM_PABSW_XMMdq_MEMdq =1856 ,
  XED_IFORM_PABSW_XMMdq_XMMdq =1857 ,
  XED_IFORM_PACKSSDW_MMXq_MEMq =1858 ,
  XED_IFORM_PACKSSDW_MMXq_MMXq =1859 ,
  XED_IFORM_PACKSSDW_XMMdq_MEMdq =1860 ,
  XED_IFORM_PACKSSDW_XMMdq_XMMdq =1861 ,
  XED_IFORM_PACKSSWB_MMXq_MEMq =1862 ,
  XED_IFORM_PACKSSWB_MMXq_MMXq =1863 ,
  XED_IFORM_PACKSSWB_XMMdq_MEMdq =1864 ,
  XED_IFORM_PACKSSWB_XMMdq_XMMdq =1865 ,
  XED_IFORM_PACKUSDW_XMMdq_MEMdq =1866 ,
  XED_IFORM_PACKUSDW_XMMdq_XMMdq =1867 ,
  XED_IFORM_PACKUSWB_MMXq_MEMq =1868 ,
  XED_IFORM_PACKUSWB_MMXq_MMXq =1869 ,
  XED_IFORM_PACKUSWB_XMMdq_MEMdq =1870 ,
  XED_IFORM_PACKUSWB_XMMdq_XMMdq =1871 ,
  XED_IFORM_PADDB_MMXq_MEMq =1872 ,
  XED_IFORM_PADDB_MMXq_MMXq =1873 ,
  XED_IFORM_PADDB_XMMdq_MEMdq =1874 ,
  XED_IFORM_PADDB_XMMdq_XMMdq =1875 ,
  XED_IFORM_PADDD_MMXq_MEMq =1876 ,
  XED_IFORM_PADDD_MMXq_MMXq =1877 ,
  XED_IFORM_PADDD_XMMdq_MEMdq =1878 ,
  XED_IFORM_PADDD_XMMdq_XMMdq =1879 ,
  XED_IFORM_PADDQ_MMXq_MEMq =1880 ,
  XED_IFORM_PADDQ_MMXq_MMXq =1881 ,
  XED_IFORM_PADDQ_XMMdq_MEMdq =1882 ,
  XED_IFORM_PADDQ_XMMdq_XMMdq =1883 ,
  XED_IFORM_PADDSB_MMXq_MEMq =1884 ,
  XED_IFORM_PADDSB_MMXq_MMXq =1885 ,
  XED_IFORM_PADDSB_XMMdq_MEMdq =1886 ,
  XED_IFORM_PADDSB_XMMdq_XMMdq =1887 ,
  XED_IFORM_PADDSW_MMXq_MEMq =1888 ,
  XED_IFORM_PADDSW_MMXq_MMXq =1889 ,
  XED_IFORM_PADDSW_XMMdq_MEMdq =1890 ,
  XED_IFORM_PADDSW_XMMdq_XMMdq =1891 ,
  XED_IFORM_PADDUSB_MMXq_MEMq =1892 ,
  XED_IFORM_PADDUSB_MMXq_MMXq =1893 ,
  XED_IFORM_PADDUSB_XMMdq_MEMdq =1894 ,
  XED_IFORM_PADDUSB_XMMdq_XMMdq =1895 ,
  XED_IFORM_PADDUSW_MMXq_MEMq =1896 ,
  XED_IFORM_PADDUSW_MMXq_MMXq =1897 ,
  XED_IFORM_PADDUSW_XMMdq_MEMdq =1898 ,
  XED_IFORM_PADDUSW_XMMdq_XMMdq =1899 ,
  XED_IFORM_PADDW_MMXq_MEMq =1900 ,
  XED_IFORM_PADDW_MMXq_MMXq =1901 ,
  XED_IFORM_PADDW_XMMdq_MEMdq =1902 ,
  XED_IFORM_PADDW_XMMdq_XMMdq =1903 ,
  XED_IFORM_PALIGNR_MMXq_MEMq_IMMb =1904 ,
  XED_IFORM_PALIGNR_MMXq_MMXq_IMMb =1905 ,
  XED_IFORM_PALIGNR_XMMdq_MEMdq_IMMb =1906 ,
  XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb =1907 ,
  XED_IFORM_PAND_MMXq_MEMq =1908 ,
  XED_IFORM_PAND_MMXq_MMXq =1909 ,
  XED_IFORM_PAND_XMMdq_MEMdq =1910 ,
  XED_IFORM_PAND_XMMdq_XMMdq =1911 ,
  XED_IFORM_PANDN_MMXq_MEMq =1912 ,
  XED_IFORM_PANDN_MMXq_MMXq =1913 ,
  XED_IFORM_PANDN_XMMdq_MEMdq =1914 ,
  XED_IFORM_PANDN_XMMdq_XMMdq =1915 ,
  XED_IFORM_PAUSE =1916 ,
  XED_IFORM_PAVGB_MMXq_MEMq =1917 ,
  XED_IFORM_PAVGB_MMXq_MMXq =1918 ,
  XED_IFORM_PAVGB_XMMdq_MEMdq =1919 ,
  XED_IFORM_PAVGB_XMMdq_XMMdq =1920 ,
  XED_IFORM_PAVGUSB_MMXq_MEMq =1921 ,
  XED_IFORM_PAVGUSB_MMXq_MMXq =1922 ,
  XED_IFORM_PAVGW_MMXq_MEMq =1923 ,
  XED_IFORM_PAVGW_MMXq_MMXq =1924 ,
  XED_IFORM_PAVGW_XMMdq_MEMdq =1925 ,
  XED_IFORM_PAVGW_XMMdq_XMMdq =1926 ,
  XED_IFORM_PBLENDVB_XMMdq_MEMdq =1927 ,
  XED_IFORM_PBLENDVB_XMMdq_XMMdq =1928 ,
  XED_IFORM_PBLENDW_XMMdq_MEMdq_IMMb =1929 ,
  XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb =1930 ,
  XED_IFORM_PBNDKB =1931 ,
  XED_IFORM_PCLMULQDQ_XMMdq_MEMdq_IMMb =1932 ,
  XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb =1933 ,
  XED_IFORM_PCMPEQB_MMXq_MEMq =1934 ,
  XED_IFORM_PCMPEQB_MMXq_MMXq =1935 ,
  XED_IFORM_PCMPEQB_XMMdq_MEMdq =1936 ,
  XED_IFORM_PCMPEQB_XMMdq_XMMdq =1937 ,
  XED_IFORM_PCMPEQD_MMXq_MEMq =1938 ,
  XED_IFORM_PCMPEQD_MMXq_MMXq =1939 ,
  XED_IFORM_PCMPEQD_XMMdq_MEMdq =1940 ,
  XED_IFORM_PCMPEQD_XMMdq_XMMdq =1941 ,
  XED_IFORM_PCMPEQQ_XMMdq_MEMdq =1942 ,
  XED_IFORM_PCMPEQQ_XMMdq_XMMdq =1943 ,
  XED_IFORM_PCMPEQW_MMXq_MEMq =1944 ,
  XED_IFORM_PCMPEQW_MMXq_MMXq =1945 ,
  XED_IFORM_PCMPEQW_XMMdq_MEMdq =1946 ,
  XED_IFORM_PCMPEQW_XMMdq_XMMdq =1947 ,
  XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb =1948 ,
  XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb =1949 ,
  XED_IFORM_PCMPESTRI64_XMMdq_MEMdq_IMMb =1950 ,
  XED_IFORM_PCMPESTRI64_XMMdq_XMMdq_IMMb =1951 ,
  XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb =1952 ,
  XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb =1953 ,
  XED_IFORM_PCMPESTRM64_XMMdq_MEMdq_IMMb =1954 ,
  XED_IFORM_PCMPESTRM64_XMMdq_XMMdq_IMMb =1955 ,
  XED_IFORM_PCMPGTB_MMXq_MEMq =1956 ,
  XED_IFORM_PCMPGTB_MMXq_MMXq =1957 ,
  XED_IFORM_PCMPGTB_XMMdq_MEMdq =1958 ,
  XED_IFORM_PCMPGTB_XMMdq_XMMdq =1959 ,
  XED_IFORM_PCMPGTD_MMXq_MEMq =1960 ,
  XED_IFORM_PCMPGTD_MMXq_MMXq =1961 ,
  XED_IFORM_PCMPGTD_XMMdq_MEMdq =1962 ,
  XED_IFORM_PCMPGTD_XMMdq_XMMdq =1963 ,
  XED_IFORM_PCMPGTQ_XMMdq_MEMdq =1964 ,
  XED_IFORM_PCMPGTQ_XMMdq_XMMdq =1965 ,
  XED_IFORM_PCMPGTW_MMXq_MEMq =1966 ,
  XED_IFORM_PCMPGTW_MMXq_MMXq =1967 ,
  XED_IFORM_PCMPGTW_XMMdq_MEMdq =1968 ,
  XED_IFORM_PCMPGTW_XMMdq_XMMdq =1969 ,
  XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb =1970 ,
  XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb =1971 ,
  XED_IFORM_PCMPISTRI64_XMMdq_MEMdq_IMMb =1972 ,
  XED_IFORM_PCMPISTRI64_XMMdq_XMMdq_IMMb =1973 ,
  XED_IFORM_PCMPISTRM_XMMdq_MEMdq_IMMb =1974 ,
  XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb =1975 ,
  XED_IFORM_PCONFIG =1976 ,
  XED_IFORM_PCONFIG64 =1977 ,
  XED_IFORM_PDEP_GPR32d_GPR32d_GPR32d =1978 ,
  XED_IFORM_PDEP_GPR32d_GPR32d_MEMd =1979 ,
  XED_IFORM_PDEP_GPR32i32_GPR32i32_GPR32i32_APX =1980 ,
  XED_IFORM_PDEP_GPR32i32_GPR32i32_MEMi32_APX =1981 ,
  XED_IFORM_PDEP_GPR64i64_GPR64i64_GPR64i64_APX =1982 ,
  XED_IFORM_PDEP_GPR64i64_GPR64i64_MEMi64_APX =1983 ,
  XED_IFORM_PDEP_GPR64q_GPR64q_GPR64q =1984 ,
  XED_IFORM_PDEP_GPR64q_GPR64q_MEMq =1985 ,
  XED_IFORM_PEXT_GPR32d_GPR32d_GPR32d =1986 ,
  XED_IFORM_PEXT_GPR32d_GPR32d_MEMd =1987 ,
  XED_IFORM_PEXT_GPR32i32_GPR32i32_GPR32i32_APX =1988 ,
  XED_IFORM_PEXT_GPR32i32_GPR32i32_MEMi32_APX =1989 ,
  XED_IFORM_PEXT_GPR64i64_GPR64i64_GPR64i64_APX =1990 ,
  XED_IFORM_PEXT_GPR64i64_GPR64i64_MEMi64_APX =1991 ,
  XED_IFORM_PEXT_GPR64q_GPR64q_GPR64q =1992 ,
  XED_IFORM_PEXT_GPR64q_GPR64q_MEMq =1993 ,
  XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb =1994 ,
  XED_IFORM_PEXTRB_MEMb_XMMdq_IMMb =1995 ,
  XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb =1996 ,
  XED_IFORM_PEXTRD_MEMd_XMMdq_IMMb =1997 ,
  XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb =1998 ,
  XED_IFORM_PEXTRQ_MEMq_XMMdq_IMMb =1999 ,
  XED_IFORM_PEXTRW_GPR32_MMXq_IMMb =2000 ,
  XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb =2001 ,
  XED_IFORM_PEXTRW_SSE4_GPR32_XMMdq_IMMb =2002 ,
  XED_IFORM_PEXTRW_SSE4_MEMw_XMMdq_IMMb =2003 ,
  XED_IFORM_PF2ID_MMXq_MEMq =2004 ,
  XED_IFORM_PF2ID_MMXq_MMXq =2005 ,
  XED_IFORM_PF2IW_MMXq_MEMq =2006 ,
  XED_IFORM_PF2IW_MMXq_MMXq =2007 ,
  XED_IFORM_PFACC_MMXq_MEMq =2008 ,
  XED_IFORM_PFACC_MMXq_MMXq =2009 ,
  XED_IFORM_PFADD_MMXq_MEMq =2010 ,
  XED_IFORM_PFADD_MMXq_MMXq =2011 ,
  XED_IFORM_PFCMPEQ_MMXq_MEMq =2012 ,
  XED_IFORM_PFCMPEQ_MMXq_MMXq =2013 ,
  XED_IFORM_PFCMPGE_MMXq_MEMq =2014 ,
  XED_IFORM_PFCMPGE_MMXq_MMXq =2015 ,
  XED_IFORM_PFCMPGT_MMXq_MEMq =2016 ,
  XED_IFORM_PFCMPGT_MMXq_MMXq =2017 ,
  XED_IFORM_PFMAX_MMXq_MEMq =2018 ,
  XED_IFORM_PFMAX_MMXq_MMXq =2019 ,
  XED_IFORM_PFMIN_MMXq_MEMq =2020 ,
  XED_IFORM_PFMIN_MMXq_MMXq =2021 ,
  XED_IFORM_PFMUL_MMXq_MEMq =2022 ,
  XED_IFORM_PFMUL_MMXq_MMXq =2023 ,
  XED_IFORM_PFNACC_MMXq_MEMq =2024 ,
  XED_IFORM_PFNACC_MMXq_MMXq =2025 ,
  XED_IFORM_PFPNACC_MMXq_MEMq =2026 ,
  XED_IFORM_PFPNACC_MMXq_MMXq =2027 ,
  XED_IFORM_PFRCP_MMXq_MEMq =2028 ,
  XED_IFORM_PFRCP_MMXq_MMXq =2029 ,
  XED_IFORM_PFRCPIT1_MMXq_MEMq =2030 ,
  XED_IFORM_PFRCPIT1_MMXq_MMXq =2031 ,
  XED_IFORM_PFRCPIT2_MMXq_MEMq =2032 ,
  XED_IFORM_PFRCPIT2_MMXq_MMXq =2033 ,
  XED_IFORM_PFRSQIT1_MMXq_MEMq =2034 ,
  XED_IFORM_PFRSQIT1_MMXq_MMXq =2035 ,
  XED_IFORM_PFRSQRT_MMXq_MEMq =2036 ,
  XED_IFORM_PFRSQRT_MMXq_MMXq =2037 ,
  XED_IFORM_PFSUB_MMXq_MEMq =2038 ,
  XED_IFORM_PFSUB_MMXq_MMXq =2039 ,
  XED_IFORM_PFSUBR_MMXq_MEMq =2040 ,
  XED_IFORM_PFSUBR_MMXq_MMXq =2041 ,
  XED_IFORM_PHADDD_MMXq_MEMq =2042 ,
  XED_IFORM_PHADDD_MMXq_MMXq =2043 ,
  XED_IFORM_PHADDD_XMMdq_MEMdq =2044 ,
  XED_IFORM_PHADDD_XMMdq_XMMdq =2045 ,
  XED_IFORM_PHADDSW_MMXq_MEMq =2046 ,
  XED_IFORM_PHADDSW_MMXq_MMXq =2047 ,
  XED_IFORM_PHADDSW_XMMdq_MEMdq =2048 ,
  XED_IFORM_PHADDSW_XMMdq_XMMdq =2049 ,
  XED_IFORM_PHADDW_MMXq_MEMq =2050 ,
  XED_IFORM_PHADDW_MMXq_MMXq =2051 ,
  XED_IFORM_PHADDW_XMMdq_MEMdq =2052 ,
  XED_IFORM_PHADDW_XMMdq_XMMdq =2053 ,
  XED_IFORM_PHMINPOSUW_XMMdq_MEMdq =2054 ,
  XED_IFORM_PHMINPOSUW_XMMdq_XMMdq =2055 ,
  XED_IFORM_PHSUBD_MMXq_MEMq =2056 ,
  XED_IFORM_PHSUBD_MMXq_MMXq =2057 ,
  XED_IFORM_PHSUBD_XMMdq_MEMdq =2058 ,
  XED_IFORM_PHSUBD_XMMdq_XMMdq =2059 ,
  XED_IFORM_PHSUBSW_MMXq_MEMq =2060 ,
  XED_IFORM_PHSUBSW_MMXq_MMXq =2061 ,
  XED_IFORM_PHSUBSW_XMMdq_MEMdq =2062 ,
  XED_IFORM_PHSUBSW_XMMdq_XMMdq =2063 ,
  XED_IFORM_PHSUBW_MMXq_MEMq =2064 ,
  XED_IFORM_PHSUBW_MMXq_MMXq =2065 ,
  XED_IFORM_PHSUBW_XMMdq_MEMdq =2066 ,
  XED_IFORM_PHSUBW_XMMdq_XMMdq =2067 ,
  XED_IFORM_PI2FD_MMXq_MEMq =2068 ,
  XED_IFORM_PI2FD_MMXq_MMXq =2069 ,
  XED_IFORM_PI2FW_MMXq_MEMq =2070 ,
  XED_IFORM_PI2FW_MMXq_MMXq =2071 ,
  XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb =2072 ,
  XED_IFORM_PINSRB_XMMdq_MEMb_IMMb =2073 ,
  XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb =2074 ,
  XED_IFORM_PINSRD_XMMdq_MEMd_IMMb =2075 ,
  XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb =2076 ,
  XED_IFORM_PINSRQ_XMMdq_MEMq_IMMb =2077 ,
  XED_IFORM_PINSRW_MMXq_GPR32_IMMb =2078 ,
  XED_IFORM_PINSRW_MMXq_MEMw_IMMb =2079 ,
  XED_IFORM_PINSRW_XMMdq_GPR32_IMMb =2080 ,
  XED_IFORM_PINSRW_XMMdq_MEMw_IMMb =2081 ,
  XED_IFORM_PMADDUBSW_MMXq_MEMq =2082 ,
  XED_IFORM_PMADDUBSW_MMXq_MMXq =2083 ,
  XED_IFORM_PMADDUBSW_XMMdq_MEMdq =2084 ,
  XED_IFORM_PMADDUBSW_XMMdq_XMMdq =2085 ,
  XED_IFORM_PMADDWD_MMXq_MEMq =2086 ,
  XED_IFORM_PMADDWD_MMXq_MMXq =2087 ,
  XED_IFORM_PMADDWD_XMMdq_MEMdq =2088 ,
  XED_IFORM_PMADDWD_XMMdq_XMMdq =2089 ,
  XED_IFORM_PMAXSB_XMMdq_MEMdq =2090 ,
  XED_IFORM_PMAXSB_XMMdq_XMMdq =2091 ,
  XED_IFORM_PMAXSD_XMMdq_MEMdq =2092 ,
  XED_IFORM_PMAXSD_XMMdq_XMMdq =2093 ,
  XED_IFORM_PMAXSW_MMXq_MEMq =2094 ,
  XED_IFORM_PMAXSW_MMXq_MMXq =2095 ,
  XED_IFORM_PMAXSW_XMMdq_MEMdq =2096 ,
  XED_IFORM_PMAXSW_XMMdq_XMMdq =2097 ,
  XED_IFORM_PMAXUB_MMXq_MEMq =2098 ,
  XED_IFORM_PMAXUB_MMXq_MMXq =2099 ,
  XED_IFORM_PMAXUB_XMMdq_MEMdq =2100 ,
  XED_IFORM_PMAXUB_XMMdq_XMMdq =2101 ,
  XED_IFORM_PMAXUD_XMMdq_MEMdq =2102 ,
  XED_IFORM_PMAXUD_XMMdq_XMMdq =2103 ,
  XED_IFORM_PMAXUW_XMMdq_MEMdq =2104 ,
  XED_IFORM_PMAXUW_XMMdq_XMMdq =2105 ,
  XED_IFORM_PMINSB_XMMdq_MEMdq =2106 ,
  XED_IFORM_PMINSB_XMMdq_XMMdq =2107 ,
  XED_IFORM_PMINSD_XMMdq_MEMdq =2108 ,
  XED_IFORM_PMINSD_XMMdq_XMMdq =2109 ,
  XED_IFORM_PMINSW_MMXq_MEMq =2110 ,
  XED_IFORM_PMINSW_MMXq_MMXq =2111 ,
  XED_IFORM_PMINSW_XMMdq_MEMdq =2112 ,
  XED_IFORM_PMINSW_XMMdq_XMMdq =2113 ,
  XED_IFORM_PMINUB_MMXq_MEMq =2114 ,
  XED_IFORM_PMINUB_MMXq_MMXq =2115 ,
  XED_IFORM_PMINUB_XMMdq_MEMdq =2116 ,
  XED_IFORM_PMINUB_XMMdq_XMMdq =2117 ,
  XED_IFORM_PMINUD_XMMdq_MEMdq =2118 ,
  XED_IFORM_PMINUD_XMMdq_XMMdq =2119 ,
  XED_IFORM_PMINUW_XMMdq_MEMdq =2120 ,
  XED_IFORM_PMINUW_XMMdq_XMMdq =2121 ,
  XED_IFORM_PMOVMSKB_GPR32_MMXq =2122 ,
  XED_IFORM_PMOVMSKB_GPR32_XMMdq =2123 ,
  XED_IFORM_PMOVSXBD_XMMdq_MEMd =2124 ,
  XED_IFORM_PMOVSXBD_XMMdq_XMMd =2125 ,
  XED_IFORM_PMOVSXBQ_XMMdq_MEMw =2126 ,
  XED_IFORM_PMOVSXBQ_XMMdq_XMMw =2127 ,
  XED_IFORM_PMOVSXBW_XMMdq_MEMq =2128 ,
  XED_IFORM_PMOVSXBW_XMMdq_XMMq =2129 ,
  XED_IFORM_PMOVSXDQ_XMMdq_MEMq =2130 ,
  XED_IFORM_PMOVSXDQ_XMMdq_XMMq =2131 ,
  XED_IFORM_PMOVSXWD_XMMdq_MEMq =2132 ,
  XED_IFORM_PMOVSXWD_XMMdq_XMMq =2133 ,
  XED_IFORM_PMOVSXWQ_XMMdq_MEMd =2134 ,
  XED_IFORM_PMOVSXWQ_XMMdq_XMMd =2135 ,
  XED_IFORM_PMOVZXBD_XMMdq_MEMd =2136 ,
  XED_IFORM_PMOVZXBD_XMMdq_XMMd =2137 ,
  XED_IFORM_PMOVZXBQ_XMMdq_MEMw =2138 ,
  XED_IFORM_PMOVZXBQ_XMMdq_XMMw =2139 ,
  XED_IFORM_PMOVZXBW_XMMdq_MEMq =2140 ,
  XED_IFORM_PMOVZXBW_XMMdq_XMMq =2141 ,
  XED_IFORM_PMOVZXDQ_XMMdq_MEMq =2142 ,
  XED_IFORM_PMOVZXDQ_XMMdq_XMMq =2143 ,
  XED_IFORM_PMOVZXWD_XMMdq_MEMq =2144 ,
  XED_IFORM_PMOVZXWD_XMMdq_XMMq =2145 ,
  XED_IFORM_PMOVZXWQ_XMMdq_MEMd =2146 ,
  XED_IFORM_PMOVZXWQ_XMMdq_XMMd =2147 ,
  XED_IFORM_PMULDQ_XMMdq_MEMdq =2148 ,
  XED_IFORM_PMULDQ_XMMdq_XMMdq =2149 ,
  XED_IFORM_PMULHRSW_MMXq_MEMq =2150 ,
  XED_IFORM_PMULHRSW_MMXq_MMXq =2151 ,
  XED_IFORM_PMULHRSW_XMMdq_MEMdq =2152 ,
  XED_IFORM_PMULHRSW_XMMdq_XMMdq =2153 ,
  XED_IFORM_PMULHRW_MMXq_MEMq =2154 ,
  XED_IFORM_PMULHRW_MMXq_MMXq =2155 ,
  XED_IFORM_PMULHUW_MMXq_MEMq =2156 ,
  XED_IFORM_PMULHUW_MMXq_MMXq =2157 ,
  XED_IFORM_PMULHUW_XMMdq_MEMdq =2158 ,
  XED_IFORM_PMULHUW_XMMdq_XMMdq =2159 ,
  XED_IFORM_PMULHW_MMXq_MEMq =2160 ,
  XED_IFORM_PMULHW_MMXq_MMXq =2161 ,
  XED_IFORM_PMULHW_XMMdq_MEMdq =2162 ,
  XED_IFORM_PMULHW_XMMdq_XMMdq =2163 ,
  XED_IFORM_PMULLD_XMMdq_MEMdq =2164 ,
  XED_IFORM_PMULLD_XMMdq_XMMdq =2165 ,
  XED_IFORM_PMULLW_MMXq_MEMq =2166 ,
  XED_IFORM_PMULLW_MMXq_MMXq =2167 ,
  XED_IFORM_PMULLW_XMMdq_MEMdq =2168 ,
  XED_IFORM_PMULLW_XMMdq_XMMdq =2169 ,
  XED_IFORM_PMULUDQ_MMXq_MEMq =2170 ,
  XED_IFORM_PMULUDQ_MMXq_MMXq =2171 ,
  XED_IFORM_PMULUDQ_XMMdq_MEMdq =2172 ,
  XED_IFORM_PMULUDQ_XMMdq_XMMdq =2173 ,
  XED_IFORM_POP_DS =2174 ,
  XED_IFORM_POP_ES =2175 ,
  XED_IFORM_POP_FS =2176 ,
  XED_IFORM_POP_GPRv_58 =2177 ,
  XED_IFORM_POP_GPRv_8F =2178 ,
  XED_IFORM_POP_GS =2179 ,
  XED_IFORM_POP_MEMv =2180 ,
  XED_IFORM_POP_SS =2181 ,
  XED_IFORM_POP2_GPR64u64_GPR64u64_APX =2182 ,
  XED_IFORM_POP2P_GPR64u64_GPR64u64_APX =2183 ,
  XED_IFORM_POPA =2184 ,
  XED_IFORM_POPAD =2185 ,
  XED_IFORM_POPCNT_GPRv_GPRv =2186 ,
  XED_IFORM_POPCNT_GPRv_GPRv_APX =2187 ,
  XED_IFORM_POPCNT_GPRv_MEMv =2188 ,
  XED_IFORM_POPCNT_GPRv_MEMv_APX =2189 ,
  XED_IFORM_POPF =2190 ,
  XED_IFORM_POPFD =2191 ,
  XED_IFORM_POPFQ =2192 ,
  XED_IFORM_POPP_GPR64 =2193 ,
  XED_IFORM_POR_MMXq_MEMq =2194 ,
  XED_IFORM_POR_MMXq_MMXq =2195 ,
  XED_IFORM_POR_XMMdq_MEMdq =2196 ,
  XED_IFORM_POR_XMMdq_XMMdq =2197 ,
  XED_IFORM_PREFETCHIT0_MEMu8 =2198 ,
  XED_IFORM_PREFETCHIT1_MEMu8 =2199 ,
  XED_IFORM_PREFETCHNTA_MEMmprefetch =2200 ,
  XED_IFORM_PREFETCHRST2_MEMu8 =2201 ,
  XED_IFORM_PREFETCHT0_MEMmprefetch =2202 ,
  XED_IFORM_PREFETCHT1_MEMmprefetch =2203 ,
  XED_IFORM_PREFETCHT2_MEMmprefetch =2204 ,
  XED_IFORM_PREFETCHW_0F0Dr1 =2205 ,
  XED_IFORM_PREFETCHW_0F0Dr3 =2206 ,
  XED_IFORM_PREFETCHWT1_MEMu8 =2207 ,
  XED_IFORM_PREFETCH_EXCLUSIVE_MEMmprefetch =2208 ,
  XED_IFORM_PREFETCH_RESERVED_0F0Dr4 =2209 ,
  XED_IFORM_PREFETCH_RESERVED_0F0Dr5 =2210 ,
  XED_IFORM_PREFETCH_RESERVED_0F0Dr6 =2211 ,
  XED_IFORM_PREFETCH_RESERVED_0F0Dr7 =2212 ,
  XED_IFORM_PSADBW_MMXq_MEMq =2213 ,
  XED_IFORM_PSADBW_MMXq_MMXq =2214 ,
  XED_IFORM_PSADBW_XMMdq_MEMdq =2215 ,
  XED_IFORM_PSADBW_XMMdq_XMMdq =2216 ,
  XED_IFORM_PSHUFB_MMXq_MEMq =2217 ,
  XED_IFORM_PSHUFB_MMXq_MMXq =2218 ,
  XED_IFORM_PSHUFB_XMMdq_MEMdq =2219 ,
  XED_IFORM_PSHUFB_XMMdq_XMMdq =2220 ,
  XED_IFORM_PSHUFD_XMMdq_MEMdq_IMMb =2221 ,
  XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb =2222 ,
  XED_IFORM_PSHUFHW_XMMdq_MEMdq_IMMb =2223 ,
  XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb =2224 ,
  XED_IFORM_PSHUFLW_XMMdq_MEMdq_IMMb =2225 ,
  XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb =2226 ,
  XED_IFORM_PSHUFW_MMXq_MEMq_IMMb =2227 ,
  XED_IFORM_PSHUFW_MMXq_MMXq_IMMb =2228 ,
  XED_IFORM_PSIGNB_MMXq_MEMq =2229 ,
  XED_IFORM_PSIGNB_MMXq_MMXq =2230 ,
  XED_IFORM_PSIGNB_XMMdq_MEMdq =2231 ,
  XED_IFORM_PSIGNB_XMMdq_XMMdq =2232 ,
  XED_IFORM_PSIGND_MMXq_MEMq =2233 ,
  XED_IFORM_PSIGND_MMXq_MMXq =2234 ,
  XED_IFORM_PSIGND_XMMdq_MEMdq =2235 ,
  XED_IFORM_PSIGND_XMMdq_XMMdq =2236 ,
  XED_IFORM_PSIGNW_MMXq_MEMq =2237 ,
  XED_IFORM_PSIGNW_MMXq_MMXq =2238 ,
  XED_IFORM_PSIGNW_XMMdq_MEMdq =2239 ,
  XED_IFORM_PSIGNW_XMMdq_XMMdq =2240 ,
  XED_IFORM_PSLLD_MMXq_IMMb =2241 ,
  XED_IFORM_PSLLD_MMXq_MEMq =2242 ,
  XED_IFORM_PSLLD_MMXq_MMXq =2243 ,
  XED_IFORM_PSLLD_XMMdq_IMMb =2244 ,
  XED_IFORM_PSLLD_XMMdq_MEMdq =2245 ,
  XED_IFORM_PSLLD_XMMdq_XMMdq =2246 ,
  XED_IFORM_PSLLDQ_XMMdq_IMMb =2247 ,
  XED_IFORM_PSLLQ_MMXq_IMMb =2248 ,
  XED_IFORM_PSLLQ_MMXq_MEMq =2249 ,
  XED_IFORM_PSLLQ_MMXq_MMXq =2250 ,
  XED_IFORM_PSLLQ_XMMdq_IMMb =2251 ,
  XED_IFORM_PSLLQ_XMMdq_MEMdq =2252 ,
  XED_IFORM_PSLLQ_XMMdq_XMMdq =2253 ,
  XED_IFORM_PSLLW_MMXq_IMMb =2254 ,
  XED_IFORM_PSLLW_MMXq_MEMq =2255 ,
  XED_IFORM_PSLLW_MMXq_MMXq =2256 ,
  XED_IFORM_PSLLW_XMMdq_IMMb =2257 ,
  XED_IFORM_PSLLW_XMMdq_MEMdq =2258 ,
  XED_IFORM_PSLLW_XMMdq_XMMdq =2259 ,
  XED_IFORM_PSMASH_RAX =2260 ,
  XED_IFORM_PSRAD_MMXq_IMMb =2261 ,
  XED_IFORM_PSRAD_MMXq_MEMq =2262 ,
  XED_IFORM_PSRAD_MMXq_MMXq =2263 ,
  XED_IFORM_PSRAD_XMMdq_IMMb =2264 ,
  XED_IFORM_PSRAD_XMMdq_MEMdq =2265 ,
  XED_IFORM_PSRAD_XMMdq_XMMdq =2266 ,
  XED_IFORM_PSRAW_MMXq_IMMb =2267 ,
  XED_IFORM_PSRAW_MMXq_MEMq =2268 ,
  XED_IFORM_PSRAW_MMXq_MMXq =2269 ,
  XED_IFORM_PSRAW_XMMdq_IMMb =2270 ,
  XED_IFORM_PSRAW_XMMdq_MEMdq =2271 ,
  XED_IFORM_PSRAW_XMMdq_XMMdq =2272 ,
  XED_IFORM_PSRLD_MMXq_IMMb =2273 ,
  XED_IFORM_PSRLD_MMXq_MEMq =2274 ,
  XED_IFORM_PSRLD_MMXq_MMXq =2275 ,
  XED_IFORM_PSRLD_XMMdq_IMMb =2276 ,
  XED_IFORM_PSRLD_XMMdq_MEMdq =2277 ,
  XED_IFORM_PSRLD_XMMdq_XMMdq =2278 ,
  XED_IFORM_PSRLDQ_XMMdq_IMMb =2279 ,
  XED_IFORM_PSRLQ_MMXq_IMMb =2280 ,
  XED_IFORM_PSRLQ_MMXq_MEMq =2281 ,
  XED_IFORM_PSRLQ_MMXq_MMXq =2282 ,
  XED_IFORM_PSRLQ_XMMdq_IMMb =2283 ,
  XED_IFORM_PSRLQ_XMMdq_MEMdq =2284 ,
  XED_IFORM_PSRLQ_XMMdq_XMMdq =2285 ,
  XED_IFORM_PSRLW_MMXq_IMMb =2286 ,
  XED_IFORM_PSRLW_MMXq_MEMq =2287 ,
  XED_IFORM_PSRLW_MMXq_MMXq =2288 ,
  XED_IFORM_PSRLW_XMMdq_IMMb =2289 ,
  XED_IFORM_PSRLW_XMMdq_MEMdq =2290 ,
  XED_IFORM_PSRLW_XMMdq_XMMdq =2291 ,
  XED_IFORM_PSUBB_MMXq_MEMq =2292 ,
  XED_IFORM_PSUBB_MMXq_MMXq =2293 ,
  XED_IFORM_PSUBB_XMMdq_MEMdq =2294 ,
  XED_IFORM_PSUBB_XMMdq_XMMdq =2295 ,
  XED_IFORM_PSUBD_MMXq_MEMq =2296 ,
  XED_IFORM_PSUBD_MMXq_MMXq =2297 ,
  XED_IFORM_PSUBD_XMMdq_MEMdq =2298 ,
  XED_IFORM_PSUBD_XMMdq_XMMdq =2299 ,
  XED_IFORM_PSUBQ_MMXq_MEMq =2300 ,
  XED_IFORM_PSUBQ_MMXq_MMXq =2301 ,
  XED_IFORM_PSUBQ_XMMdq_MEMdq =2302 ,
  XED_IFORM_PSUBQ_XMMdq_XMMdq =2303 ,
  XED_IFORM_PSUBSB_MMXq_MEMq =2304 ,
  XED_IFORM_PSUBSB_MMXq_MMXq =2305 ,
  XED_IFORM_PSUBSB_XMMdq_MEMdq =2306 ,
  XED_IFORM_PSUBSB_XMMdq_XMMdq =2307 ,
  XED_IFORM_PSUBSW_MMXq_MEMq =2308 ,
  XED_IFORM_PSUBSW_MMXq_MMXq =2309 ,
  XED_IFORM_PSUBSW_XMMdq_MEMdq =2310 ,
  XED_IFORM_PSUBSW_XMMdq_XMMdq =2311 ,
  XED_IFORM_PSUBUSB_MMXq_MEMq =2312 ,
  XED_IFORM_PSUBUSB_MMXq_MMXq =2313 ,
  XED_IFORM_PSUBUSB_XMMdq_MEMdq =2314 ,
  XED_IFORM_PSUBUSB_XMMdq_XMMdq =2315 ,
  XED_IFORM_PSUBUSW_MMXq_MEMq =2316 ,
  XED_IFORM_PSUBUSW_MMXq_MMXq =2317 ,
  XED_IFORM_PSUBUSW_XMMdq_MEMdq =2318 ,
  XED_IFORM_PSUBUSW_XMMdq_XMMdq =2319 ,
  XED_IFORM_PSUBW_MMXq_MEMq =2320 ,
  XED_IFORM_PSUBW_MMXq_MMXq =2321 ,
  XED_IFORM_PSUBW_XMMdq_MEMdq =2322 ,
  XED_IFORM_PSUBW_XMMdq_XMMdq =2323 ,
  XED_IFORM_PSWAPD_MMXq_MEMq =2324 ,
  XED_IFORM_PSWAPD_MMXq_MMXq =2325 ,
  XED_IFORM_PTEST_XMMdq_MEMdq =2326 ,
  XED_IFORM_PTEST_XMMdq_XMMdq =2327 ,
  XED_IFORM_PTWRITE_GPRy =2328 ,
  XED_IFORM_PTWRITE_MEMy =2329 ,
  XED_IFORM_PUNPCKHBW_MMXq_MEMq =2330 ,
  XED_IFORM_PUNPCKHBW_MMXq_MMXd =2331 ,
  XED_IFORM_PUNPCKHBW_XMMdq_MEMdq =2332 ,
  XED_IFORM_PUNPCKHBW_XMMdq_XMMq =2333 ,
  XED_IFORM_PUNPCKHDQ_MMXq_MEMq =2334 ,
  XED_IFORM_PUNPCKHDQ_MMXq_MMXd =2335 ,
  XED_IFORM_PUNPCKHDQ_XMMdq_MEMdq =2336 ,
  XED_IFORM_PUNPCKHDQ_XMMdq_XMMq =2337 ,
  XED_IFORM_PUNPCKHQDQ_XMMdq_MEMdq =2338 ,
  XED_IFORM_PUNPCKHQDQ_XMMdq_XMMq =2339 ,
  XED_IFORM_PUNPCKHWD_MMXq_MEMq =2340 ,
  XED_IFORM_PUNPCKHWD_MMXq_MMXd =2341 ,
  XED_IFORM_PUNPCKHWD_XMMdq_MEMdq =2342 ,
  XED_IFORM_PUNPCKHWD_XMMdq_XMMq =2343 ,
  XED_IFORM_PUNPCKLBW_MMXq_MEMd =2344 ,
  XED_IFORM_PUNPCKLBW_MMXq_MMXd =2345 ,
  XED_IFORM_PUNPCKLBW_XMMdq_MEMdq =2346 ,
  XED_IFORM_PUNPCKLBW_XMMdq_XMMq =2347 ,
  XED_IFORM_PUNPCKLDQ_MMXq_MEMd =2348 ,
  XED_IFORM_PUNPCKLDQ_MMXq_MMXd =2349 ,
  XED_IFORM_PUNPCKLDQ_XMMdq_MEMdq =2350 ,
  XED_IFORM_PUNPCKLDQ_XMMdq_XMMq =2351 ,
  XED_IFORM_PUNPCKLQDQ_XMMdq_MEMdq =2352 ,
  XED_IFORM_PUNPCKLQDQ_XMMdq_XMMq =2353 ,
  XED_IFORM_PUNPCKLWD_MMXq_MEMd =2354 ,
  XED_IFORM_PUNPCKLWD_MMXq_MMXd =2355 ,
  XED_IFORM_PUNPCKLWD_XMMdq_MEMdq =2356 ,
  XED_IFORM_PUNPCKLWD_XMMdq_XMMq =2357 ,
  XED_IFORM_PUSH_CS =2358 ,
  XED_IFORM_PUSH_DS =2359 ,
  XED_IFORM_PUSH_ES =2360 ,
  XED_IFORM_PUSH_FS =2361 ,
  XED_IFORM_PUSH_GPRv_50 =2362 ,
  XED_IFORM_PUSH_GPRv_FFr6 =2363 ,
  XED_IFORM_PUSH_GS =2364 ,
  XED_IFORM_PUSH_IMMb =2365 ,
  XED_IFORM_PUSH_IMMz =2366 ,
  XED_IFORM_PUSH_MEMv =2367 ,
  XED_IFORM_PUSH_SS =2368 ,
  XED_IFORM_PUSH2_GPR64u64_GPR64u64_APX =2369 ,
  XED_IFORM_PUSH2P_GPR64u64_GPR64u64_APX =2370 ,
  XED_IFORM_PUSHA =2371 ,
  XED_IFORM_PUSHAD =2372 ,
  XED_IFORM_PUSHF =2373 ,
  XED_IFORM_PUSHFD =2374 ,
  XED_IFORM_PUSHFQ =2375 ,
  XED_IFORM_PUSHP_GPR64 =2376 ,
  XED_IFORM_PVALIDATE_RAX_ECX_EDX =2377 ,
  XED_IFORM_PXOR_MMXq_MEMq =2378 ,
  XED_IFORM_PXOR_MMXq_MMXq =2379 ,
  XED_IFORM_PXOR_XMMdq_MEMdq =2380 ,
  XED_IFORM_PXOR_XMMdq_XMMdq =2381 ,
  XED_IFORM_RCL_GPR8_CL =2382 ,
  XED_IFORM_RCL_GPR8_IMMb =2383 ,
  XED_IFORM_RCL_GPR8_ONE =2384 ,
  XED_IFORM_RCL_GPR8i8_CL_APX =2385 ,
  XED_IFORM_RCL_GPR8i8_GPR8i8_CL_APX =2386 ,
  XED_IFORM_RCL_GPR8i8_GPR8i8_IMM8_APX =2387 ,
  XED_IFORM_RCL_GPR8i8_GPR8i8_ONE_APX =2388 ,
  XED_IFORM_RCL_GPR8i8_IMM8_APX =2389 ,
  XED_IFORM_RCL_GPR8i8_MEMi8_CL_APX =2390 ,
  XED_IFORM_RCL_GPR8i8_MEMi8_IMM8_APX =2391 ,
  XED_IFORM_RCL_GPR8i8_MEMi8_ONE_APX =2392 ,
  XED_IFORM_RCL_GPR8i8_ONE_APX =2393 ,
  XED_IFORM_RCL_GPRv_CL =2394 ,
  XED_IFORM_RCL_GPRv_CL_APX =2395 ,
  XED_IFORM_RCL_GPRv_GPRv_CL_APX =2396 ,
  XED_IFORM_RCL_GPRv_GPRv_IMM8_APX =2397 ,
  XED_IFORM_RCL_GPRv_GPRv_ONE_APX =2398 ,
  XED_IFORM_RCL_GPRv_IMM8_APX =2399 ,
  XED_IFORM_RCL_GPRv_IMMb =2400 ,
  XED_IFORM_RCL_GPRv_MEMv_CL_APX =2401 ,
  XED_IFORM_RCL_GPRv_MEMv_IMM8_APX =2402 ,
  XED_IFORM_RCL_GPRv_MEMv_ONE_APX =2403 ,
  XED_IFORM_RCL_GPRv_ONE =2404 ,
  XED_IFORM_RCL_GPRv_ONE_APX =2405 ,
  XED_IFORM_RCL_MEMb_CL =2406 ,
  XED_IFORM_RCL_MEMb_IMMb =2407 ,
  XED_IFORM_RCL_MEMb_ONE =2408 ,
  XED_IFORM_RCL_MEMi8_CL_APX =2409 ,
  XED_IFORM_RCL_MEMi8_IMM8_APX =2410 ,
  XED_IFORM_RCL_MEMi8_ONE_APX =2411 ,
  XED_IFORM_RCL_MEMv_CL =2412 ,
  XED_IFORM_RCL_MEMv_CL_APX =2413 ,
  XED_IFORM_RCL_MEMv_IMM8_APX =2414 ,
  XED_IFORM_RCL_MEMv_IMMb =2415 ,
  XED_IFORM_RCL_MEMv_ONE =2416 ,
  XED_IFORM_RCL_MEMv_ONE_APX =2417 ,
  XED_IFORM_RCPPS_XMMps_MEMps =2418 ,
  XED_IFORM_RCPPS_XMMps_XMMps =2419 ,
  XED_IFORM_RCPSS_XMMss_MEMss =2420 ,
  XED_IFORM_RCPSS_XMMss_XMMss =2421 ,
  XED_IFORM_RCR_GPR8_CL =2422 ,
  XED_IFORM_RCR_GPR8_IMMb =2423 ,
  XED_IFORM_RCR_GPR8_ONE =2424 ,
  XED_IFORM_RCR_GPR8i8_CL_APX =2425 ,
  XED_IFORM_RCR_GPR8i8_GPR8i8_CL_APX =2426 ,
  XED_IFORM_RCR_GPR8i8_GPR8i8_IMM8_APX =2427 ,
  XED_IFORM_RCR_GPR8i8_GPR8i8_ONE_APX =2428 ,
  XED_IFORM_RCR_GPR8i8_IMM8_APX =2429 ,
  XED_IFORM_RCR_GPR8i8_MEMi8_CL_APX =2430 ,
  XED_IFORM_RCR_GPR8i8_MEMi8_IMM8_APX =2431 ,
  XED_IFORM_RCR_GPR8i8_MEMi8_ONE_APX =2432 ,
  XED_IFORM_RCR_GPR8i8_ONE_APX =2433 ,
  XED_IFORM_RCR_GPRv_CL =2434 ,
  XED_IFORM_RCR_GPRv_CL_APX =2435 ,
  XED_IFORM_RCR_GPRv_GPRv_CL_APX =2436 ,
  XED_IFORM_RCR_GPRv_GPRv_IMM8_APX =2437 ,
  XED_IFORM_RCR_GPRv_GPRv_ONE_APX =2438 ,
  XED_IFORM_RCR_GPRv_IMM8_APX =2439 ,
  XED_IFORM_RCR_GPRv_IMMb =2440 ,
  XED_IFORM_RCR_GPRv_MEMv_CL_APX =2441 ,
  XED_IFORM_RCR_GPRv_MEMv_IMM8_APX =2442 ,
  XED_IFORM_RCR_GPRv_MEMv_ONE_APX =2443 ,
  XED_IFORM_RCR_GPRv_ONE =2444 ,
  XED_IFORM_RCR_GPRv_ONE_APX =2445 ,
  XED_IFORM_RCR_MEMb_CL =2446 ,
  XED_IFORM_RCR_MEMb_IMMb =2447 ,
  XED_IFORM_RCR_MEMb_ONE =2448 ,
  XED_IFORM_RCR_MEMi8_CL_APX =2449 ,
  XED_IFORM_RCR_MEMi8_IMM8_APX =2450 ,
  XED_IFORM_RCR_MEMi8_ONE_APX =2451 ,
  XED_IFORM_RCR_MEMv_CL =2452 ,
  XED_IFORM_RCR_MEMv_CL_APX =2453 ,
  XED_IFORM_RCR_MEMv_IMM8_APX =2454 ,
  XED_IFORM_RCR_MEMv_IMMb =2455 ,
  XED_IFORM_RCR_MEMv_ONE =2456 ,
  XED_IFORM_RCR_MEMv_ONE_APX =2457 ,
  XED_IFORM_RDFSBASE_GPRy =2458 ,
  XED_IFORM_RDGSBASE_GPRy =2459 ,
  XED_IFORM_RDMSR =2460 ,
  XED_IFORM_RDMSR_GPR64u64_IMM32 =2461 ,
  XED_IFORM_RDMSR_GPR64u64_IMM32_APX =2462 ,
  XED_IFORM_RDMSRLIST =2463 ,
  XED_IFORM_RDPID_GPR32u32 =2464 ,
  XED_IFORM_RDPID_GPR64u64 =2465 ,
  XED_IFORM_RDPKRU =2466 ,
  XED_IFORM_RDPMC =2467 ,
  XED_IFORM_RDPRU =2468 ,
  XED_IFORM_RDRAND_GPRv =2469 ,
  XED_IFORM_RDSEED_GPRv =2470 ,
  XED_IFORM_RDSSPD_GPR32u32 =2471 ,
  XED_IFORM_RDSSPQ_GPR64u64 =2472 ,
  XED_IFORM_RDTSC =2473 ,
  XED_IFORM_RDTSCP =2474 ,
  XED_IFORM_REPE_CMPSB =2475 ,
  XED_IFORM_REPE_CMPSD =2476 ,
  XED_IFORM_REPE_CMPSQ =2477 ,
  XED_IFORM_REPE_CMPSW =2478 ,
  XED_IFORM_REPE_SCASB =2479 ,
  XED_IFORM_REPE_SCASD =2480 ,
  XED_IFORM_REPE_SCASQ =2481 ,
  XED_IFORM_REPE_SCASW =2482 ,
  XED_IFORM_REPNE_CMPSB =2483 ,
  XED_IFORM_REPNE_CMPSD =2484 ,
  XED_IFORM_REPNE_CMPSQ =2485 ,
  XED_IFORM_REPNE_CMPSW =2486 ,
  XED_IFORM_REPNE_SCASB =2487 ,
  XED_IFORM_REPNE_SCASD =2488 ,
  XED_IFORM_REPNE_SCASQ =2489 ,
  XED_IFORM_REPNE_SCASW =2490 ,
  XED_IFORM_REP_INSB =2491 ,
  XED_IFORM_REP_INSD =2492 ,
  XED_IFORM_REP_INSW =2493 ,
  XED_IFORM_REP_LODSB =2494 ,
  XED_IFORM_REP_LODSD =2495 ,
  XED_IFORM_REP_LODSQ =2496 ,
  XED_IFORM_REP_LODSW =2497 ,
  XED_IFORM_REP_MONTMUL =2498 ,
  XED_IFORM_REP_MOVSB =2499 ,
  XED_IFORM_REP_MOVSD =2500 ,
  XED_IFORM_REP_MOVSQ =2501 ,
  XED_IFORM_REP_MOVSW =2502 ,
  XED_IFORM_REP_OUTSB =2503 ,
  XED_IFORM_REP_OUTSD =2504 ,
  XED_IFORM_REP_OUTSW =2505 ,
  XED_IFORM_REP_STOSB =2506 ,
  XED_IFORM_REP_STOSD =2507 ,
  XED_IFORM_REP_STOSQ =2508 ,
  XED_IFORM_REP_STOSW =2509 ,
  XED_IFORM_REP_XCRYPTCBC =2510 ,
  XED_IFORM_REP_XCRYPTCFB =2511 ,
  XED_IFORM_REP_XCRYPTCTR =2512 ,
  XED_IFORM_REP_XCRYPTECB =2513 ,
  XED_IFORM_REP_XCRYPTOFB =2514 ,
  XED_IFORM_REP_XSHA1 =2515 ,
  XED_IFORM_REP_XSHA256 =2516 ,
  XED_IFORM_REP_XSTORE =2517 ,
  XED_IFORM_RET_FAR =2518 ,
  XED_IFORM_RET_FAR_IMMw =2519 ,
  XED_IFORM_RET_NEAR =2520 ,
  XED_IFORM_RET_NEAR_IMMw =2521 ,
  XED_IFORM_RMPADJUST_RAX_RCX_RDX =2522 ,
  XED_IFORM_RMPUPDATE_RAX_RCX =2523 ,
  XED_IFORM_ROL_GPR8_CL =2524 ,
  XED_IFORM_ROL_GPR8_IMMb =2525 ,
  XED_IFORM_ROL_GPR8_ONE =2526 ,
  XED_IFORM_ROL_GPR8i8_CL_APX =2527 ,
  XED_IFORM_ROL_GPR8i8_GPR8i8_CL_APX =2528 ,
  XED_IFORM_ROL_GPR8i8_GPR8i8_IMM8_APX =2529 ,
  XED_IFORM_ROL_GPR8i8_GPR8i8_ONE_APX =2530 ,
  XED_IFORM_ROL_GPR8i8_IMM8_APX =2531 ,
  XED_IFORM_ROL_GPR8i8_MEMi8_CL_APX =2532 ,
  XED_IFORM_ROL_GPR8i8_MEMi8_IMM8_APX =2533 ,
  XED_IFORM_ROL_GPR8i8_MEMi8_ONE_APX =2534 ,
  XED_IFORM_ROL_GPR8i8_ONE_APX =2535 ,
  XED_IFORM_ROL_GPRv_CL =2536 ,
  XED_IFORM_ROL_GPRv_CL_APX =2537 ,
  XED_IFORM_ROL_GPRv_GPRv_CL_APX =2538 ,
  XED_IFORM_ROL_GPRv_GPRv_IMM8_APX =2539 ,
  XED_IFORM_ROL_GPRv_GPRv_ONE_APX =2540 ,
  XED_IFORM_ROL_GPRv_IMM8_APX =2541 ,
  XED_IFORM_ROL_GPRv_IMMb =2542 ,
  XED_IFORM_ROL_GPRv_MEMv_CL_APX =2543 ,
  XED_IFORM_ROL_GPRv_MEMv_IMM8_APX =2544 ,
  XED_IFORM_ROL_GPRv_MEMv_ONE_APX =2545 ,
  XED_IFORM_ROL_GPRv_ONE =2546 ,
  XED_IFORM_ROL_GPRv_ONE_APX =2547 ,
  XED_IFORM_ROL_MEMb_CL =2548 ,
  XED_IFORM_ROL_MEMb_IMMb =2549 ,
  XED_IFORM_ROL_MEMb_ONE =2550 ,
  XED_IFORM_ROL_MEMi8_CL_APX =2551 ,
  XED_IFORM_ROL_MEMi8_IMM8_APX =2552 ,
  XED_IFORM_ROL_MEMi8_ONE_APX =2553 ,
  XED_IFORM_ROL_MEMv_CL =2554 ,
  XED_IFORM_ROL_MEMv_CL_APX =2555 ,
  XED_IFORM_ROL_MEMv_IMM8_APX =2556 ,
  XED_IFORM_ROL_MEMv_IMMb =2557 ,
  XED_IFORM_ROL_MEMv_ONE =2558 ,
  XED_IFORM_ROL_MEMv_ONE_APX =2559 ,
  XED_IFORM_ROR_GPR8_CL =2560 ,
  XED_IFORM_ROR_GPR8_IMMb =2561 ,
  XED_IFORM_ROR_GPR8_ONE =2562 ,
  XED_IFORM_ROR_GPR8i8_CL_APX =2563 ,
  XED_IFORM_ROR_GPR8i8_GPR8i8_CL_APX =2564 ,
  XED_IFORM_ROR_GPR8i8_GPR8i8_IMM8_APX =2565 ,
  XED_IFORM_ROR_GPR8i8_GPR8i8_ONE_APX =2566 ,
  XED_IFORM_ROR_GPR8i8_IMM8_APX =2567 ,
  XED_IFORM_ROR_GPR8i8_MEMi8_CL_APX =2568 ,
  XED_IFORM_ROR_GPR8i8_MEMi8_IMM8_APX =2569 ,
  XED_IFORM_ROR_GPR8i8_MEMi8_ONE_APX =2570 ,
  XED_IFORM_ROR_GPR8i8_ONE_APX =2571 ,
  XED_IFORM_ROR_GPRv_CL =2572 ,
  XED_IFORM_ROR_GPRv_CL_APX =2573 ,
  XED_IFORM_ROR_GPRv_GPRv_CL_APX =2574 ,
  XED_IFORM_ROR_GPRv_GPRv_IMM8_APX =2575 ,
  XED_IFORM_ROR_GPRv_GPRv_ONE_APX =2576 ,
  XED_IFORM_ROR_GPRv_IMM8_APX =2577 ,
  XED_IFORM_ROR_GPRv_IMMb =2578 ,
  XED_IFORM_ROR_GPRv_MEMv_CL_APX =2579 ,
  XED_IFORM_ROR_GPRv_MEMv_IMM8_APX =2580 ,
  XED_IFORM_ROR_GPRv_MEMv_ONE_APX =2581 ,
  XED_IFORM_ROR_GPRv_ONE =2582 ,
  XED_IFORM_ROR_GPRv_ONE_APX =2583 ,
  XED_IFORM_ROR_MEMb_CL =2584 ,
  XED_IFORM_ROR_MEMb_IMMb =2585 ,
  XED_IFORM_ROR_MEMb_ONE =2586 ,
  XED_IFORM_ROR_MEMi8_CL_APX =2587 ,
  XED_IFORM_ROR_MEMi8_IMM8_APX =2588 ,
  XED_IFORM_ROR_MEMi8_ONE_APX =2589 ,
  XED_IFORM_ROR_MEMv_CL =2590 ,
  XED_IFORM_ROR_MEMv_CL_APX =2591 ,
  XED_IFORM_ROR_MEMv_IMM8_APX =2592 ,
  XED_IFORM_ROR_MEMv_IMMb =2593 ,
  XED_IFORM_ROR_MEMv_ONE =2594 ,
  XED_IFORM_ROR_MEMv_ONE_APX =2595 ,
  XED_IFORM_RORX_GPR32d_GPR32d_IMMb =2596 ,
  XED_IFORM_RORX_GPR32d_MEMd_IMMb =2597 ,
  XED_IFORM_RORX_GPR32i32_GPR32i32_IMM8_APX =2598 ,
  XED_IFORM_RORX_GPR32i32_MEMi32_IMM8_APX =2599 ,
  XED_IFORM_RORX_GPR64i64_GPR64i64_IMM8_APX =2600 ,
  XED_IFORM_RORX_GPR64i64_MEMi64_IMM8_APX =2601 ,
  XED_IFORM_RORX_GPR64q_GPR64q_IMMb =2602 ,
  XED_IFORM_RORX_GPR64q_MEMq_IMMb =2603 ,
  XED_IFORM_ROUNDPD_XMMpd_MEMpd_IMMb =2604 ,
  XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb =2605 ,
  XED_IFORM_ROUNDPS_XMMps_MEMps_IMMb =2606 ,
  XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb =2607 ,
  XED_IFORM_ROUNDSD_XMMq_MEMq_IMMb =2608 ,
  XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb =2609 ,
  XED_IFORM_ROUNDSS_XMMd_MEMd_IMMb =2610 ,
  XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb =2611 ,
  XED_IFORM_RSM =2612 ,
  XED_IFORM_RSQRTPS_XMMps_MEMps =2613 ,
  XED_IFORM_RSQRTPS_XMMps_XMMps =2614 ,
  XED_IFORM_RSQRTSS_XMMss_MEMss =2615 ,
  XED_IFORM_RSQRTSS_XMMss_XMMss =2616 ,
  XED_IFORM_RSTORSSP_MEMu64 =2617 ,
  XED_IFORM_SAHF =2618 ,
  XED_IFORM_SALC =2619 ,
  XED_IFORM_SAR_GPR8_CL =2620 ,
  XED_IFORM_SAR_GPR8_IMMb =2621 ,
  XED_IFORM_SAR_GPR8_ONE =2622 ,
  XED_IFORM_SAR_GPR8i8_CL_APX =2623 ,
  XED_IFORM_SAR_GPR8i8_GPR8i8_CL_APX =2624 ,
  XED_IFORM_SAR_GPR8i8_GPR8i8_IMM8_APX =2625 ,
  XED_IFORM_SAR_GPR8i8_GPR8i8_ONE_APX =2626 ,
  XED_IFORM_SAR_GPR8i8_IMM8_APX =2627 ,
  XED_IFORM_SAR_GPR8i8_MEMi8_CL_APX =2628 ,
  XED_IFORM_SAR_GPR8i8_MEMi8_IMM8_APX =2629 ,
  XED_IFORM_SAR_GPR8i8_MEMi8_ONE_APX =2630 ,
  XED_IFORM_SAR_GPR8i8_ONE_APX =2631 ,
  XED_IFORM_SAR_GPRv_CL =2632 ,
  XED_IFORM_SAR_GPRv_CL_APX =2633 ,
  XED_IFORM_SAR_GPRv_GPRv_CL_APX =2634 ,
  XED_IFORM_SAR_GPRv_GPRv_IMM8_APX =2635 ,
  XED_IFORM_SAR_GPRv_GPRv_ONE_APX =2636 ,
  XED_IFORM_SAR_GPRv_IMM8_APX =2637 ,
  XED_IFORM_SAR_GPRv_IMMb =2638 ,
  XED_IFORM_SAR_GPRv_MEMv_CL_APX =2639 ,
  XED_IFORM_SAR_GPRv_MEMv_IMM8_APX =2640 ,
  XED_IFORM_SAR_GPRv_MEMv_ONE_APX =2641 ,
  XED_IFORM_SAR_GPRv_ONE =2642 ,
  XED_IFORM_SAR_GPRv_ONE_APX =2643 ,
  XED_IFORM_SAR_MEMb_CL =2644 ,
  XED_IFORM_SAR_MEMb_IMMb =2645 ,
  XED_IFORM_SAR_MEMb_ONE =2646 ,
  XED_IFORM_SAR_MEMi8_CL_APX =2647 ,
  XED_IFORM_SAR_MEMi8_IMM8_APX =2648 ,
  XED_IFORM_SAR_MEMi8_ONE_APX =2649 ,
  XED_IFORM_SAR_MEMv_CL =2650 ,
  XED_IFORM_SAR_MEMv_CL_APX =2651 ,
  XED_IFORM_SAR_MEMv_IMM8_APX =2652 ,
  XED_IFORM_SAR_MEMv_IMMb =2653 ,
  XED_IFORM_SAR_MEMv_ONE =2654 ,
  XED_IFORM_SAR_MEMv_ONE_APX =2655 ,
  XED_IFORM_SARX_GPR32d_GPR32d_GPR32d =2656 ,
  XED_IFORM_SARX_GPR32d_MEMd_GPR32d =2657 ,
  XED_IFORM_SARX_GPR32i32_GPR32i32_GPR32i32_APX =2658 ,
  XED_IFORM_SARX_GPR32i32_MEMi32_GPR32i32_APX =2659 ,
  XED_IFORM_SARX_GPR64i64_GPR64i64_GPR64i64_APX =2660 ,
  XED_IFORM_SARX_GPR64i64_MEMi64_GPR64i64_APX =2661 ,
  XED_IFORM_SARX_GPR64q_GPR64q_GPR64q =2662 ,
  XED_IFORM_SARX_GPR64q_MEMq_GPR64q =2663 ,
  XED_IFORM_SAVEPREVSSP =2664 ,
  XED_IFORM_SBB_AL_IMMb =2665 ,
  XED_IFORM_SBB_GPR8_GPR8_18 =2666 ,
  XED_IFORM_SBB_GPR8_GPR8_1A =2667 ,
  XED_IFORM_SBB_GPR8_IMMb_80r3 =2668 ,
  XED_IFORM_SBB_GPR8_IMMb_82r3 =2669 ,
  XED_IFORM_SBB_GPR8_MEMb =2670 ,
  XED_IFORM_SBB_GPR8i8_GPR8i8_APX =2671 ,
  XED_IFORM_SBB_GPR8i8_GPR8i8_GPR8i8_APX =2672 ,
  XED_IFORM_SBB_GPR8i8_GPR8i8_IMM8_APX =2673 ,
  XED_IFORM_SBB_GPR8i8_GPR8i8_MEMi8_APX =2674 ,
  XED_IFORM_SBB_GPR8i8_IMM8_APX =2675 ,
  XED_IFORM_SBB_GPR8i8_MEMi8_APX =2676 ,
  XED_IFORM_SBB_GPR8i8_MEMi8_GPR8i8_APX =2677 ,
  XED_IFORM_SBB_GPR8i8_MEMi8_IMM8_APX =2678 ,
  XED_IFORM_SBB_GPRv_GPRv_19 =2679 ,
  XED_IFORM_SBB_GPRv_GPRv_1B =2680 ,
  XED_IFORM_SBB_GPRv_GPRv_APX =2681 ,
  XED_IFORM_SBB_GPRv_GPRv_GPRv_APX =2682 ,
  XED_IFORM_SBB_GPRv_GPRv_IMM8_APX =2683 ,
  XED_IFORM_SBB_GPRv_GPRv_IMMz_APX =2684 ,
  XED_IFORM_SBB_GPRv_GPRv_MEMv_APX =2685 ,
  XED_IFORM_SBB_GPRv_IMM8_APX =2686 ,
  XED_IFORM_SBB_GPRv_IMMb =2687 ,
  XED_IFORM_SBB_GPRv_IMMz =2688 ,
  XED_IFORM_SBB_GPRv_IMMz_APX =2689 ,
  XED_IFORM_SBB_GPRv_MEMv =2690 ,
  XED_IFORM_SBB_GPRv_MEMv_APX =2691 ,
  XED_IFORM_SBB_GPRv_MEMv_GPRv_APX =2692 ,
  XED_IFORM_SBB_GPRv_MEMv_IMM8_APX =2693 ,
  XED_IFORM_SBB_GPRv_MEMv_IMMz_APX =2694 ,
  XED_IFORM_SBB_MEMb_GPR8 =2695 ,
  XED_IFORM_SBB_MEMb_IMMb_80r3 =2696 ,
  XED_IFORM_SBB_MEMb_IMMb_82r3 =2697 ,
  XED_IFORM_SBB_MEMi8_GPR8i8_APX =2698 ,
  XED_IFORM_SBB_MEMi8_IMM8_APX =2699 ,
  XED_IFORM_SBB_MEMv_GPRv =2700 ,
  XED_IFORM_SBB_MEMv_GPRv_APX =2701 ,
  XED_IFORM_SBB_MEMv_IMM8_APX =2702 ,
  XED_IFORM_SBB_MEMv_IMMb =2703 ,
  XED_IFORM_SBB_MEMv_IMMz =2704 ,
  XED_IFORM_SBB_MEMv_IMMz_APX =2705 ,
  XED_IFORM_SBB_OrAX_IMMz =2706 ,
  XED_IFORM_SBB_LOCK_MEMb_GPR8 =2707 ,
  XED_IFORM_SBB_LOCK_MEMb_IMMb_80r3 =2708 ,
  XED_IFORM_SBB_LOCK_MEMb_IMMb_82r3 =2709 ,
  XED_IFORM_SBB_LOCK_MEMv_GPRv =2710 ,
  XED_IFORM_SBB_LOCK_MEMv_IMMb =2711 ,
  XED_IFORM_SBB_LOCK_MEMv_IMMz =2712 ,
  XED_IFORM_SCASB =2713 ,
  XED_IFORM_SCASD =2714 ,
  XED_IFORM_SCASQ =2715 ,
  XED_IFORM_SCASW =2716 ,
  XED_IFORM_SEAMCALL =2717 ,
  XED_IFORM_SEAMOPS =2718 ,
  XED_IFORM_SEAMRET =2719 ,
  XED_IFORM_SENDUIPI_GPR64u32 =2720 ,
  XED_IFORM_SERIALIZE =2721 ,
  XED_IFORM_SETB_GPR8 =2722 ,
  XED_IFORM_SETB_GPR8i8_APX =2723 ,
  XED_IFORM_SETB_GPR8i8_APX_ZU =2724 ,
  XED_IFORM_SETB_MEMb =2725 ,
  XED_IFORM_SETB_MEMi8_APX =2726 ,
  XED_IFORM_SETB_MEMi8_APX_ZU =2727 ,
  XED_IFORM_SETBE_GPR8 =2728 ,
  XED_IFORM_SETBE_GPR8i8_APX =2729 ,
  XED_IFORM_SETBE_GPR8i8_APX_ZU =2730 ,
  XED_IFORM_SETBE_MEMb =2731 ,
  XED_IFORM_SETBE_MEMi8_APX =2732 ,
  XED_IFORM_SETBE_MEMi8_APX_ZU =2733 ,
  XED_IFORM_SETL_GPR8 =2734 ,
  XED_IFORM_SETL_GPR8i8_APX =2735 ,
  XED_IFORM_SETL_GPR8i8_APX_ZU =2736 ,
  XED_IFORM_SETL_MEMb =2737 ,
  XED_IFORM_SETL_MEMi8_APX =2738 ,
  XED_IFORM_SETL_MEMi8_APX_ZU =2739 ,
  XED_IFORM_SETLE_GPR8 =2740 ,
  XED_IFORM_SETLE_GPR8i8_APX =2741 ,
  XED_IFORM_SETLE_GPR8i8_APX_ZU =2742 ,
  XED_IFORM_SETLE_MEMb =2743 ,
  XED_IFORM_SETLE_MEMi8_APX =2744 ,
  XED_IFORM_SETLE_MEMi8_APX_ZU =2745 ,
  XED_IFORM_SETNB_GPR8 =2746 ,
  XED_IFORM_SETNB_GPR8i8_APX =2747 ,
  XED_IFORM_SETNB_GPR8i8_APX_ZU =2748 ,
  XED_IFORM_SETNB_MEMb =2749 ,
  XED_IFORM_SETNB_MEMi8_APX =2750 ,
  XED_IFORM_SETNB_MEMi8_APX_ZU =2751 ,
  XED_IFORM_SETNBE_GPR8 =2752 ,
  XED_IFORM_SETNBE_GPR8i8_APX =2753 ,
  XED_IFORM_SETNBE_GPR8i8_APX_ZU =2754 ,
  XED_IFORM_SETNBE_MEMb =2755 ,
  XED_IFORM_SETNBE_MEMi8_APX =2756 ,
  XED_IFORM_SETNBE_MEMi8_APX_ZU =2757 ,
  XED_IFORM_SETNL_GPR8 =2758 ,
  XED_IFORM_SETNL_GPR8i8_APX =2759 ,
  XED_IFORM_SETNL_GPR8i8_APX_ZU =2760 ,
  XED_IFORM_SETNL_MEMb =2761 ,
  XED_IFORM_SETNL_MEMi8_APX =2762 ,
  XED_IFORM_SETNL_MEMi8_APX_ZU =2763 ,
  XED_IFORM_SETNLE_GPR8 =2764 ,
  XED_IFORM_SETNLE_GPR8i8_APX =2765 ,
  XED_IFORM_SETNLE_GPR8i8_APX_ZU =2766 ,
  XED_IFORM_SETNLE_MEMb =2767 ,
  XED_IFORM_SETNLE_MEMi8_APX =2768 ,
  XED_IFORM_SETNLE_MEMi8_APX_ZU =2769 ,
  XED_IFORM_SETNO_GPR8 =2770 ,
  XED_IFORM_SETNO_GPR8i8_APX =2771 ,
  XED_IFORM_SETNO_GPR8i8_APX_ZU =2772 ,
  XED_IFORM_SETNO_MEMb =2773 ,
  XED_IFORM_SETNO_MEMi8_APX =2774 ,
  XED_IFORM_SETNO_MEMi8_APX_ZU =2775 ,
  XED_IFORM_SETNP_GPR8 =2776 ,
  XED_IFORM_SETNP_GPR8i8_APX =2777 ,
  XED_IFORM_SETNP_GPR8i8_APX_ZU =2778 ,
  XED_IFORM_SETNP_MEMb =2779 ,
  XED_IFORM_SETNP_MEMi8_APX =2780 ,
  XED_IFORM_SETNP_MEMi8_APX_ZU =2781 ,
  XED_IFORM_SETNS_GPR8 =2782 ,
  XED_IFORM_SETNS_GPR8i8_APX =2783 ,
  XED_IFORM_SETNS_GPR8i8_APX_ZU =2784 ,
  XED_IFORM_SETNS_MEMb =2785 ,
  XED_IFORM_SETNS_MEMi8_APX =2786 ,
  XED_IFORM_SETNS_MEMi8_APX_ZU =2787 ,
  XED_IFORM_SETNZ_GPR8 =2788 ,
  XED_IFORM_SETNZ_GPR8i8_APX =2789 ,
  XED_IFORM_SETNZ_GPR8i8_APX_ZU =2790 ,
  XED_IFORM_SETNZ_MEMb =2791 ,
  XED_IFORM_SETNZ_MEMi8_APX =2792 ,
  XED_IFORM_SETNZ_MEMi8_APX_ZU =2793 ,
  XED_IFORM_SETO_GPR8 =2794 ,
  XED_IFORM_SETO_GPR8i8_APX =2795 ,
  XED_IFORM_SETO_GPR8i8_APX_ZU =2796 ,
  XED_IFORM_SETO_MEMb =2797 ,
  XED_IFORM_SETO_MEMi8_APX =2798 ,
  XED_IFORM_SETO_MEMi8_APX_ZU =2799 ,
  XED_IFORM_SETP_GPR8 =2800 ,
  XED_IFORM_SETP_GPR8i8_APX =2801 ,
  XED_IFORM_SETP_GPR8i8_APX_ZU =2802 ,
  XED_IFORM_SETP_MEMb =2803 ,
  XED_IFORM_SETP_MEMi8_APX =2804 ,
  XED_IFORM_SETP_MEMi8_APX_ZU =2805 ,
  XED_IFORM_SETS_GPR8 =2806 ,
  XED_IFORM_SETS_GPR8i8_APX =2807 ,
  XED_IFORM_SETS_GPR8i8_APX_ZU =2808 ,
  XED_IFORM_SETS_MEMb =2809 ,
  XED_IFORM_SETS_MEMi8_APX =2810 ,
  XED_IFORM_SETS_MEMi8_APX_ZU =2811 ,
  XED_IFORM_SETSSBSY =2812 ,
  XED_IFORM_SETZ_GPR8 =2813 ,
  XED_IFORM_SETZ_GPR8i8_APX =2814 ,
  XED_IFORM_SETZ_GPR8i8_APX_ZU =2815 ,
  XED_IFORM_SETZ_MEMb =2816 ,
  XED_IFORM_SETZ_MEMi8_APX =2817 ,
  XED_IFORM_SETZ_MEMi8_APX_ZU =2818 ,
  XED_IFORM_SFENCE =2819 ,
  XED_IFORM_SGDT_MEMs =2820 ,
  XED_IFORM_SGDT_MEMs64 =2821 ,
  XED_IFORM_SHA1MSG1_XMMi32_MEMi32_SHA =2822 ,
  XED_IFORM_SHA1MSG1_XMMi32_XMMi32_SHA =2823 ,
  XED_IFORM_SHA1MSG2_XMMi32_MEMi32_SHA =2824 ,
  XED_IFORM_SHA1MSG2_XMMi32_XMMi32_SHA =2825 ,
  XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_SHA =2826 ,
  XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_SHA =2827 ,
  XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA =2828 ,
  XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA =2829 ,
  XED_IFORM_SHA256MSG1_XMMi32_MEMi32_SHA =2830 ,
  XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA =2831 ,
  XED_IFORM_SHA256MSG2_XMMi32_MEMi32_SHA =2832 ,
  XED_IFORM_SHA256MSG2_XMMi32_XMMi32_SHA =2833 ,
  XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_SHA =2834 ,
  XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_SHA =2835 ,
  XED_IFORM_SHL_GPR8_CL_D2r4 =2836 ,
  XED_IFORM_SHL_GPR8_CL_D2r6 =2837 ,
  XED_IFORM_SHL_GPR8_IMMb_C0r4 =2838 ,
  XED_IFORM_SHL_GPR8_IMMb_C0r6 =2839 ,
  XED_IFORM_SHL_GPR8_ONE_D0r4 =2840 ,
  XED_IFORM_SHL_GPR8_ONE_D0r6 =2841 ,
  XED_IFORM_SHL_GPR8i8_CL_APX =2842 ,
  XED_IFORM_SHL_GPR8i8_GPR8i8_CL_APX =2843 ,
  XED_IFORM_SHL_GPR8i8_GPR8i8_IMM8_APX =2844 ,
  XED_IFORM_SHL_GPR8i8_GPR8i8_ONE_APX =2845 ,
  XED_IFORM_SHL_GPR8i8_IMM8_APX =2846 ,
  XED_IFORM_SHL_GPR8i8_MEMi8_CL_APX =2847 ,
  XED_IFORM_SHL_GPR8i8_MEMi8_IMM8_APX =2848 ,
  XED_IFORM_SHL_GPR8i8_MEMi8_ONE_APX =2849 ,
  XED_IFORM_SHL_GPR8i8_ONE_APX =2850 ,
  XED_IFORM_SHL_GPRv_CL_APX =2851 ,
  XED_IFORM_SHL_GPRv_CL_D3r4 =2852 ,
  XED_IFORM_SHL_GPRv_CL_D3r6 =2853 ,
  XED_IFORM_SHL_GPRv_GPRv_CL_APX =2854 ,
  XED_IFORM_SHL_GPRv_GPRv_IMM8_APX =2855 ,
  XED_IFORM_SHL_GPRv_GPRv_ONE_APX =2856 ,
  XED_IFORM_SHL_GPRv_IMM8_APX =2857 ,
  XED_IFORM_SHL_GPRv_IMMb_C1r4 =2858 ,
  XED_IFORM_SHL_GPRv_IMMb_C1r6 =2859 ,
  XED_IFORM_SHL_GPRv_MEMv_CL_APX =2860 ,
  XED_IFORM_SHL_GPRv_MEMv_IMM8_APX =2861 ,
  XED_IFORM_SHL_GPRv_MEMv_ONE_APX =2862 ,
  XED_IFORM_SHL_GPRv_ONE_APX =2863 ,
  XED_IFORM_SHL_GPRv_ONE_D1r4 =2864 ,
  XED_IFORM_SHL_GPRv_ONE_D1r6 =2865 ,
  XED_IFORM_SHL_MEMb_CL_D2r4 =2866 ,
  XED_IFORM_SHL_MEMb_CL_D2r6 =2867 ,
  XED_IFORM_SHL_MEMb_IMMb_C0r4 =2868 ,
  XED_IFORM_SHL_MEMb_IMMb_C0r6 =2869 ,
  XED_IFORM_SHL_MEMb_ONE_D0r4 =2870 ,
  XED_IFORM_SHL_MEMb_ONE_D0r6 =2871 ,
  XED_IFORM_SHL_MEMi8_CL_APX =2872 ,
  XED_IFORM_SHL_MEMi8_IMM8_APX =2873 ,
  XED_IFORM_SHL_MEMi8_ONE_APX =2874 ,
  XED_IFORM_SHL_MEMv_CL_APX =2875 ,
  XED_IFORM_SHL_MEMv_CL_D3r4 =2876 ,
  XED_IFORM_SHL_MEMv_CL_D3r6 =2877 ,
  XED_IFORM_SHL_MEMv_IMM8_APX =2878 ,
  XED_IFORM_SHL_MEMv_IMMb_C1r4 =2879 ,
  XED_IFORM_SHL_MEMv_IMMb_C1r6 =2880 ,
  XED_IFORM_SHL_MEMv_ONE_APX =2881 ,
  XED_IFORM_SHL_MEMv_ONE_D1r4 =2882 ,
  XED_IFORM_SHL_MEMv_ONE_D1r6 =2883 ,
  XED_IFORM_SHLD_GPRv_GPRv_CL =2884 ,
  XED_IFORM_SHLD_GPRv_GPRv_CL_APX =2885 ,
  XED_IFORM_SHLD_GPRv_GPRv_GPRv_CL_APX =2886 ,
  XED_IFORM_SHLD_GPRv_GPRv_GPRv_IMM8_APX =2887 ,
  XED_IFORM_SHLD_GPRv_GPRv_IMM8_APX =2888 ,
  XED_IFORM_SHLD_GPRv_GPRv_IMMb =2889 ,
  XED_IFORM_SHLD_GPRv_MEMv_GPRv_CL_APX =2890 ,
  XED_IFORM_SHLD_GPRv_MEMv_GPRv_IMM8_APX =2891 ,
  XED_IFORM_SHLD_MEMv_GPRv_CL =2892 ,
  XED_IFORM_SHLD_MEMv_GPRv_CL_APX =2893 ,
  XED_IFORM_SHLD_MEMv_GPRv_IMM8_APX =2894 ,
  XED_IFORM_SHLD_MEMv_GPRv_IMMb =2895 ,
  XED_IFORM_SHLX_GPR32d_GPR32d_GPR32d =2896 ,
  XED_IFORM_SHLX_GPR32d_MEMd_GPR32d =2897 ,
  XED_IFORM_SHLX_GPR32i32_GPR32i32_GPR32i32_APX =2898 ,
  XED_IFORM_SHLX_GPR32i32_MEMi32_GPR32i32_APX =2899 ,
  XED_IFORM_SHLX_GPR64i64_GPR64i64_GPR64i64_APX =2900 ,
  XED_IFORM_SHLX_GPR64i64_MEMi64_GPR64i64_APX =2901 ,
  XED_IFORM_SHLX_GPR64q_GPR64q_GPR64q =2902 ,
  XED_IFORM_SHLX_GPR64q_MEMq_GPR64q =2903 ,
  XED_IFORM_SHR_GPR8_CL =2904 ,
  XED_IFORM_SHR_GPR8_IMMb =2905 ,
  XED_IFORM_SHR_GPR8_ONE =2906 ,
  XED_IFORM_SHR_GPR8i8_CL_APX =2907 ,
  XED_IFORM_SHR_GPR8i8_GPR8i8_CL_APX =2908 ,
  XED_IFORM_SHR_GPR8i8_GPR8i8_IMM8_APX =2909 ,
  XED_IFORM_SHR_GPR8i8_GPR8i8_ONE_APX =2910 ,
  XED_IFORM_SHR_GPR8i8_IMM8_APX =2911 ,
  XED_IFORM_SHR_GPR8i8_MEMi8_CL_APX =2912 ,
  XED_IFORM_SHR_GPR8i8_MEMi8_IMM8_APX =2913 ,
  XED_IFORM_SHR_GPR8i8_MEMi8_ONE_APX =2914 ,
  XED_IFORM_SHR_GPR8i8_ONE_APX =2915 ,
  XED_IFORM_SHR_GPRv_CL =2916 ,
  XED_IFORM_SHR_GPRv_CL_APX =2917 ,
  XED_IFORM_SHR_GPRv_GPRv_CL_APX =2918 ,
  XED_IFORM_SHR_GPRv_GPRv_IMM8_APX =2919 ,
  XED_IFORM_SHR_GPRv_GPRv_ONE_APX =2920 ,
  XED_IFORM_SHR_GPRv_IMM8_APX =2921 ,
  XED_IFORM_SHR_GPRv_IMMb =2922 ,
  XED_IFORM_SHR_GPRv_MEMv_CL_APX =2923 ,
  XED_IFORM_SHR_GPRv_MEMv_IMM8_APX =2924 ,
  XED_IFORM_SHR_GPRv_MEMv_ONE_APX =2925 ,
  XED_IFORM_SHR_GPRv_ONE =2926 ,
  XED_IFORM_SHR_GPRv_ONE_APX =2927 ,
  XED_IFORM_SHR_MEMb_CL =2928 ,
  XED_IFORM_SHR_MEMb_IMMb =2929 ,
  XED_IFORM_SHR_MEMb_ONE =2930 ,
  XED_IFORM_SHR_MEMi8_CL_APX =2931 ,
  XED_IFORM_SHR_MEMi8_IMM8_APX =2932 ,
  XED_IFORM_SHR_MEMi8_ONE_APX =2933 ,
  XED_IFORM_SHR_MEMv_CL =2934 ,
  XED_IFORM_SHR_MEMv_CL_APX =2935 ,
  XED_IFORM_SHR_MEMv_IMM8_APX =2936 ,
  XED_IFORM_SHR_MEMv_IMMb =2937 ,
  XED_IFORM_SHR_MEMv_ONE =2938 ,
  XED_IFORM_SHR_MEMv_ONE_APX =2939 ,
  XED_IFORM_SHRD_GPRv_GPRv_CL =2940 ,
  XED_IFORM_SHRD_GPRv_GPRv_CL_APX =2941 ,
  XED_IFORM_SHRD_GPRv_GPRv_GPRv_CL_APX =2942 ,
  XED_IFORM_SHRD_GPRv_GPRv_GPRv_IMM8_APX =2943 ,
  XED_IFORM_SHRD_GPRv_GPRv_IMM8_APX =2944 ,
  XED_IFORM_SHRD_GPRv_GPRv_IMMb =2945 ,
  XED_IFORM_SHRD_GPRv_MEMv_GPRv_CL_APX =2946 ,
  XED_IFORM_SHRD_GPRv_MEMv_GPRv_IMM8_APX =2947 ,
  XED_IFORM_SHRD_MEMv_GPRv_CL =2948 ,
  XED_IFORM_SHRD_MEMv_GPRv_CL_APX =2949 ,
  XED_IFORM_SHRD_MEMv_GPRv_IMM8_APX =2950 ,
  XED_IFORM_SHRD_MEMv_GPRv_IMMb =2951 ,
  XED_IFORM_SHRX_GPR32d_GPR32d_GPR32d =2952 ,
  XED_IFORM_SHRX_GPR32d_MEMd_GPR32d =2953 ,
  XED_IFORM_SHRX_GPR32i32_GPR32i32_GPR32i32_APX =2954 ,
  XED_IFORM_SHRX_GPR32i32_MEMi32_GPR32i32_APX =2955 ,
  XED_IFORM_SHRX_GPR64i64_GPR64i64_GPR64i64_APX =2956 ,
  XED_IFORM_SHRX_GPR64i64_MEMi64_GPR64i64_APX =2957 ,
  XED_IFORM_SHRX_GPR64q_GPR64q_GPR64q =2958 ,
  XED_IFORM_SHRX_GPR64q_MEMq_GPR64q =2959 ,
  XED_IFORM_SHUFPD_XMMpd_MEMpd_IMMb =2960 ,
  XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb =2961 ,
  XED_IFORM_SHUFPS_XMMps_MEMps_IMMb =2962 ,
  XED_IFORM_SHUFPS_XMMps_XMMps_IMMb =2963 ,
  XED_IFORM_SIDT_MEMs =2964 ,
  XED_IFORM_SIDT_MEMs64 =2965 ,
  XED_IFORM_SKINIT_EAX =2966 ,
  XED_IFORM_SLDT_GPRv =2967 ,
  XED_IFORM_SLDT_MEMw =2968 ,
  XED_IFORM_SLWPCB_GPRyy =2969 ,
  XED_IFORM_SMSW_GPRv =2970 ,
  XED_IFORM_SMSW_MEMw =2971 ,
  XED_IFORM_SQRTPD_XMMpd_MEMpd =2972 ,
  XED_IFORM_SQRTPD_XMMpd_XMMpd =2973 ,
  XED_IFORM_SQRTPS_XMMps_MEMps =2974 ,
  XED_IFORM_SQRTPS_XMMps_XMMps =2975 ,
  XED_IFORM_SQRTSD_XMMsd_MEMsd =2976 ,
  XED_IFORM_SQRTSD_XMMsd_XMMsd =2977 ,
  XED_IFORM_SQRTSS_XMMss_MEMss =2978 ,
  XED_IFORM_SQRTSS_XMMss_XMMss =2979 ,
  XED_IFORM_STAC =2980 ,
  XED_IFORM_STC =2981 ,
  XED_IFORM_STD =2982 ,
  XED_IFORM_STGI =2983 ,
  XED_IFORM_STI =2984 ,
  XED_IFORM_STMXCSR_MEMd =2985 ,
  XED_IFORM_STOSB =2986 ,
  XED_IFORM_STOSD =2987 ,
  XED_IFORM_STOSQ =2988 ,
  XED_IFORM_STOSW =2989 ,
  XED_IFORM_STR_GPRv =2990 ,
  XED_IFORM_STR_MEMw =2991 ,
  XED_IFORM_STTILECFG_MEM =2992 ,
  XED_IFORM_STTILECFG_MEM_APX =2993 ,
  XED_IFORM_STUI =2994 ,
  XED_IFORM_SUB_AL_IMMb =2995 ,
  XED_IFORM_SUB_GPR8_GPR8_28 =2996 ,
  XED_IFORM_SUB_GPR8_GPR8_2A =2997 ,
  XED_IFORM_SUB_GPR8_IMMb_80r5 =2998 ,
  XED_IFORM_SUB_GPR8_IMMb_82r5 =2999 ,
  XED_IFORM_SUB_GPR8_MEMb =3000 ,
  XED_IFORM_SUB_GPR8i8_GPR8i8_APX =3001 ,
  XED_IFORM_SUB_GPR8i8_GPR8i8_GPR8i8_APX =3002 ,
  XED_IFORM_SUB_GPR8i8_GPR8i8_IMM8_APX =3003 ,
  XED_IFORM_SUB_GPR8i8_GPR8i8_MEMi8_APX =3004 ,
  XED_IFORM_SUB_GPR8i8_IMM8_APX =3005 ,
  XED_IFORM_SUB_GPR8i8_MEMi8_APX =3006 ,
  XED_IFORM_SUB_GPR8i8_MEMi8_GPR8i8_APX =3007 ,
  XED_IFORM_SUB_GPR8i8_MEMi8_IMM8_APX =3008 ,
  XED_IFORM_SUB_GPRv_GPRv_29 =3009 ,
  XED_IFORM_SUB_GPRv_GPRv_2B =3010 ,
  XED_IFORM_SUB_GPRv_GPRv_APX =3011 ,
  XED_IFORM_SUB_GPRv_GPRv_GPRv_APX =3012 ,
  XED_IFORM_SUB_GPRv_GPRv_IMM8_APX =3013 ,
  XED_IFORM_SUB_GPRv_GPRv_IMMz_APX =3014 ,
  XED_IFORM_SUB_GPRv_GPRv_MEMv_APX =3015 ,
  XED_IFORM_SUB_GPRv_IMM8_APX =3016 ,
  XED_IFORM_SUB_GPRv_IMMb =3017 ,
  XED_IFORM_SUB_GPRv_IMMz =3018 ,
  XED_IFORM_SUB_GPRv_IMMz_APX =3019 ,
  XED_IFORM_SUB_GPRv_MEMv =3020 ,
  XED_IFORM_SUB_GPRv_MEMv_APX =3021 ,
  XED_IFORM_SUB_GPRv_MEMv_GPRv_APX =3022 ,
  XED_IFORM_SUB_GPRv_MEMv_IMM8_APX =3023 ,
  XED_IFORM_SUB_GPRv_MEMv_IMMz_APX =3024 ,
  XED_IFORM_SUB_MEMb_GPR8 =3025 ,
  XED_IFORM_SUB_MEMb_IMMb_80r5 =3026 ,
  XED_IFORM_SUB_MEMb_IMMb_82r5 =3027 ,
  XED_IFORM_SUB_MEMi8_GPR8i8_APX =3028 ,
  XED_IFORM_SUB_MEMi8_IMM8_APX =3029 ,
  XED_IFORM_SUB_MEMv_GPRv =3030 ,
  XED_IFORM_SUB_MEMv_GPRv_APX =3031 ,
  XED_IFORM_SUB_MEMv_IMM8_APX =3032 ,
  XED_IFORM_SUB_MEMv_IMMb =3033 ,
  XED_IFORM_SUB_MEMv_IMMz =3034 ,
  XED_IFORM_SUB_MEMv_IMMz_APX =3035 ,
  XED_IFORM_SUB_OrAX_IMMz =3036 ,
  XED_IFORM_SUBPD_XMMpd_MEMpd =3037 ,
  XED_IFORM_SUBPD_XMMpd_XMMpd =3038 ,
  XED_IFORM_SUBPS_XMMps_MEMps =3039 ,
  XED_IFORM_SUBPS_XMMps_XMMps =3040 ,
  XED_IFORM_SUBSD_XMMsd_MEMsd =3041 ,
  XED_IFORM_SUBSD_XMMsd_XMMsd =3042 ,
  XED_IFORM_SUBSS_XMMss_MEMss =3043 ,
  XED_IFORM_SUBSS_XMMss_XMMss =3044 ,
  XED_IFORM_SUB_LOCK_MEMb_GPR8 =3045 ,
  XED_IFORM_SUB_LOCK_MEMb_IMMb_80r5 =3046 ,
  XED_IFORM_SUB_LOCK_MEMb_IMMb_82r5 =3047 ,
  XED_IFORM_SUB_LOCK_MEMv_GPRv =3048 ,
  XED_IFORM_SUB_LOCK_MEMv_IMMb =3049 ,
  XED_IFORM_SUB_LOCK_MEMv_IMMz =3050 ,
  XED_IFORM_SWAPGS =3051 ,
  XED_IFORM_SYSCALL =3052 ,
  XED_IFORM_SYSCALL_AMD =3053 ,
  XED_IFORM_SYSENTER =3054 ,
  XED_IFORM_SYSEXIT =3055 ,
  XED_IFORM_SYSRET =3056 ,
  XED_IFORM_SYSRET64 =3057 ,
  XED_IFORM_SYSRET_AMD =3058 ,
  XED_IFORM_T1MSKC_GPR32d_GPR32d =3059 ,
  XED_IFORM_T1MSKC_GPR32d_MEMd =3060 ,
  XED_IFORM_T1MSKC_GPRyy_GPRyy =3061 ,
  XED_IFORM_T1MSKC_GPRyy_MEMy =3062 ,
  XED_IFORM_T2RPNTLVWZ0_TMM2u16_MEMu16 =3063 ,
  XED_IFORM_T2RPNTLVWZ0_TMM2u16_MEMu16_APX =3064 ,
  XED_IFORM_T2RPNTLVWZ0RS_TMM2u16_MEMu16 =3065 ,
  XED_IFORM_T2RPNTLVWZ0RS_TMM2u16_MEMu16_APX =3066 ,
  XED_IFORM_T2RPNTLVWZ0RST1_TMM2u16_MEMu16 =3067 ,
  XED_IFORM_T2RPNTLVWZ0RST1_TMM2u16_MEMu16_APX =3068 ,
  XED_IFORM_T2RPNTLVWZ0T1_TMM2u16_MEMu16 =3069 ,
  XED_IFORM_T2RPNTLVWZ0T1_TMM2u16_MEMu16_APX =3070 ,
  XED_IFORM_T2RPNTLVWZ1_TMM2u16_MEMu16 =3071 ,
  XED_IFORM_T2RPNTLVWZ1_TMM2u16_MEMu16_APX =3072 ,
  XED_IFORM_T2RPNTLVWZ1RS_TMM2u16_MEMu16 =3073 ,
  XED_IFORM_T2RPNTLVWZ1RS_TMM2u16_MEMu16_APX =3074 ,
  XED_IFORM_T2RPNTLVWZ1RST1_TMM2u16_MEMu16 =3075 ,
  XED_IFORM_T2RPNTLVWZ1RST1_TMM2u16_MEMu16_APX =3076 ,
  XED_IFORM_T2RPNTLVWZ1T1_TMM2u16_MEMu16 =3077 ,
  XED_IFORM_T2RPNTLVWZ1T1_TMM2u16_MEMu16_APX =3078 ,
  XED_IFORM_TCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16 =3079 ,
  XED_IFORM_TCMMRLFP16PS_TMMf32_TMM2f16_TMM2f16 =3080 ,
  XED_IFORM_TCONJTCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16 =3081 ,
  XED_IFORM_TCONJTFP16_TMM2f16_TMM2f16 =3082 ,
  XED_IFORM_TCVTROWD2PS_ZMMf32_TMMu32_GPR32u32 =3083 ,
  XED_IFORM_TCVTROWD2PS_ZMMf32_TMMu32_IMM8 =3084 ,
  XED_IFORM_TCVTROWPS2BF16H_ZMMbf16_TMMf32_GPR32u32 =3085 ,
  XED_IFORM_TCVTROWPS2BF16H_ZMMbf16_TMMf32_IMM8 =3086 ,
  XED_IFORM_TCVTROWPS2BF16L_ZMMbf16_TMMf32_GPR32u32 =3087 ,
  XED_IFORM_TCVTROWPS2BF16L_ZMMbf16_TMMf32_IMM8 =3088 ,
  XED_IFORM_TCVTROWPS2PHH_ZMMf16_TMMf32_GPR32u32 =3089 ,
  XED_IFORM_TCVTROWPS2PHH_ZMMf16_TMMf32_IMM8 =3090 ,
  XED_IFORM_TCVTROWPS2PHL_ZMMf16_TMMf32_GPR32u32 =3091 ,
  XED_IFORM_TCVTROWPS2PHL_ZMMf16_TMMf32_IMM8 =3092 ,
  XED_IFORM_TDCALL =3093 ,
  XED_IFORM_TDPBF16PS_TMMf32_TMM2bf16_TMM2bf16 =3094 ,
  XED_IFORM_TDPBF8PS_TMMf32_TMM4bf8_TMM4bf8 =3095 ,
  XED_IFORM_TDPBHF8PS_TMMf32_TMM4bf8_TMM4hf8 =3096 ,
  XED_IFORM_TDPBSSD_TMMi32_TMM4i8_TMM4i8 =3097 ,
  XED_IFORM_TDPBSUD_TMMi32_TMM4i8_TMM4u8 =3098 ,
  XED_IFORM_TDPBUSD_TMMi32_TMM4u8_TMM4i8 =3099 ,
  XED_IFORM_TDPBUUD_TMMu32_TMM4u8_TMM4u8 =3100 ,
  XED_IFORM_TDPFP16PS_TMMf32_TMM2f16_TMM2f16 =3101 ,
  XED_IFORM_TDPHBF8PS_TMMf32_TMM4hf8_TMM4bf8 =3102 ,
  XED_IFORM_TDPHF8PS_TMMf32_TMM4hf8_TMM4hf8 =3103 ,
  XED_IFORM_TEST_AL_IMMb =3104 ,
  XED_IFORM_TEST_GPR8_GPR8 =3105 ,
  XED_IFORM_TEST_GPR8_IMMb_F6r0 =3106 ,
  XED_IFORM_TEST_GPR8_IMMb_F6r1 =3107 ,
  XED_IFORM_TEST_GPRv_GPRv =3108 ,
  XED_IFORM_TEST_GPRv_IMMz_F7r0 =3109 ,
  XED_IFORM_TEST_GPRv_IMMz_F7r1 =3110 ,
  XED_IFORM_TEST_MEMb_GPR8 =3111 ,
  XED_IFORM_TEST_MEMb_IMMb_F6r0 =3112 ,
  XED_IFORM_TEST_MEMb_IMMb_F6r1 =3113 ,
  XED_IFORM_TEST_MEMv_GPRv =3114 ,
  XED_IFORM_TEST_MEMv_IMMz_F7r0 =3115 ,
  XED_IFORM_TEST_MEMv_IMMz_F7r1 =3116 ,
  XED_IFORM_TEST_OrAX_IMMz =3117 ,
  XED_IFORM_TESTUI =3118 ,
  XED_IFORM_TILELOADD_TMMu32_MEMu32 =3119 ,
  XED_IFORM_TILELOADD_TMMu32_MEMu32_APX =3120 ,
  XED_IFORM_TILELOADDRS_TMMu32_MEMu32 =3121 ,
  XED_IFORM_TILELOADDRS_TMMu32_MEMu32_APX =3122 ,
  XED_IFORM_TILELOADDRST1_TMMu32_MEMu32 =3123 ,
  XED_IFORM_TILELOADDRST1_TMMu32_MEMu32_APX =3124 ,
  XED_IFORM_TILELOADDT1_TMMu32_MEMu32 =3125 ,
  XED_IFORM_TILELOADDT1_TMMu32_MEMu32_APX =3126 ,
  XED_IFORM_TILEMOVROW_ZMMu8_TMMu8_GPR32u32 =3127 ,
  XED_IFORM_TILEMOVROW_ZMMu8_TMMu8_IMM8 =3128 ,
  XED_IFORM_TILERELEASE =3129 ,
  XED_IFORM_TILESTORED_MEMu32_TMMu32 =3130 ,
  XED_IFORM_TILESTORED_MEMu32_TMMu32_APX =3131 ,
  XED_IFORM_TILEZERO_TMMu32 =3132 ,
  XED_IFORM_TLBSYNC =3133 ,
  XED_IFORM_TMMULTF32PS_TMMf32_TMMf32_TMMf32 =3134 ,
  XED_IFORM_TPAUSE_GPR32u32 =3135 ,
  XED_IFORM_TTCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16 =3136 ,
  XED_IFORM_TTCMMRLFP16PS_TMMf32_TMM2f16_TMM2f16 =3137 ,
  XED_IFORM_TTDPBF16PS_TMMf32_TMMbf16_TMMbf16 =3138 ,
  XED_IFORM_TTDPFP16PS_TMMf32_TMMf16_TMMf16 =3139 ,
  XED_IFORM_TTMMULTF32PS_TMMf32_TMMf32_TMMf32 =3140 ,
  XED_IFORM_TTRANSPOSED_TMMu32_TMMu32 =3141 ,
  XED_IFORM_TZCNT_GPRv_GPRv =3142 ,
  XED_IFORM_TZCNT_GPRv_GPRv_APX =3143 ,
  XED_IFORM_TZCNT_GPRv_MEMv =3144 ,
  XED_IFORM_TZCNT_GPRv_MEMv_APX =3145 ,
  XED_IFORM_TZMSK_GPR32d_GPR32d =3146 ,
  XED_IFORM_TZMSK_GPR32d_MEMd =3147 ,
  XED_IFORM_TZMSK_GPRyy_GPRyy =3148 ,
  XED_IFORM_TZMSK_GPRyy_MEMy =3149 ,
  XED_IFORM_UCOMISD_XMMsd_MEMsd =3150 ,
  XED_IFORM_UCOMISD_XMMsd_XMMsd =3151 ,
  XED_IFORM_UCOMISS_XMMss_MEMss =3152 ,
  XED_IFORM_UCOMISS_XMMss_XMMss =3153 ,
  XED_IFORM_UD0 =3154 ,
  XED_IFORM_UD0_GPR32_GPR32 =3155 ,
  XED_IFORM_UD0_GPR32_MEMd =3156 ,
  XED_IFORM_UD1_GPR32_GPR32 =3157 ,
  XED_IFORM_UD1_GPR32_MEMd =3158 ,
  XED_IFORM_UD2 =3159 ,
  XED_IFORM_UIRET =3160 ,
  XED_IFORM_UMONITOR_GPRa =3161 ,
  XED_IFORM_UMWAIT_GPR32 =3162 ,
  XED_IFORM_UNPCKHPD_XMMpd_MEMdq =3163 ,
  XED_IFORM_UNPCKHPD_XMMpd_XMMq =3164 ,
  XED_IFORM_UNPCKHPS_XMMps_MEMdq =3165 ,
  XED_IFORM_UNPCKHPS_XMMps_XMMdq =3166 ,
  XED_IFORM_UNPCKLPD_XMMpd_MEMdq =3167 ,
  XED_IFORM_UNPCKLPD_XMMpd_XMMq =3168 ,
  XED_IFORM_UNPCKLPS_XMMps_MEMdq =3169 ,
  XED_IFORM_UNPCKLPS_XMMps_XMMq =3170 ,
  XED_IFORM_URDMSR_GPR64u64_GPR64u64 =3171 ,
  XED_IFORM_URDMSR_GPR64u64_GPR64u64_APX =3172 ,
  XED_IFORM_URDMSR_GPR64u64_IMM32 =3173 ,
  XED_IFORM_URDMSR_GPR64u64_IMM32_APX =3174 ,
  XED_IFORM_UWRMSR_GPR64u64_GPR64u64 =3175 ,
  XED_IFORM_UWRMSR_GPR64u64_GPR64u64_APX =3176 ,
  XED_IFORM_UWRMSR_IMM32_GPR64u64 =3177 ,
  XED_IFORM_UWRMSR_IMM32_GPR64u64_APX =3178 ,
  XED_IFORM_V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =3179 ,
  XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =3180 ,
  XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =3181 ,
  XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =3182 ,
  XED_IFORM_VADDBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =3183 ,
  XED_IFORM_VADDBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =3184 ,
  XED_IFORM_VADDBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =3185 ,
  XED_IFORM_VADDBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =3186 ,
  XED_IFORM_VADDBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =3187 ,
  XED_IFORM_VADDBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =3188 ,
  XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq =3189 ,
  XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq =3190 ,
  XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =3191 ,
  XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =3192 ,
  XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =3193 ,
  XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =3194 ,
  XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq =3195 ,
  XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq =3196 ,
  XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =3197 ,
  XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =3198 ,
  XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =3199 ,
  XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =3200 ,
  XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =3201 ,
  XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =3202 ,
  XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =3203 ,
  XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =3204 ,
  XED_IFORM_VADDPS_XMMdq_XMMdq_MEMdq =3205 ,
  XED_IFORM_VADDPS_XMMdq_XMMdq_XMMdq =3206 ,
  XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =3207 ,
  XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =3208 ,
  XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =3209 ,
  XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =3210 ,
  XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq =3211 ,
  XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq =3212 ,
  XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =3213 ,
  XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =3214 ,
  XED_IFORM_VADDSD_XMMdq_XMMdq_MEMq =3215 ,
  XED_IFORM_VADDSD_XMMdq_XMMdq_XMMq =3216 ,
  XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =3217 ,
  XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =3218 ,
  XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =3219 ,
  XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =3220 ,
  XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd =3221 ,
  XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd =3222 ,
  XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =3223 ,
  XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =3224 ,
  XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq =3225 ,
  XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq =3226 ,
  XED_IFORM_VADDSUBPD_YMMqq_YMMqq_MEMqq =3227 ,
  XED_IFORM_VADDSUBPD_YMMqq_YMMqq_YMMqq =3228 ,
  XED_IFORM_VADDSUBPS_XMMdq_XMMdq_MEMdq =3229 ,
  XED_IFORM_VADDSUBPS_XMMdq_XMMdq_XMMdq =3230 ,
  XED_IFORM_VADDSUBPS_YMMqq_YMMqq_MEMqq =3231 ,
  XED_IFORM_VADDSUBPS_YMMqq_YMMqq_YMMqq =3232 ,
  XED_IFORM_VAESDEC_XMMdq_XMMdq_MEMdq =3233 ,
  XED_IFORM_VAESDEC_XMMdq_XMMdq_XMMdq =3234 ,
  XED_IFORM_VAESDEC_XMMu128_XMMu128_MEMu128_AVX512 =3235 ,
  XED_IFORM_VAESDEC_XMMu128_XMMu128_XMMu128_AVX512 =3236 ,
  XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128 =3237 ,
  XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_AVX512 =3238 ,
  XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128 =3239 ,
  XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_AVX512 =3240 ,
  XED_IFORM_VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512 =3241 ,
  XED_IFORM_VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512 =3242 ,
  XED_IFORM_VAESDECLAST_XMMdq_XMMdq_MEMdq =3243 ,
  XED_IFORM_VAESDECLAST_XMMdq_XMMdq_XMMdq =3244 ,
  XED_IFORM_VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512 =3245 ,
  XED_IFORM_VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512 =3246 ,
  XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128 =3247 ,
  XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512 =3248 ,
  XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128 =3249 ,
  XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512 =3250 ,
  XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512 =3251 ,
  XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 =3252 ,
  XED_IFORM_VAESENC_XMMdq_XMMdq_MEMdq =3253 ,
  XED_IFORM_VAESENC_XMMdq_XMMdq_XMMdq =3254 ,
  XED_IFORM_VAESENC_XMMu128_XMMu128_MEMu128_AVX512 =3255 ,
  XED_IFORM_VAESENC_XMMu128_XMMu128_XMMu128_AVX512 =3256 ,
  XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128 =3257 ,
  XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_AVX512 =3258 ,
  XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128 =3259 ,
  XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_AVX512 =3260 ,
  XED_IFORM_VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512 =3261 ,
  XED_IFORM_VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512 =3262 ,
  XED_IFORM_VAESENCLAST_XMMdq_XMMdq_MEMdq =3263 ,
  XED_IFORM_VAESENCLAST_XMMdq_XMMdq_XMMdq =3264 ,
  XED_IFORM_VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512 =3265 ,
  XED_IFORM_VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512 =3266 ,
  XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128 =3267 ,
  XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512 =3268 ,
  XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128 =3269 ,
  XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512 =3270 ,
  XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512 =3271 ,
  XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 =3272 ,
  XED_IFORM_VAESIMC_XMMdq_MEMdq =3273 ,
  XED_IFORM_VAESIMC_XMMdq_XMMdq =3274 ,
  XED_IFORM_VAESKEYGENASSIST_XMMdq_MEMdq_IMMb =3275 ,
  XED_IFORM_VAESKEYGENASSIST_XMMdq_XMMdq_IMMb =3276 ,
  XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 =3277 ,
  XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 =3278 ,
  XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 =3279 ,
  XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 =3280 ,
  XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 =3281 ,
  XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 =3282 ,
  XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 =3283 ,
  XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 =3284 ,
  XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 =3285 ,
  XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 =3286 ,
  XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 =3287 ,
  XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 =3288 ,
  XED_IFORM_VANDNPD_XMMdq_XMMdq_MEMdq =3289 ,
  XED_IFORM_VANDNPD_XMMdq_XMMdq_XMMdq =3290 ,
  XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =3291 ,
  XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =3292 ,
  XED_IFORM_VANDNPD_YMMqq_YMMqq_MEMqq =3293 ,
  XED_IFORM_VANDNPD_YMMqq_YMMqq_YMMqq =3294 ,
  XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =3295 ,
  XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =3296 ,
  XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =3297 ,
  XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =3298 ,
  XED_IFORM_VANDNPS_XMMdq_XMMdq_MEMdq =3299 ,
  XED_IFORM_VANDNPS_XMMdq_XMMdq_XMMdq =3300 ,
  XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =3301 ,
  XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =3302 ,
  XED_IFORM_VANDNPS_YMMqq_YMMqq_MEMqq =3303 ,
  XED_IFORM_VANDNPS_YMMqq_YMMqq_YMMqq =3304 ,
  XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =3305 ,
  XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =3306 ,
  XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =3307 ,
  XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =3308 ,
  XED_IFORM_VANDPD_XMMdq_XMMdq_MEMdq =3309 ,
  XED_IFORM_VANDPD_XMMdq_XMMdq_XMMdq =3310 ,
  XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =3311 ,
  XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =3312 ,
  XED_IFORM_VANDPD_YMMqq_YMMqq_MEMqq =3313 ,
  XED_IFORM_VANDPD_YMMqq_YMMqq_YMMqq =3314 ,
  XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =3315 ,
  XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =3316 ,
  XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =3317 ,
  XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =3318 ,
  XED_IFORM_VANDPS_XMMdq_XMMdq_MEMdq =3319 ,
  XED_IFORM_VANDPS_XMMdq_XMMdq_XMMdq =3320 ,
  XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =3321 ,
  XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =3322 ,
  XED_IFORM_VANDPS_YMMqq_YMMqq_MEMqq =3323 ,
  XED_IFORM_VANDPS_YMMqq_YMMqq_YMMqq =3324 ,
  XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =3325 ,
  XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =3326 ,
  XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =3327 ,
  XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =3328 ,
  XED_IFORM_VBCSTNEBF162PS_XMMf32_MEMbf16 =3329 ,
  XED_IFORM_VBCSTNEBF162PS_YMMf32_MEMbf16 =3330 ,
  XED_IFORM_VBCSTNESH2PS_XMMf32_MEMf16 =3331 ,
  XED_IFORM_VBCSTNESH2PS_YMMf32_MEMf16 =3332 ,
  XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =3333 ,
  XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =3334 ,
  XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =3335 ,
  XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =3336 ,
  XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =3337 ,
  XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =3338 ,
  XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =3339 ,
  XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =3340 ,
  XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =3341 ,
  XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =3342 ,
  XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =3343 ,
  XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =3344 ,
  XED_IFORM_VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb =3345 ,
  XED_IFORM_VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb =3346 ,
  XED_IFORM_VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb =3347 ,
  XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb =3348 ,
  XED_IFORM_VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb =3349 ,
  XED_IFORM_VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb =3350 ,
  XED_IFORM_VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb =3351 ,
  XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb =3352 ,
  XED_IFORM_VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq =3353 ,
  XED_IFORM_VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq =3354 ,
  XED_IFORM_VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq =3355 ,
  XED_IFORM_VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq =3356 ,
  XED_IFORM_VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq =3357 ,
  XED_IFORM_VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq =3358 ,
  XED_IFORM_VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq =3359 ,
  XED_IFORM_VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq =3360 ,
  XED_IFORM_VBROADCASTF128_YMMqq_MEMdq =3361 ,
  XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512 =3362 ,
  XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512 =3363 ,
  XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512 =3364 ,
  XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512 =3365 ,
  XED_IFORM_VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512 =3366 ,
  XED_IFORM_VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512 =3367 ,
  XED_IFORM_VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512 =3368 ,
  XED_IFORM_VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512 =3369 ,
  XED_IFORM_VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512 =3370 ,
  XED_IFORM_VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512 =3371 ,
  XED_IFORM_VBROADCASTI128_YMMqq_MEMdq =3372 ,
  XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512 =3373 ,
  XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512 =3374 ,
  XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512 =3375 ,
  XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512 =3376 ,
  XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512 =3377 ,
  XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512 =3378 ,
  XED_IFORM_VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512 =3379 ,
  XED_IFORM_VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512 =3380 ,
  XED_IFORM_VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512 =3381 ,
  XED_IFORM_VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512 =3382 ,
  XED_IFORM_VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512 =3383 ,
  XED_IFORM_VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512 =3384 ,
  XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512 =3385 ,
  XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512 =3386 ,
  XED_IFORM_VBROADCASTSD_YMMqq_MEMq =3387 ,
  XED_IFORM_VBROADCASTSD_YMMqq_XMMdq =3388 ,
  XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512 =3389 ,
  XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512 =3390 ,
  XED_IFORM_VBROADCASTSS_XMMdq_MEMd =3391 ,
  XED_IFORM_VBROADCASTSS_XMMdq_XMMdq =3392 ,
  XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512 =3393 ,
  XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512 =3394 ,
  XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512 =3395 ,
  XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512 =3396 ,
  XED_IFORM_VBROADCASTSS_YMMqq_MEMd =3397 ,
  XED_IFORM_VBROADCASTSS_YMMqq_XMMdq =3398 ,
  XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512 =3399 ,
  XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512 =3400 ,
  XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_XMMbf16_MEMbf16_IMM8_AVX512 =3401 ,
  XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_XMMbf16_XMMbf16_IMM8_AVX512 =3402 ,
  XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_YMMbf16_MEMbf16_IMM8_AVX512 =3403 ,
  XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_YMMbf16_YMMbf16_IMM8_AVX512 =3404 ,
  XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_ZMMbf16_MEMbf16_IMM8_AVX512 =3405 ,
  XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_ZMMbf16_ZMMbf16_IMM8_AVX512 =3406 ,
  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =3407 ,
  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =3408 ,
  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 =3409 ,
  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 =3410 ,
  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 =3411 ,
  XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 =3412 ,
  XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb =3413 ,
  XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb =3414 ,
  XED_IFORM_VCMPPD_YMMqq_YMMqq_MEMqq_IMMb =3415 ,
  XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb =3416 ,
  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 =3417 ,
  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 =3418 ,
  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512 =3419 ,
  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512 =3420 ,
  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512 =3421 ,
  XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512 =3422 ,
  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =3423 ,
  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =3424 ,
  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 =3425 ,
  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 =3426 ,
  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 =3427 ,
  XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 =3428 ,
  XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb =3429 ,
  XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb =3430 ,
  XED_IFORM_VCMPPS_YMMqq_YMMqq_MEMqq_IMMb =3431 ,
  XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb =3432 ,
  XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =3433 ,
  XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =3434 ,
  XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb =3435 ,
  XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb =3436 ,
  XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 =3437 ,
  XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 =3438 ,
  XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =3439 ,
  XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =3440 ,
  XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb =3441 ,
  XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb =3442 ,
  XED_IFORM_VCOMISBF16_XMMbf16_MEMbf16_AVX512 =3443 ,
  XED_IFORM_VCOMISBF16_XMMbf16_XMMbf16_AVX512 =3444 ,
  XED_IFORM_VCOMISD_XMMf64_MEMf64_AVX512 =3445 ,
  XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512 =3446 ,
  XED_IFORM_VCOMISD_XMMq_MEMq =3447 ,
  XED_IFORM_VCOMISD_XMMq_XMMq =3448 ,
  XED_IFORM_VCOMISH_XMMf16_MEMf16_AVX512 =3449 ,
  XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512 =3450 ,
  XED_IFORM_VCOMISS_XMMd_MEMd =3451 ,
  XED_IFORM_VCOMISS_XMMd_XMMd =3452 ,
  XED_IFORM_VCOMISS_XMMf32_MEMf32_AVX512 =3453 ,
  XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512 =3454 ,
  XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512 =3455 ,
  XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512 =3456 ,
  XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512 =3457 ,
  XED_IFORM_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512 =3458 ,
  XED_IFORM_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512 =3459 ,
  XED_IFORM_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512 =3460 ,
  XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512 =3461 ,
  XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512 =3462 ,
  XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512 =3463 ,
  XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512 =3464 ,
  XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512 =3465 ,
  XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512 =3466 ,
  XED_IFORM_VCOMXSD_XMMf64_MEMf64_AVX512 =3467 ,
  XED_IFORM_VCOMXSD_XMMf64_XMMf64_AVX512 =3468 ,
  XED_IFORM_VCOMXSH_XMMf16_MEMf16_AVX512 =3469 ,
  XED_IFORM_VCOMXSH_XMMf16_XMMf16_AVX512 =3470 ,
  XED_IFORM_VCOMXSS_XMMf32_MEMf32_AVX512 =3471 ,
  XED_IFORM_VCOMXSS_XMMf32_XMMf32_AVX512 =3472 ,
  XED_IFORM_VCVT2PH2BF8_XMMbf8_MASKmskw_XMMf16_MEMf16_AVX512 =3473 ,
  XED_IFORM_VCVT2PH2BF8_XMMbf8_MASKmskw_XMMf16_XMMf16_AVX512 =3474 ,
  XED_IFORM_VCVT2PH2BF8_YMMbf8_MASKmskw_YMMf16_MEMf16_AVX512 =3475 ,
  XED_IFORM_VCVT2PH2BF8_YMMbf8_MASKmskw_YMMf16_YMMf16_AVX512 =3476 ,
  XED_IFORM_VCVT2PH2BF8_ZMMbf8_MASKmskw_ZMMf16_MEMf16_AVX512 =3477 ,
  XED_IFORM_VCVT2PH2BF8_ZMMbf8_MASKmskw_ZMMf16_ZMMf16_AVX512 =3478 ,
  XED_IFORM_VCVT2PH2BF8S_XMMbf8_MASKmskw_XMMf16_MEMf16_AVX512 =3479 ,
  XED_IFORM_VCVT2PH2BF8S_XMMbf8_MASKmskw_XMMf16_XMMf16_AVX512 =3480 ,
  XED_IFORM_VCVT2PH2BF8S_YMMbf8_MASKmskw_YMMf16_MEMf16_AVX512 =3481 ,
  XED_IFORM_VCVT2PH2BF8S_YMMbf8_MASKmskw_YMMf16_YMMf16_AVX512 =3482 ,
  XED_IFORM_VCVT2PH2BF8S_ZMMbf8_MASKmskw_ZMMf16_MEMf16_AVX512 =3483 ,
  XED_IFORM_VCVT2PH2BF8S_ZMMbf8_MASKmskw_ZMMf16_ZMMf16_AVX512 =3484 ,
  XED_IFORM_VCVT2PH2HF8_XMMhf8_MASKmskw_XMMf16_MEMf16_AVX512 =3485 ,
  XED_IFORM_VCVT2PH2HF8_XMMhf8_MASKmskw_XMMf16_XMMf16_AVX512 =3486 ,
  XED_IFORM_VCVT2PH2HF8_YMMhf8_MASKmskw_YMMf16_MEMf16_AVX512 =3487 ,
  XED_IFORM_VCVT2PH2HF8_YMMhf8_MASKmskw_YMMf16_YMMf16_AVX512 =3488 ,
  XED_IFORM_VCVT2PH2HF8_ZMMhf8_MASKmskw_ZMMf16_MEMf16_AVX512 =3489 ,
  XED_IFORM_VCVT2PH2HF8_ZMMhf8_MASKmskw_ZMMf16_ZMMf16_AVX512 =3490 ,
  XED_IFORM_VCVT2PH2HF8S_XMMhf8_MASKmskw_XMMf16_MEMf16_AVX512 =3491 ,
  XED_IFORM_VCVT2PH2HF8S_XMMhf8_MASKmskw_XMMf16_XMMf16_AVX512 =3492 ,
  XED_IFORM_VCVT2PH2HF8S_YMMhf8_MASKmskw_YMMf16_MEMf16_AVX512 =3493 ,
  XED_IFORM_VCVT2PH2HF8S_YMMhf8_MASKmskw_YMMf16_YMMf16_AVX512 =3494 ,
  XED_IFORM_VCVT2PH2HF8S_ZMMhf8_MASKmskw_ZMMf16_MEMf16_AVX512 =3495 ,
  XED_IFORM_VCVT2PH2HF8S_ZMMhf8_MASKmskw_ZMMf16_ZMMf16_AVX512 =3496 ,
  XED_IFORM_VCVT2PS2PHX_XMMf16_MASKmskw_XMMf32_MEMf32_AVX512 =3497 ,
  XED_IFORM_VCVT2PS2PHX_XMMf16_MASKmskw_XMMf32_XMMf32_AVX512 =3498 ,
  XED_IFORM_VCVT2PS2PHX_YMMf16_MASKmskw_YMMf32_MEMf32_AVX512 =3499 ,
  XED_IFORM_VCVT2PS2PHX_YMMf16_MASKmskw_YMMf32_YMMf32_AVX512 =3500 ,
  XED_IFORM_VCVT2PS2PHX_ZMMf16_MASKmskw_ZMMf32_MEMf32_AVX512 =3501 ,
  XED_IFORM_VCVT2PS2PHX_ZMMf16_MASKmskw_ZMMf32_ZMMf32_AVX512 =3502 ,
  XED_IFORM_VCVTBF162IBS_XMMi8_MASKmskw_MEMbf16_AVX512 =3503 ,
  XED_IFORM_VCVTBF162IBS_XMMi8_MASKmskw_XMMbf16_AVX512 =3504 ,
  XED_IFORM_VCVTBF162IBS_YMMi8_MASKmskw_MEMbf16_AVX512 =3505 ,
  XED_IFORM_VCVTBF162IBS_YMMi8_MASKmskw_YMMbf16_AVX512 =3506 ,
  XED_IFORM_VCVTBF162IBS_ZMMi8_MASKmskw_MEMbf16_AVX512 =3507 ,
  XED_IFORM_VCVTBF162IBS_ZMMi8_MASKmskw_ZMMbf16_AVX512 =3508 ,
  XED_IFORM_VCVTBF162IUBS_XMMu8_MASKmskw_MEMbf16_AVX512 =3509 ,
  XED_IFORM_VCVTBF162IUBS_XMMu8_MASKmskw_XMMbf16_AVX512 =3510 ,
  XED_IFORM_VCVTBF162IUBS_YMMu8_MASKmskw_MEMbf16_AVX512 =3511 ,
  XED_IFORM_VCVTBF162IUBS_YMMu8_MASKmskw_YMMbf16_AVX512 =3512 ,
  XED_IFORM_VCVTBF162IUBS_ZMMu8_MASKmskw_MEMbf16_AVX512 =3513 ,
  XED_IFORM_VCVTBF162IUBS_ZMMu8_MASKmskw_ZMMbf16_AVX512 =3514 ,
  XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128 =3515 ,
  XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_XMM2i8_XMMf16_AVX512 =3516 ,
  XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256 =3517 ,
  XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_YMM2i8_YMMf16_AVX512 =3518 ,
  XED_IFORM_VCVTBIASPH2BF8_YMMbf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512 =3519 ,
  XED_IFORM_VCVTBIASPH2BF8_YMMbf8_MASKmskw_ZMM2i8_ZMMf16_AVX512 =3520 ,
  XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128 =3521 ,
  XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_XMM2i8_XMMf16_AVX512 =3522 ,
  XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256 =3523 ,
  XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_YMM2i8_YMMf16_AVX512 =3524 ,
  XED_IFORM_VCVTBIASPH2BF8S_YMMbf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512 =3525 ,
  XED_IFORM_VCVTBIASPH2BF8S_YMMbf8_MASKmskw_ZMM2i8_ZMMf16_AVX512 =3526 ,
  XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128 =3527 ,
  XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_XMM2i8_XMMf16_AVX512 =3528 ,
  XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256 =3529 ,
  XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_YMM2i8_YMMf16_AVX512 =3530 ,
  XED_IFORM_VCVTBIASPH2HF8_YMMhf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512 =3531 ,
  XED_IFORM_VCVTBIASPH2HF8_YMMhf8_MASKmskw_ZMM2i8_ZMMf16_AVX512 =3532 ,
  XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128 =3533 ,
  XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_XMM2i8_XMMf16_AVX512 =3534 ,
  XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256 =3535 ,
  XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_YMM2i8_YMMf16_AVX512 =3536 ,
  XED_IFORM_VCVTBIASPH2HF8S_YMMhf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512 =3537 ,
  XED_IFORM_VCVTBIASPH2HF8S_YMMhf8_MASKmskw_ZMM2i8_ZMMf16_AVX512 =3538 ,
  XED_IFORM_VCVTDQ2PD_XMMdq_MEMq =3539 ,
  XED_IFORM_VCVTDQ2PD_XMMdq_XMMq =3540 ,
  XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512 =3541 ,
  XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512 =3542 ,
  XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512 =3543 ,
  XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512 =3544 ,
  XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq =3545 ,
  XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq =3546 ,
  XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512 =3547 ,
  XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512 =3548 ,
  XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128 =3549 ,
  XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256 =3550 ,
  XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512 =3551 ,
  XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512 =3552 ,
  XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512 =3553 ,
  XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512 =3554 ,
  XED_IFORM_VCVTDQ2PS_XMMdq_MEMdq =3555 ,
  XED_IFORM_VCVTDQ2PS_XMMdq_XMMdq =3556 ,
  XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512 =3557 ,
  XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512 =3558 ,
  XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512 =3559 ,
  XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512 =3560 ,
  XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq =3561 ,
  XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq =3562 ,
  XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512 =3563 ,
  XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512 =3564 ,
  XED_IFORM_VCVTHF82PH_XMMf16_MASKmskw_MEMhf8_AVX512 =3565 ,
  XED_IFORM_VCVTHF82PH_XMMf16_MASKmskw_XMMhf8_AVX512 =3566 ,
  XED_IFORM_VCVTHF82PH_YMMf16_MASKmskw_MEMhf8_AVX512 =3567 ,
  XED_IFORM_VCVTHF82PH_YMMf16_MASKmskw_XMMhf8_AVX512 =3568 ,
  XED_IFORM_VCVTHF82PH_ZMMf16_MASKmskw_MEMhf8_AVX512 =3569 ,
  XED_IFORM_VCVTHF82PH_ZMMf16_MASKmskw_YMMhf8_AVX512 =3570 ,
  XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128 =3571 ,
  XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512 =3572 ,
  XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256 =3573 ,
  XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512 =3574 ,
  XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512 =3575 ,
  XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512 =3576 ,
  XED_IFORM_VCVTNEEBF162PS_XMMf32_MEM2bf16 =3577 ,
  XED_IFORM_VCVTNEEBF162PS_YMMf32_MEM2bf16 =3578 ,
  XED_IFORM_VCVTNEEPH2PS_XMMf32_MEM2f16 =3579 ,
  XED_IFORM_VCVTNEEPH2PS_YMMf32_MEM2f16 =3580 ,
  XED_IFORM_VCVTNEOBF162PS_XMMf32_MEM2bf16 =3581 ,
  XED_IFORM_VCVTNEOBF162PS_YMMf32_MEM2bf16 =3582 ,
  XED_IFORM_VCVTNEOPH2PS_XMMf32_MEM2f16 =3583 ,
  XED_IFORM_VCVTNEOPH2PS_YMMf32_MEM2f16 =3584 ,
  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128 =3585 ,
  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256 =3586 ,
  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512 =3587 ,
  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512 =3588 ,
  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MEMf32_VL128 =3589 ,
  XED_IFORM_VCVTNEPS2BF16_XMMbf16_MEMf32_VL256 =3590 ,
  XED_IFORM_VCVTNEPS2BF16_XMMbf16_XMMf32 =3591 ,
  XED_IFORM_VCVTNEPS2BF16_XMMbf16_YMMf32 =3592 ,
  XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512 =3593 ,
  XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512 =3594 ,
  XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq =3595 ,
  XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq =3596 ,
  XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq =3597 ,
  XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq =3598 ,
  XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 =3599 ,
  XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 =3600 ,
  XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 =3601 ,
  XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 =3602 ,
  XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 =3603 ,
  XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 =3604 ,
  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128 =3605 ,
  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256 =3606 ,
  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512 =3607 ,
  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512 =3608 ,
  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512 =3609 ,
  XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512 =3610 ,
  XED_IFORM_VCVTPD2PS_XMMdq_MEMdq =3611 ,
  XED_IFORM_VCVTPD2PS_XMMdq_MEMqq =3612 ,
  XED_IFORM_VCVTPD2PS_XMMdq_XMMdq =3613 ,
  XED_IFORM_VCVTPD2PS_XMMdq_YMMqq =3614 ,
  XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128 =3615 ,
  XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256 =3616 ,
  XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128 =3617 ,
  XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256 =3618 ,
  XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512 =3619 ,
  XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512 =3620 ,
  XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 =3621 ,
  XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 =3622 ,
  XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 =3623 ,
  XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 =3624 ,
  XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 =3625 ,
  XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 =3626 ,
  XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 =3627 ,
  XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 =3628 ,
  XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 =3629 ,
  XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 =3630 ,
  XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 =3631 ,
  XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 =3632 ,
  XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 =3633 ,
  XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 =3634 ,
  XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 =3635 ,
  XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 =3636 ,
  XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 =3637 ,
  XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 =3638 ,
  XED_IFORM_VCVTPH2BF8_XMMbf8_MASKmskw_MEMf16_AVX512_VL128 =3639 ,
  XED_IFORM_VCVTPH2BF8_XMMbf8_MASKmskw_MEMf16_AVX512_VL256 =3640 ,
  XED_IFORM_VCVTPH2BF8_XMMbf8_MASKmskw_XMMf16_AVX512 =3641 ,
  XED_IFORM_VCVTPH2BF8_XMMbf8_MASKmskw_YMMf16_AVX512 =3642 ,
  XED_IFORM_VCVTPH2BF8_YMMbf8_MASKmskw_MEMf16_AVX512_VL512 =3643 ,
  XED_IFORM_VCVTPH2BF8_YMMbf8_MASKmskw_ZMMf16_AVX512 =3644 ,
  XED_IFORM_VCVTPH2BF8S_XMMbf8_MASKmskw_MEMf16_AVX512_VL128 =3645 ,
  XED_IFORM_VCVTPH2BF8S_XMMbf8_MASKmskw_MEMf16_AVX512_VL256 =3646 ,
  XED_IFORM_VCVTPH2BF8S_XMMbf8_MASKmskw_XMMf16_AVX512 =3647 ,
  XED_IFORM_VCVTPH2BF8S_XMMbf8_MASKmskw_YMMf16_AVX512 =3648 ,
  XED_IFORM_VCVTPH2BF8S_YMMbf8_MASKmskw_MEMf16_AVX512_VL512 =3649 ,
  XED_IFORM_VCVTPH2BF8S_YMMbf8_MASKmskw_ZMMf16_AVX512 =3650 ,
  XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512 =3651 ,
  XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512 =3652 ,
  XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512 =3653 ,
  XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512 =3654 ,
  XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512 =3655 ,
  XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 =3656 ,
  XED_IFORM_VCVTPH2HF8_XMMhf8_MASKmskw_MEMf16_AVX512_VL128 =3657 ,
  XED_IFORM_VCVTPH2HF8_XMMhf8_MASKmskw_MEMf16_AVX512_VL256 =3658 ,
  XED_IFORM_VCVTPH2HF8_XMMhf8_MASKmskw_XMMf16_AVX512 =3659 ,
  XED_IFORM_VCVTPH2HF8_XMMhf8_MASKmskw_YMMf16_AVX512 =3660 ,
  XED_IFORM_VCVTPH2HF8_YMMhf8_MASKmskw_MEMf16_AVX512_VL512 =3661 ,
  XED_IFORM_VCVTPH2HF8_YMMhf8_MASKmskw_ZMMf16_AVX512 =3662 ,
  XED_IFORM_VCVTPH2HF8S_XMMhf8_MASKmskw_MEMf16_AVX512_VL128 =3663 ,
  XED_IFORM_VCVTPH2HF8S_XMMhf8_MASKmskw_MEMf16_AVX512_VL256 =3664 ,
  XED_IFORM_VCVTPH2HF8S_XMMhf8_MASKmskw_XMMf16_AVX512 =3665 ,
  XED_IFORM_VCVTPH2HF8S_XMMhf8_MASKmskw_YMMf16_AVX512 =3666 ,
  XED_IFORM_VCVTPH2HF8S_YMMhf8_MASKmskw_MEMf16_AVX512_VL512 =3667 ,
  XED_IFORM_VCVTPH2HF8S_YMMhf8_MASKmskw_ZMMf16_AVX512 =3668 ,
  XED_IFORM_VCVTPH2IBS_XMMi8_MASKmskw_MEMf16_AVX512 =3669 ,
  XED_IFORM_VCVTPH2IBS_XMMi8_MASKmskw_XMMf16_AVX512 =3670 ,
  XED_IFORM_VCVTPH2IBS_YMMi8_MASKmskw_MEMf16_AVX512 =3671 ,
  XED_IFORM_VCVTPH2IBS_YMMi8_MASKmskw_YMMf16_AVX512 =3672 ,
  XED_IFORM_VCVTPH2IBS_ZMMi8_MASKmskw_MEMf16_AVX512 =3673 ,
  XED_IFORM_VCVTPH2IBS_ZMMi8_MASKmskw_ZMMf16_AVX512 =3674 ,
  XED_IFORM_VCVTPH2IUBS_XMMu8_MASKmskw_MEMf16_AVX512 =3675 ,
  XED_IFORM_VCVTPH2IUBS_XMMu8_MASKmskw_XMMf16_AVX512 =3676 ,
  XED_IFORM_VCVTPH2IUBS_YMMu8_MASKmskw_MEMf16_AVX512 =3677 ,
  XED_IFORM_VCVTPH2IUBS_YMMu8_MASKmskw_YMMf16_AVX512 =3678 ,
  XED_IFORM_VCVTPH2IUBS_ZMMu8_MASKmskw_MEMf16_AVX512 =3679 ,
  XED_IFORM_VCVTPH2IUBS_ZMMu8_MASKmskw_ZMMf16_AVX512 =3680 ,
  XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512 =3681 ,
  XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512 =3682 ,
  XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512 =3683 ,
  XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512 =3684 ,
  XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512 =3685 ,
  XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512 =3686 ,
  XED_IFORM_VCVTPH2PS_XMMdq_MEMq =3687 ,
  XED_IFORM_VCVTPH2PS_XMMdq_XMMq =3688 ,
  XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512 =3689 ,
  XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512 =3690 ,
  XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512 =3691 ,
  XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512 =3692 ,
  XED_IFORM_VCVTPH2PS_YMMqq_MEMdq =3693 ,
  XED_IFORM_VCVTPH2PS_YMMqq_XMMdq =3694 ,
  XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512 =3695 ,
  XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512 =3696 ,
  XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512 =3697 ,
  XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512 =3698 ,
  XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512 =3699 ,
  XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512 =3700 ,
  XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512 =3701 ,
  XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512 =3702 ,
  XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512 =3703 ,
  XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512 =3704 ,
  XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512 =3705 ,
  XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512 =3706 ,
  XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512 =3707 ,
  XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 =3708 ,
  XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512 =3709 ,
  XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512 =3710 ,
  XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512 =3711 ,
  XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512 =3712 ,
  XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512 =3713 ,
  XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 =3714 ,
  XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512 =3715 ,
  XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512 =3716 ,
  XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512 =3717 ,
  XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512 =3718 ,
  XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512 =3719 ,
  XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 =3720 ,
  XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512 =3721 ,
  XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512 =3722 ,
  XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512 =3723 ,
  XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512 =3724 ,
  XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512 =3725 ,
  XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 =3726 ,
  XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512 =3727 ,
  XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512 =3728 ,
  XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512 =3729 ,
  XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512 =3730 ,
  XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512 =3731 ,
  XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 =3732 ,
  XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq =3733 ,
  XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq =3734 ,
  XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 =3735 ,
  XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 =3736 ,
  XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 =3737 ,
  XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 =3738 ,
  XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq =3739 ,
  XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq =3740 ,
  XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 =3741 ,
  XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 =3742 ,
  XED_IFORM_VCVTPS2IBS_XMMi8_MASKmskw_MEMf32_AVX512 =3743 ,
  XED_IFORM_VCVTPS2IBS_XMMi8_MASKmskw_XMMf32_AVX512 =3744 ,
  XED_IFORM_VCVTPS2IBS_YMMi8_MASKmskw_MEMf32_AVX512 =3745 ,
  XED_IFORM_VCVTPS2IBS_YMMi8_MASKmskw_YMMf32_AVX512 =3746 ,
  XED_IFORM_VCVTPS2IBS_ZMMi8_MASKmskw_MEMf32_AVX512 =3747 ,
  XED_IFORM_VCVTPS2IBS_ZMMi8_MASKmskw_ZMMf32_AVX512 =3748 ,
  XED_IFORM_VCVTPS2IUBS_XMMu8_MASKmskw_MEMf32_AVX512 =3749 ,
  XED_IFORM_VCVTPS2IUBS_XMMu8_MASKmskw_XMMf32_AVX512 =3750 ,
  XED_IFORM_VCVTPS2IUBS_YMMu8_MASKmskw_MEMf32_AVX512 =3751 ,
  XED_IFORM_VCVTPS2IUBS_YMMu8_MASKmskw_YMMf32_AVX512 =3752 ,
  XED_IFORM_VCVTPS2IUBS_ZMMu8_MASKmskw_MEMf32_AVX512 =3753 ,
  XED_IFORM_VCVTPS2IUBS_ZMMu8_MASKmskw_ZMMf32_AVX512 =3754 ,
  XED_IFORM_VCVTPS2PD_XMMdq_MEMq =3755 ,
  XED_IFORM_VCVTPS2PD_XMMdq_XMMq =3756 ,
  XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512 =3757 ,
  XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512 =3758 ,
  XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512 =3759 ,
  XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512 =3760 ,
  XED_IFORM_VCVTPS2PD_YMMqq_MEMdq =3761 ,
  XED_IFORM_VCVTPS2PD_YMMqq_XMMdq =3762 ,
  XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512 =3763 ,
  XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512 =3764 ,
  XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb =3765 ,
  XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512 =3766 ,
  XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512 =3767 ,
  XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512 =3768 ,
  XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb =3769 ,
  XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb =3770 ,
  XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512 =3771 ,
  XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512 =3772 ,
  XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb =3773 ,
  XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512 =3774 ,
  XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128 =3775 ,
  XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256 =3776 ,
  XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512 =3777 ,
  XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512 =3778 ,
  XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512 =3779 ,
  XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512 =3780 ,
  XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 =3781 ,
  XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 =3782 ,
  XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 =3783 ,
  XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 =3784 ,
  XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 =3785 ,
  XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 =3786 ,
  XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 =3787 ,
  XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 =3788 ,
  XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 =3789 ,
  XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 =3790 ,
  XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 =3791 ,
  XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 =3792 ,
  XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 =3793 ,
  XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 =3794 ,
  XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 =3795 ,
  XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 =3796 ,
  XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 =3797 ,
  XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 =3798 ,
  XED_IFORM_VCVTQQ2PD_XMMf64_MASKmskw_MEMi64_AVX512 =3799 ,
  XED_IFORM_VCVTQQ2PD_XMMf64_MASKmskw_XMMi64_AVX512 =3800 ,
  XED_IFORM_VCVTQQ2PD_YMMf64_MASKmskw_MEMi64_AVX512 =3801 ,
  XED_IFORM_VCVTQQ2PD_YMMf64_MASKmskw_YMMi64_AVX512 =3802 ,
  XED_IFORM_VCVTQQ2PD_ZMMf64_MASKmskw_MEMi64_AVX512 =3803 ,
  XED_IFORM_VCVTQQ2PD_ZMMf64_MASKmskw_ZMMi64_AVX512 =3804 ,
  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128 =3805 ,
  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256 =3806 ,
  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512 =3807 ,
  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512 =3808 ,
  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512 =3809 ,
  XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 =3810 ,
  XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 =3811 ,
  XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 =3812 ,
  XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 =3813 ,
  XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 =3814 ,
  XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 =3815 ,
  XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 =3816 ,
  XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512 =3817 ,
  XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512 =3818 ,
  XED_IFORM_VCVTSD2SI_GPR32d_MEMq =3819 ,
  XED_IFORM_VCVTSD2SI_GPR32d_XMMq =3820 ,
  XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512 =3821 ,
  XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512 =3822 ,
  XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512 =3823 ,
  XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512 =3824 ,
  XED_IFORM_VCVTSD2SI_GPR64q_MEMq =3825 ,
  XED_IFORM_VCVTSD2SI_GPR64q_XMMq =3826 ,
  XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq =3827 ,
  XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq =3828 ,
  XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512 =3829 ,
  XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512 =3830 ,
  XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512 =3831 ,
  XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512 =3832 ,
  XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512 =3833 ,
  XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512 =3834 ,
  XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512 =3835 ,
  XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512 =3836 ,
  XED_IFORM_VCVTSH2SI_GPR32i32_MEMf16_AVX512 =3837 ,
  XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512 =3838 ,
  XED_IFORM_VCVTSH2SI_GPR64i64_MEMf16_AVX512 =3839 ,
  XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512 =3840 ,
  XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512 =3841 ,
  XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512 =3842 ,
  XED_IFORM_VCVTSH2USI_GPR32u32_MEMf16_AVX512 =3843 ,
  XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512 =3844 ,
  XED_IFORM_VCVTSH2USI_GPR64u64_MEMf16_AVX512 =3845 ,
  XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512 =3846 ,
  XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d =3847 ,
  XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q =3848 ,
  XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd =3849 ,
  XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq =3850 ,
  XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512 =3851 ,
  XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512 =3852 ,
  XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512 =3853 ,
  XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512 =3854 ,
  XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512 =3855 ,
  XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512 =3856 ,
  XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512 =3857 ,
  XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512 =3858 ,
  XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d =3859 ,
  XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q =3860 ,
  XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd =3861 ,
  XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq =3862 ,
  XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 =3863 ,
  XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512 =3864 ,
  XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512 =3865 ,
  XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512 =3866 ,
  XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd =3867 ,
  XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd =3868 ,
  XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512 =3869 ,
  XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512 =3870 ,
  XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512 =3871 ,
  XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512 =3872 ,
  XED_IFORM_VCVTSS2SI_GPR32d_MEMd =3873 ,
  XED_IFORM_VCVTSS2SI_GPR32d_XMMd =3874 ,
  XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512 =3875 ,
  XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512 =3876 ,
  XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512 =3877 ,
  XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512 =3878 ,
  XED_IFORM_VCVTSS2SI_GPR64q_MEMd =3879 ,
  XED_IFORM_VCVTSS2SI_GPR64q_XMMd =3880 ,
  XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512 =3881 ,
  XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512 =3882 ,
  XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512 =3883 ,
  XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512 =3884 ,
  XED_IFORM_VCVTTBF162IBS_XMMi8_MASKmskw_MEMbf16_AVX512 =3885 ,
  XED_IFORM_VCVTTBF162IBS_XMMi8_MASKmskw_XMMbf16_AVX512 =3886 ,
  XED_IFORM_VCVTTBF162IBS_YMMi8_MASKmskw_MEMbf16_AVX512 =3887 ,
  XED_IFORM_VCVTTBF162IBS_YMMi8_MASKmskw_YMMbf16_AVX512 =3888 ,
  XED_IFORM_VCVTTBF162IBS_ZMMi8_MASKmskw_MEMbf16_AVX512 =3889 ,
  XED_IFORM_VCVTTBF162IBS_ZMMi8_MASKmskw_ZMMbf16_AVX512 =3890 ,
  XED_IFORM_VCVTTBF162IUBS_XMMu8_MASKmskw_MEMbf16_AVX512 =3891 ,
  XED_IFORM_VCVTTBF162IUBS_XMMu8_MASKmskw_XMMbf16_AVX512 =3892 ,
  XED_IFORM_VCVTTBF162IUBS_YMMu8_MASKmskw_MEMbf16_AVX512 =3893 ,
  XED_IFORM_VCVTTBF162IUBS_YMMu8_MASKmskw_YMMbf16_AVX512 =3894 ,
  XED_IFORM_VCVTTBF162IUBS_ZMMu8_MASKmskw_MEMbf16_AVX512 =3895 ,
  XED_IFORM_VCVTTBF162IUBS_ZMMu8_MASKmskw_ZMMbf16_AVX512 =3896 ,
  XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq =3897 ,
  XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq =3898 ,
  XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq =3899 ,
  XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq =3900 ,
  XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 =3901 ,
  XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 =3902 ,
  XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 =3903 ,
  XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 =3904 ,
  XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 =3905 ,
  XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 =3906 ,
  XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_MEMf64_AVX512_VL128 =3907 ,
  XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_MEMf64_AVX512_VL256 =3908 ,
  XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_XMMf64_AVX512 =3909 ,
  XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_YMMf64_AVX512 =3910 ,
  XED_IFORM_VCVTTPD2DQS_YMMi32_MASKmskw_MEMf64_AVX512_VL512 =3911 ,
  XED_IFORM_VCVTTPD2DQS_YMMi32_MASKmskw_ZMMf64_AVX512 =3912 ,
  XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 =3913 ,
  XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 =3914 ,
  XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 =3915 ,
  XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 =3916 ,
  XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 =3917 ,
  XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 =3918 ,
  XED_IFORM_VCVTTPD2QQS_XMMi64_MASKmskw_MEMf64_AVX512 =3919 ,
  XED_IFORM_VCVTTPD2QQS_XMMi64_MASKmskw_XMMf64_AVX512 =3920 ,
  XED_IFORM_VCVTTPD2QQS_YMMi64_MASKmskw_MEMf64_AVX512 =3921 ,
  XED_IFORM_VCVTTPD2QQS_YMMi64_MASKmskw_YMMf64_AVX512 =3922 ,
  XED_IFORM_VCVTTPD2QQS_ZMMi64_MASKmskw_MEMf64_AVX512 =3923 ,
  XED_IFORM_VCVTTPD2QQS_ZMMi64_MASKmskw_ZMMf64_AVX512 =3924 ,
  XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 =3925 ,
  XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 =3926 ,
  XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 =3927 ,
  XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 =3928 ,
  XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 =3929 ,
  XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 =3930 ,
  XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_MEMf64_AVX512_VL128 =3931 ,
  XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_MEMf64_AVX512_VL256 =3932 ,
  XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_XMMf64_AVX512 =3933 ,
  XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_YMMf64_AVX512 =3934 ,
  XED_IFORM_VCVTTPD2UDQS_YMMu32_MASKmskw_MEMf64_AVX512_VL512 =3935 ,
  XED_IFORM_VCVTTPD2UDQS_YMMu32_MASKmskw_ZMMf64_AVX512 =3936 ,
  XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 =3937 ,
  XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 =3938 ,
  XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 =3939 ,
  XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 =3940 ,
  XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 =3941 ,
  XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 =3942 ,
  XED_IFORM_VCVTTPD2UQQS_XMMu64_MASKmskw_MEMf64_AVX512 =3943 ,
  XED_IFORM_VCVTTPD2UQQS_XMMu64_MASKmskw_XMMf64_AVX512 =3944 ,
  XED_IFORM_VCVTTPD2UQQS_YMMu64_MASKmskw_MEMf64_AVX512 =3945 ,
  XED_IFORM_VCVTTPD2UQQS_YMMu64_MASKmskw_YMMf64_AVX512 =3946 ,
  XED_IFORM_VCVTTPD2UQQS_ZMMu64_MASKmskw_MEMf64_AVX512 =3947 ,
  XED_IFORM_VCVTTPD2UQQS_ZMMu64_MASKmskw_ZMMf64_AVX512 =3948 ,
  XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512 =3949 ,
  XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512 =3950 ,
  XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512 =3951 ,
  XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512 =3952 ,
  XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512 =3953 ,
  XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 =3954 ,
  XED_IFORM_VCVTTPH2IBS_XMMi8_MASKmskw_MEMf16_AVX512 =3955 ,
  XED_IFORM_VCVTTPH2IBS_XMMi8_MASKmskw_XMMf16_AVX512 =3956 ,
  XED_IFORM_VCVTTPH2IBS_YMMi8_MASKmskw_MEMf16_AVX512 =3957 ,
  XED_IFORM_VCVTTPH2IBS_YMMi8_MASKmskw_YMMf16_AVX512 =3958 ,
  XED_IFORM_VCVTTPH2IBS_ZMMi8_MASKmskw_MEMf16_AVX512 =3959 ,
  XED_IFORM_VCVTTPH2IBS_ZMMi8_MASKmskw_ZMMf16_AVX512 =3960 ,
  XED_IFORM_VCVTTPH2IUBS_XMMu8_MASKmskw_MEMf16_AVX512 =3961 ,
  XED_IFORM_VCVTTPH2IUBS_XMMu8_MASKmskw_XMMf16_AVX512 =3962 ,
  XED_IFORM_VCVTTPH2IUBS_YMMu8_MASKmskw_MEMf16_AVX512 =3963 ,
  XED_IFORM_VCVTTPH2IUBS_YMMu8_MASKmskw_YMMf16_AVX512 =3964 ,
  XED_IFORM_VCVTTPH2IUBS_ZMMu8_MASKmskw_MEMf16_AVX512 =3965 ,
  XED_IFORM_VCVTTPH2IUBS_ZMMu8_MASKmskw_ZMMf16_AVX512 =3966 ,
  XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512 =3967 ,
  XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512 =3968 ,
  XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512 =3969 ,
  XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512 =3970 ,
  XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512 =3971 ,
  XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 =3972 ,
  XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512 =3973 ,
  XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512 =3974 ,
  XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512 =3975 ,
  XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512 =3976 ,
  XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512 =3977 ,
  XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 =3978 ,
  XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512 =3979 ,
  XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512 =3980 ,
  XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512 =3981 ,
  XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512 =3982 ,
  XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512 =3983 ,
  XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 =3984 ,
  XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512 =3985 ,
  XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512 =3986 ,
  XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512 =3987 ,
  XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512 =3988 ,
  XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512 =3989 ,
  XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 =3990 ,
  XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512 =3991 ,
  XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512 =3992 ,
  XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512 =3993 ,
  XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512 =3994 ,
  XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512 =3995 ,
  XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 =3996 ,
  XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq =3997 ,
  XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq =3998 ,
  XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 =3999 ,
  XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 =4000 ,
  XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 =4001 ,
  XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 =4002 ,
  XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq =4003 ,
  XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq =4004 ,
  XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 =4005 ,
  XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 =4006 ,
  XED_IFORM_VCVTTPS2DQS_XMMi32_MASKmskw_MEMf32_AVX512 =4007 ,
  XED_IFORM_VCVTTPS2DQS_XMMi32_MASKmskw_XMMf32_AVX512 =4008 ,
  XED_IFORM_VCVTTPS2DQS_YMMi32_MASKmskw_MEMf32_AVX512 =4009 ,
  XED_IFORM_VCVTTPS2DQS_YMMi32_MASKmskw_YMMf32_AVX512 =4010 ,
  XED_IFORM_VCVTTPS2DQS_ZMMi32_MASKmskw_MEMf32_AVX512 =4011 ,
  XED_IFORM_VCVTTPS2DQS_ZMMi32_MASKmskw_ZMMf32_AVX512 =4012 ,
  XED_IFORM_VCVTTPS2IBS_XMMi8_MASKmskw_MEMf32_AVX512 =4013 ,
  XED_IFORM_VCVTTPS2IBS_XMMi8_MASKmskw_XMMf32_AVX512 =4014 ,
  XED_IFORM_VCVTTPS2IBS_YMMi8_MASKmskw_MEMf32_AVX512 =4015 ,
  XED_IFORM_VCVTTPS2IBS_YMMi8_MASKmskw_YMMf32_AVX512 =4016 ,
  XED_IFORM_VCVTTPS2IBS_ZMMi8_MASKmskw_MEMf32_AVX512 =4017 ,
  XED_IFORM_VCVTTPS2IBS_ZMMi8_MASKmskw_ZMMf32_AVX512 =4018 ,
  XED_IFORM_VCVTTPS2IUBS_XMMu8_MASKmskw_MEMf32_AVX512 =4019 ,
  XED_IFORM_VCVTTPS2IUBS_XMMu8_MASKmskw_XMMf32_AVX512 =4020 ,
  XED_IFORM_VCVTTPS2IUBS_YMMu8_MASKmskw_MEMf32_AVX512 =4021 ,
  XED_IFORM_VCVTTPS2IUBS_YMMu8_MASKmskw_YMMf32_AVX512 =4022 ,
  XED_IFORM_VCVTTPS2IUBS_ZMMu8_MASKmskw_MEMf32_AVX512 =4023 ,
  XED_IFORM_VCVTTPS2IUBS_ZMMu8_MASKmskw_ZMMf32_AVX512 =4024 ,
  XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 =4025 ,
  XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 =4026 ,
  XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 =4027 ,
  XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 =4028 ,
  XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 =4029 ,
  XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 =4030 ,
  XED_IFORM_VCVTTPS2QQS_XMMi64_MASKmskw_MEMf32_AVX512 =4031 ,
  XED_IFORM_VCVTTPS2QQS_XMMi64_MASKmskw_XMMf32_AVX512 =4032 ,
  XED_IFORM_VCVTTPS2QQS_YMMi64_MASKmskw_MEMf32_AVX512 =4033 ,
  XED_IFORM_VCVTTPS2QQS_YMMi64_MASKmskw_XMMf32_AVX512 =4034 ,
  XED_IFORM_VCVTTPS2QQS_ZMMi64_MASKmskw_MEMf32_AVX512 =4035 ,
  XED_IFORM_VCVTTPS2QQS_ZMMi64_MASKmskw_YMMf32_AVX512 =4036 ,
  XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 =4037 ,
  XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 =4038 ,
  XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 =4039 ,
  XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 =4040 ,
  XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 =4041 ,
  XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 =4042 ,
  XED_IFORM_VCVTTPS2UDQS_XMMu32_MASKmskw_MEMf32_AVX512 =4043 ,
  XED_IFORM_VCVTTPS2UDQS_XMMu32_MASKmskw_XMMf32_AVX512 =4044 ,
  XED_IFORM_VCVTTPS2UDQS_YMMu32_MASKmskw_MEMf32_AVX512 =4045 ,
  XED_IFORM_VCVTTPS2UDQS_YMMu32_MASKmskw_YMMf32_AVX512 =4046 ,
  XED_IFORM_VCVTTPS2UDQS_ZMMu32_MASKmskw_MEMf32_AVX512 =4047 ,
  XED_IFORM_VCVTTPS2UDQS_ZMMu32_MASKmskw_ZMMf32_AVX512 =4048 ,
  XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 =4049 ,
  XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 =4050 ,
  XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 =4051 ,
  XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 =4052 ,
  XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 =4053 ,
  XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 =4054 ,
  XED_IFORM_VCVTTPS2UQQS_XMMu64_MASKmskw_MEMf32_AVX512 =4055 ,
  XED_IFORM_VCVTTPS2UQQS_XMMu64_MASKmskw_XMMf32_AVX512 =4056 ,
  XED_IFORM_VCVTTPS2UQQS_YMMu64_MASKmskw_MEMf32_AVX512 =4057 ,
  XED_IFORM_VCVTTPS2UQQS_YMMu64_MASKmskw_XMMf32_AVX512 =4058 ,
  XED_IFORM_VCVTTPS2UQQS_ZMMu64_MASKmskw_MEMf32_AVX512 =4059 ,
  XED_IFORM_VCVTTPS2UQQS_ZMMu64_MASKmskw_YMMf32_AVX512 =4060 ,
  XED_IFORM_VCVTTSD2SI_GPR32d_MEMq =4061 ,
  XED_IFORM_VCVTTSD2SI_GPR32d_XMMq =4062 ,
  XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512 =4063 ,
  XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512 =4064 ,
  XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512 =4065 ,
  XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512 =4066 ,
  XED_IFORM_VCVTTSD2SI_GPR64q_MEMq =4067 ,
  XED_IFORM_VCVTTSD2SI_GPR64q_XMMq =4068 ,
  XED_IFORM_VCVTTSD2SIS_GPR32i32_MEMf64_AVX512 =4069 ,
  XED_IFORM_VCVTTSD2SIS_GPR32i32_XMMf64_AVX512 =4070 ,
  XED_IFORM_VCVTTSD2SIS_GPR64i64_MEMf64_AVX512 =4071 ,
  XED_IFORM_VCVTTSD2SIS_GPR64i64_XMMf64_AVX512 =4072 ,
  XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512 =4073 ,
  XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512 =4074 ,
  XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512 =4075 ,
  XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512 =4076 ,
  XED_IFORM_VCVTTSD2USIS_GPR32u32_MEMf64_AVX512 =4077 ,
  XED_IFORM_VCVTTSD2USIS_GPR32u32_XMMf64_AVX512 =4078 ,
  XED_IFORM_VCVTTSD2USIS_GPR64u64_MEMf64_AVX512 =4079 ,
  XED_IFORM_VCVTTSD2USIS_GPR64u64_XMMf64_AVX512 =4080 ,
  XED_IFORM_VCVTTSH2SI_GPR32i32_MEMf16_AVX512 =4081 ,
  XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512 =4082 ,
  XED_IFORM_VCVTTSH2SI_GPR64i64_MEMf16_AVX512 =4083 ,
  XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512 =4084 ,
  XED_IFORM_VCVTTSH2USI_GPR32u32_MEMf16_AVX512 =4085 ,
  XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512 =4086 ,
  XED_IFORM_VCVTTSH2USI_GPR64u64_MEMf16_AVX512 =4087 ,
  XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512 =4088 ,
  XED_IFORM_VCVTTSS2SI_GPR32d_MEMd =4089 ,
  XED_IFORM_VCVTTSS2SI_GPR32d_XMMd =4090 ,
  XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512 =4091 ,
  XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512 =4092 ,
  XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512 =4093 ,
  XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512 =4094 ,
  XED_IFORM_VCVTTSS2SI_GPR64q_MEMd =4095 ,
  XED_IFORM_VCVTTSS2SI_GPR64q_XMMd =4096 ,
  XED_IFORM_VCVTTSS2SIS_GPR32i32_MEMf32_AVX512 =4097 ,
  XED_IFORM_VCVTTSS2SIS_GPR32i32_XMMf32_AVX512 =4098 ,
  XED_IFORM_VCVTTSS2SIS_GPR64i64_MEMf32_AVX512 =4099 ,
  XED_IFORM_VCVTTSS2SIS_GPR64i64_XMMf32_AVX512 =4100 ,
  XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512 =4101 ,
  XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512 =4102 ,
  XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512 =4103 ,
  XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512 =4104 ,
  XED_IFORM_VCVTTSS2USIS_GPR32u32_MEMf32_AVX512 =4105 ,
  XED_IFORM_VCVTTSS2USIS_GPR32u32_XMMf32_AVX512 =4106 ,
  XED_IFORM_VCVTTSS2USIS_GPR64u64_MEMf32_AVX512 =4107 ,
  XED_IFORM_VCVTTSS2USIS_GPR64u64_XMMf32_AVX512 =4108 ,
  XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512 =4109 ,
  XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512 =4110 ,
  XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512 =4111 ,
  XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512 =4112 ,
  XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512 =4113 ,
  XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512 =4114 ,
  XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128 =4115 ,
  XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256 =4116 ,
  XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512 =4117 ,
  XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512 =4118 ,
  XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512 =4119 ,
  XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512 =4120 ,
  XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512 =4121 ,
  XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512 =4122 ,
  XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512 =4123 ,
  XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512 =4124 ,
  XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512 =4125 ,
  XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512 =4126 ,
  XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512 =4127 ,
  XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512 =4128 ,
  XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512 =4129 ,
  XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512 =4130 ,
  XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512 =4131 ,
  XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512 =4132 ,
  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128 =4133 ,
  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256 =4134 ,
  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512 =4135 ,
  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512 =4136 ,
  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512 =4137 ,
  XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 =4138 ,
  XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 =4139 ,
  XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 =4140 ,
  XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 =4141 ,
  XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 =4142 ,
  XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 =4143 ,
  XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 =4144 ,
  XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512 =4145 ,
  XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512 =4146 ,
  XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512 =4147 ,
  XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512 =4148 ,
  XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512 =4149 ,
  XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512 =4150 ,
  XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512 =4151 ,
  XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512 =4152 ,
  XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 =4153 ,
  XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512 =4154 ,
  XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512 =4155 ,
  XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512 =4156 ,
  XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512 =4157 ,
  XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512 =4158 ,
  XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512 =4159 ,
  XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512 =4160 ,
  XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512 =4161 ,
  XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512 =4162 ,
  XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512 =4163 ,
  XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512 =4164 ,
  XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512 =4165 ,
  XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512 =4166 ,
  XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512 =4167 ,
  XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512 =4168 ,
  XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 =4169 ,
  XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 =4170 ,
  XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 =4171 ,
  XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 =4172 ,
  XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 =4173 ,
  XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 =4174 ,
  XED_IFORM_VDIVBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =4175 ,
  XED_IFORM_VDIVBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =4176 ,
  XED_IFORM_VDIVBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =4177 ,
  XED_IFORM_VDIVBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =4178 ,
  XED_IFORM_VDIVBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =4179 ,
  XED_IFORM_VDIVBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =4180 ,
  XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq =4181 ,
  XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq =4182 ,
  XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4183 ,
  XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4184 ,
  XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4185 ,
  XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4186 ,
  XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq =4187 ,
  XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq =4188 ,
  XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4189 ,
  XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4190 ,
  XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4191 ,
  XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4192 ,
  XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4193 ,
  XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4194 ,
  XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4195 ,
  XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4196 ,
  XED_IFORM_VDIVPS_XMMdq_XMMdq_MEMdq =4197 ,
  XED_IFORM_VDIVPS_XMMdq_XMMdq_XMMdq =4198 ,
  XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4199 ,
  XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4200 ,
  XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4201 ,
  XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4202 ,
  XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq =4203 ,
  XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq =4204 ,
  XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4205 ,
  XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4206 ,
  XED_IFORM_VDIVSD_XMMdq_XMMdq_MEMq =4207 ,
  XED_IFORM_VDIVSD_XMMdq_XMMdq_XMMq =4208 ,
  XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4209 ,
  XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4210 ,
  XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4211 ,
  XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4212 ,
  XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd =4213 ,
  XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd =4214 ,
  XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4215 ,
  XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4216 ,
  XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512 =4217 ,
  XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512 =4218 ,
  XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512 =4219 ,
  XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512 =4220 ,
  XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512 =4221 ,
  XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512 =4222 ,
  XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb =4223 ,
  XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb =4224 ,
  XED_IFORM_VDPPHPS_XMMf32_MASKmskw_XMM2f16_MEM2f16_AVX512 =4225 ,
  XED_IFORM_VDPPHPS_XMMf32_MASKmskw_XMM2f16_XMM2f16_AVX512 =4226 ,
  XED_IFORM_VDPPHPS_YMMf32_MASKmskw_YMM2f16_MEM2f16_AVX512 =4227 ,
  XED_IFORM_VDPPHPS_YMMf32_MASKmskw_YMM2f16_YMM2f16_AVX512 =4228 ,
  XED_IFORM_VDPPHPS_ZMMf32_MASKmskw_ZMM2f16_MEM2f16_AVX512 =4229 ,
  XED_IFORM_VDPPHPS_ZMMf32_MASKmskw_ZMM2f16_ZMM2f16_AVX512 =4230 ,
  XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb =4231 ,
  XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb =4232 ,
  XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb =4233 ,
  XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb =4234 ,
  XED_IFORM_VERR_GPR16 =4235 ,
  XED_IFORM_VERR_MEMw =4236 ,
  XED_IFORM_VERW_GPR16 =4237 ,
  XED_IFORM_VERW_MEMw =4238 ,
  XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER =4239 ,
  XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER =4240 ,
  XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER =4241 ,
  XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER =4242 ,
  XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512 =4243 ,
  XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512 =4244 ,
  XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512 =4245 ,
  XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512 =4246 ,
  XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512 =4247 ,
  XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512 =4248 ,
  XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512 =4249 ,
  XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512 =4250 ,
  XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512 =4251 ,
  XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512 =4252 ,
  XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512 =4253 ,
  XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512 =4254 ,
  XED_IFORM_VEXTRACTF128_MEMdq_YMMdq_IMMb =4255 ,
  XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb =4256 ,
  XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512 =4257 ,
  XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 =4258 ,
  XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512 =4259 ,
  XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512 =4260 ,
  XED_IFORM_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 =4261 ,
  XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512 =4262 ,
  XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512 =4263 ,
  XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 =4264 ,
  XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512 =4265 ,
  XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512 =4266 ,
  XED_IFORM_VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 =4267 ,
  XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512 =4268 ,
  XED_IFORM_VEXTRACTI128_MEMdq_YMMqq_IMMb =4269 ,
  XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb =4270 ,
  XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512 =4271 ,
  XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 =4272 ,
  XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512 =4273 ,
  XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512 =4274 ,
  XED_IFORM_VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 =4275 ,
  XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512 =4276 ,
  XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512 =4277 ,
  XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 =4278 ,
  XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512 =4279 ,
  XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512 =4280 ,
  XED_IFORM_VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 =4281 ,
  XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512 =4282 ,
  XED_IFORM_VEXTRACTPS_GPR32_XMMdq_IMMb =4283 ,
  XED_IFORM_VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512 =4284 ,
  XED_IFORM_VEXTRACTPS_MEMd_XMMdq_IMMb =4285 ,
  XED_IFORM_VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512 =4286 ,
  XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 =4287 ,
  XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 =4288 ,
  XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 =4289 ,
  XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 =4290 ,
  XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 =4291 ,
  XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 =4292 ,
  XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 =4293 ,
  XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 =4294 ,
  XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 =4295 ,
  XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 =4296 ,
  XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 =4297 ,
  XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 =4298 ,
  XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 =4299 ,
  XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 =4300 ,
  XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 =4301 ,
  XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 =4302 ,
  XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =4303 ,
  XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =4304 ,
  XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 =4305 ,
  XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 =4306 ,
  XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 =4307 ,
  XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 =4308 ,
  XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =4309 ,
  XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =4310 ,
  XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 =4311 ,
  XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 =4312 ,
  XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 =4313 ,
  XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 =4314 ,
  XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =4315 ,
  XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =4316 ,
  XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =4317 ,
  XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =4318 ,
  XED_IFORM_VFMADD132BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =4319 ,
  XED_IFORM_VFMADD132BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =4320 ,
  XED_IFORM_VFMADD132BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =4321 ,
  XED_IFORM_VFMADD132BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =4322 ,
  XED_IFORM_VFMADD132BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =4323 ,
  XED_IFORM_VFMADD132BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =4324 ,
  XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq =4325 ,
  XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq =4326 ,
  XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4327 ,
  XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4328 ,
  XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4329 ,
  XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4330 ,
  XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq =4331 ,
  XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq =4332 ,
  XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4333 ,
  XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4334 ,
  XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4335 ,
  XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4336 ,
  XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4337 ,
  XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4338 ,
  XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4339 ,
  XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4340 ,
  XED_IFORM_VFMADD132PS_XMMdq_XMMdq_MEMdq =4341 ,
  XED_IFORM_VFMADD132PS_XMMdq_XMMdq_XMMdq =4342 ,
  XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4343 ,
  XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4344 ,
  XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4345 ,
  XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4346 ,
  XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq =4347 ,
  XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq =4348 ,
  XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4349 ,
  XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4350 ,
  XED_IFORM_VFMADD132SD_XMMdq_XMMq_MEMq =4351 ,
  XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq =4352 ,
  XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4353 ,
  XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4354 ,
  XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4355 ,
  XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4356 ,
  XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd =4357 ,
  XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd =4358 ,
  XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4359 ,
  XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4360 ,
  XED_IFORM_VFMADD213BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =4361 ,
  XED_IFORM_VFMADD213BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =4362 ,
  XED_IFORM_VFMADD213BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =4363 ,
  XED_IFORM_VFMADD213BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =4364 ,
  XED_IFORM_VFMADD213BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =4365 ,
  XED_IFORM_VFMADD213BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =4366 ,
  XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq =4367 ,
  XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq =4368 ,
  XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4369 ,
  XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4370 ,
  XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4371 ,
  XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4372 ,
  XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq =4373 ,
  XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq =4374 ,
  XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4375 ,
  XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4376 ,
  XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4377 ,
  XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4378 ,
  XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4379 ,
  XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4380 ,
  XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4381 ,
  XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4382 ,
  XED_IFORM_VFMADD213PS_XMMdq_XMMdq_MEMdq =4383 ,
  XED_IFORM_VFMADD213PS_XMMdq_XMMdq_XMMdq =4384 ,
  XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4385 ,
  XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4386 ,
  XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4387 ,
  XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4388 ,
  XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq =4389 ,
  XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq =4390 ,
  XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4391 ,
  XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4392 ,
  XED_IFORM_VFMADD213SD_XMMdq_XMMq_MEMq =4393 ,
  XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq =4394 ,
  XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4395 ,
  XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4396 ,
  XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4397 ,
  XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4398 ,
  XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd =4399 ,
  XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd =4400 ,
  XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4401 ,
  XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4402 ,
  XED_IFORM_VFMADD231BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =4403 ,
  XED_IFORM_VFMADD231BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =4404 ,
  XED_IFORM_VFMADD231BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =4405 ,
  XED_IFORM_VFMADD231BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =4406 ,
  XED_IFORM_VFMADD231BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =4407 ,
  XED_IFORM_VFMADD231BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =4408 ,
  XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq =4409 ,
  XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq =4410 ,
  XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4411 ,
  XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4412 ,
  XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4413 ,
  XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4414 ,
  XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq =4415 ,
  XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq =4416 ,
  XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4417 ,
  XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4418 ,
  XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4419 ,
  XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4420 ,
  XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4421 ,
  XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4422 ,
  XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4423 ,
  XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4424 ,
  XED_IFORM_VFMADD231PS_XMMdq_XMMdq_MEMdq =4425 ,
  XED_IFORM_VFMADD231PS_XMMdq_XMMdq_XMMdq =4426 ,
  XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4427 ,
  XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4428 ,
  XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4429 ,
  XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4430 ,
  XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq =4431 ,
  XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq =4432 ,
  XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4433 ,
  XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4434 ,
  XED_IFORM_VFMADD231SD_XMMdq_XMMq_MEMq =4435 ,
  XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq =4436 ,
  XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4437 ,
  XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4438 ,
  XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4439 ,
  XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4440 ,
  XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd =4441 ,
  XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd =4442 ,
  XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4443 ,
  XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4444 ,
  XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 =4445 ,
  XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 =4446 ,
  XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 =4447 ,
  XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 =4448 ,
  XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 =4449 ,
  XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 =4450 ,
  XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 =4451 ,
  XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 =4452 ,
  XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq =4453 ,
  XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq =4454 ,
  XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq =4455 ,
  XED_IFORM_VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq =4456 ,
  XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq =4457 ,
  XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq =4458 ,
  XED_IFORM_VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq =4459 ,
  XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq =4460 ,
  XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq =4461 ,
  XED_IFORM_VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq =4462 ,
  XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq =4463 ,
  XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq =4464 ,
  XED_IFORM_VFMADDSD_XMMdq_XMMq_MEMq_XMMq =4465 ,
  XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_MEMq =4466 ,
  XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_XMMq =4467 ,
  XED_IFORM_VFMADDSS_XMMdq_XMMd_MEMd_XMMd =4468 ,
  XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_MEMd =4469 ,
  XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_XMMd =4470 ,
  XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_MEMdq =4471 ,
  XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_XMMdq =4472 ,
  XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4473 ,
  XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4474 ,
  XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4475 ,
  XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4476 ,
  XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq =4477 ,
  XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq =4478 ,
  XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4479 ,
  XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4480 ,
  XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4481 ,
  XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4482 ,
  XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4483 ,
  XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4484 ,
  XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4485 ,
  XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4486 ,
  XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_MEMdq =4487 ,
  XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_XMMdq =4488 ,
  XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4489 ,
  XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4490 ,
  XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4491 ,
  XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4492 ,
  XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq =4493 ,
  XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq =4494 ,
  XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4495 ,
  XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4496 ,
  XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_MEMdq =4497 ,
  XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_XMMdq =4498 ,
  XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4499 ,
  XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4500 ,
  XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4501 ,
  XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4502 ,
  XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq =4503 ,
  XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq =4504 ,
  XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4505 ,
  XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4506 ,
  XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4507 ,
  XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4508 ,
  XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4509 ,
  XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4510 ,
  XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4511 ,
  XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4512 ,
  XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_MEMdq =4513 ,
  XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_XMMdq =4514 ,
  XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4515 ,
  XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4516 ,
  XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4517 ,
  XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4518 ,
  XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq =4519 ,
  XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq =4520 ,
  XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4521 ,
  XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4522 ,
  XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_MEMdq =4523 ,
  XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_XMMdq =4524 ,
  XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4525 ,
  XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4526 ,
  XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4527 ,
  XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4528 ,
  XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq =4529 ,
  XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq =4530 ,
  XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4531 ,
  XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4532 ,
  XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4533 ,
  XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4534 ,
  XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4535 ,
  XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4536 ,
  XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4537 ,
  XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4538 ,
  XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_MEMdq =4539 ,
  XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_XMMdq =4540 ,
  XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4541 ,
  XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4542 ,
  XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4543 ,
  XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4544 ,
  XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq =4545 ,
  XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq =4546 ,
  XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4547 ,
  XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4548 ,
  XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq =4549 ,
  XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq =4550 ,
  XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq =4551 ,
  XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq =4552 ,
  XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq =4553 ,
  XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq =4554 ,
  XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq =4555 ,
  XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq =4556 ,
  XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq =4557 ,
  XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq =4558 ,
  XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq =4559 ,
  XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq =4560 ,
  XED_IFORM_VFMSUB132BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =4561 ,
  XED_IFORM_VFMSUB132BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =4562 ,
  XED_IFORM_VFMSUB132BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =4563 ,
  XED_IFORM_VFMSUB132BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =4564 ,
  XED_IFORM_VFMSUB132BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =4565 ,
  XED_IFORM_VFMSUB132BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =4566 ,
  XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq =4567 ,
  XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq =4568 ,
  XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4569 ,
  XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4570 ,
  XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4571 ,
  XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4572 ,
  XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq =4573 ,
  XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq =4574 ,
  XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4575 ,
  XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4576 ,
  XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4577 ,
  XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4578 ,
  XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4579 ,
  XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4580 ,
  XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4581 ,
  XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4582 ,
  XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_MEMdq =4583 ,
  XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_XMMdq =4584 ,
  XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4585 ,
  XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4586 ,
  XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4587 ,
  XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4588 ,
  XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq =4589 ,
  XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq =4590 ,
  XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4591 ,
  XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4592 ,
  XED_IFORM_VFMSUB132SD_XMMdq_XMMq_MEMq =4593 ,
  XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq =4594 ,
  XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4595 ,
  XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4596 ,
  XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4597 ,
  XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4598 ,
  XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd =4599 ,
  XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd =4600 ,
  XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4601 ,
  XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4602 ,
  XED_IFORM_VFMSUB213BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =4603 ,
  XED_IFORM_VFMSUB213BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =4604 ,
  XED_IFORM_VFMSUB213BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =4605 ,
  XED_IFORM_VFMSUB213BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =4606 ,
  XED_IFORM_VFMSUB213BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =4607 ,
  XED_IFORM_VFMSUB213BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =4608 ,
  XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq =4609 ,
  XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq =4610 ,
  XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4611 ,
  XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4612 ,
  XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4613 ,
  XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4614 ,
  XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq =4615 ,
  XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq =4616 ,
  XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4617 ,
  XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4618 ,
  XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4619 ,
  XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4620 ,
  XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4621 ,
  XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4622 ,
  XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4623 ,
  XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4624 ,
  XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_MEMdq =4625 ,
  XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_XMMdq =4626 ,
  XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4627 ,
  XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4628 ,
  XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4629 ,
  XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4630 ,
  XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq =4631 ,
  XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq =4632 ,
  XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4633 ,
  XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4634 ,
  XED_IFORM_VFMSUB213SD_XMMdq_XMMq_MEMq =4635 ,
  XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq =4636 ,
  XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4637 ,
  XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4638 ,
  XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4639 ,
  XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4640 ,
  XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd =4641 ,
  XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd =4642 ,
  XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4643 ,
  XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4644 ,
  XED_IFORM_VFMSUB231BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =4645 ,
  XED_IFORM_VFMSUB231BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =4646 ,
  XED_IFORM_VFMSUB231BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =4647 ,
  XED_IFORM_VFMSUB231BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =4648 ,
  XED_IFORM_VFMSUB231BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =4649 ,
  XED_IFORM_VFMSUB231BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =4650 ,
  XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq =4651 ,
  XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq =4652 ,
  XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4653 ,
  XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4654 ,
  XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4655 ,
  XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4656 ,
  XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq =4657 ,
  XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq =4658 ,
  XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4659 ,
  XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4660 ,
  XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4661 ,
  XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4662 ,
  XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4663 ,
  XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4664 ,
  XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4665 ,
  XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4666 ,
  XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_MEMdq =4667 ,
  XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_XMMdq =4668 ,
  XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4669 ,
  XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4670 ,
  XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4671 ,
  XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4672 ,
  XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq =4673 ,
  XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq =4674 ,
  XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4675 ,
  XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4676 ,
  XED_IFORM_VFMSUB231SD_XMMdq_XMMq_MEMq =4677 ,
  XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq =4678 ,
  XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4679 ,
  XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4680 ,
  XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4681 ,
  XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4682 ,
  XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd =4683 ,
  XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd =4684 ,
  XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4685 ,
  XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4686 ,
  XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq =4687 ,
  XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq =4688 ,
  XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4689 ,
  XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4690 ,
  XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4691 ,
  XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4692 ,
  XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq =4693 ,
  XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq =4694 ,
  XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4695 ,
  XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4696 ,
  XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4697 ,
  XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4698 ,
  XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4699 ,
  XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4700 ,
  XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4701 ,
  XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4702 ,
  XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_MEMdq =4703 ,
  XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_XMMdq =4704 ,
  XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4705 ,
  XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4706 ,
  XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4707 ,
  XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4708 ,
  XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq =4709 ,
  XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq =4710 ,
  XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4711 ,
  XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4712 ,
  XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_MEMdq =4713 ,
  XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_XMMdq =4714 ,
  XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4715 ,
  XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4716 ,
  XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4717 ,
  XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4718 ,
  XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq =4719 ,
  XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq =4720 ,
  XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4721 ,
  XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4722 ,
  XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4723 ,
  XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4724 ,
  XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4725 ,
  XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4726 ,
  XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4727 ,
  XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4728 ,
  XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_MEMdq =4729 ,
  XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_XMMdq =4730 ,
  XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4731 ,
  XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4732 ,
  XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4733 ,
  XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4734 ,
  XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq =4735 ,
  XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq =4736 ,
  XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4737 ,
  XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4738 ,
  XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_MEMdq =4739 ,
  XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_XMMdq =4740 ,
  XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4741 ,
  XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4742 ,
  XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4743 ,
  XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4744 ,
  XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq =4745 ,
  XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq =4746 ,
  XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4747 ,
  XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4748 ,
  XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4749 ,
  XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4750 ,
  XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4751 ,
  XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4752 ,
  XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4753 ,
  XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4754 ,
  XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_MEMdq =4755 ,
  XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_XMMdq =4756 ,
  XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4757 ,
  XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4758 ,
  XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4759 ,
  XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4760 ,
  XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq =4761 ,
  XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq =4762 ,
  XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4763 ,
  XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4764 ,
  XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq =4765 ,
  XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq =4766 ,
  XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq =4767 ,
  XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq =4768 ,
  XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq =4769 ,
  XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq =4770 ,
  XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq =4771 ,
  XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq =4772 ,
  XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq =4773 ,
  XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq =4774 ,
  XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq =4775 ,
  XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq =4776 ,
  XED_IFORM_VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq =4777 ,
  XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq =4778 ,
  XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq =4779 ,
  XED_IFORM_VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq =4780 ,
  XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq =4781 ,
  XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq =4782 ,
  XED_IFORM_VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq =4783 ,
  XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq =4784 ,
  XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq =4785 ,
  XED_IFORM_VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq =4786 ,
  XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq =4787 ,
  XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq =4788 ,
  XED_IFORM_VFMSUBSD_XMMdq_XMMq_MEMq_XMMq =4789 ,
  XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_MEMq =4790 ,
  XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_XMMq =4791 ,
  XED_IFORM_VFMSUBSS_XMMdq_XMMd_MEMd_XMMd =4792 ,
  XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_MEMd =4793 ,
  XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_XMMd =4794 ,
  XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 =4795 ,
  XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 =4796 ,
  XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 =4797 ,
  XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 =4798 ,
  XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 =4799 ,
  XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 =4800 ,
  XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 =4801 ,
  XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 =4802 ,
  XED_IFORM_VFNMADD132BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =4803 ,
  XED_IFORM_VFNMADD132BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =4804 ,
  XED_IFORM_VFNMADD132BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =4805 ,
  XED_IFORM_VFNMADD132BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =4806 ,
  XED_IFORM_VFNMADD132BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =4807 ,
  XED_IFORM_VFNMADD132BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =4808 ,
  XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq =4809 ,
  XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq =4810 ,
  XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4811 ,
  XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4812 ,
  XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4813 ,
  XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4814 ,
  XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq =4815 ,
  XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq =4816 ,
  XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4817 ,
  XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4818 ,
  XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4819 ,
  XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4820 ,
  XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4821 ,
  XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4822 ,
  XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4823 ,
  XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4824 ,
  XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_MEMdq =4825 ,
  XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_XMMdq =4826 ,
  XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4827 ,
  XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4828 ,
  XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4829 ,
  XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4830 ,
  XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq =4831 ,
  XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq =4832 ,
  XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4833 ,
  XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4834 ,
  XED_IFORM_VFNMADD132SD_XMMdq_XMMq_MEMq =4835 ,
  XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq =4836 ,
  XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4837 ,
  XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4838 ,
  XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4839 ,
  XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4840 ,
  XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd =4841 ,
  XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd =4842 ,
  XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4843 ,
  XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4844 ,
  XED_IFORM_VFNMADD213BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =4845 ,
  XED_IFORM_VFNMADD213BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =4846 ,
  XED_IFORM_VFNMADD213BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =4847 ,
  XED_IFORM_VFNMADD213BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =4848 ,
  XED_IFORM_VFNMADD213BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =4849 ,
  XED_IFORM_VFNMADD213BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =4850 ,
  XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq =4851 ,
  XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq =4852 ,
  XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4853 ,
  XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4854 ,
  XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4855 ,
  XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4856 ,
  XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq =4857 ,
  XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq =4858 ,
  XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4859 ,
  XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4860 ,
  XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4861 ,
  XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4862 ,
  XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4863 ,
  XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4864 ,
  XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4865 ,
  XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4866 ,
  XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_MEMdq =4867 ,
  XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_XMMdq =4868 ,
  XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4869 ,
  XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4870 ,
  XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4871 ,
  XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4872 ,
  XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq =4873 ,
  XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq =4874 ,
  XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4875 ,
  XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4876 ,
  XED_IFORM_VFNMADD213SD_XMMdq_XMMq_MEMq =4877 ,
  XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq =4878 ,
  XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4879 ,
  XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4880 ,
  XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4881 ,
  XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4882 ,
  XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd =4883 ,
  XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd =4884 ,
  XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4885 ,
  XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4886 ,
  XED_IFORM_VFNMADD231BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =4887 ,
  XED_IFORM_VFNMADD231BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =4888 ,
  XED_IFORM_VFNMADD231BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =4889 ,
  XED_IFORM_VFNMADD231BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =4890 ,
  XED_IFORM_VFNMADD231BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =4891 ,
  XED_IFORM_VFNMADD231BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =4892 ,
  XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq =4893 ,
  XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq =4894 ,
  XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4895 ,
  XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4896 ,
  XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4897 ,
  XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4898 ,
  XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq =4899 ,
  XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq =4900 ,
  XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4901 ,
  XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4902 ,
  XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4903 ,
  XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4904 ,
  XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4905 ,
  XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4906 ,
  XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4907 ,
  XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4908 ,
  XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_MEMdq =4909 ,
  XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_XMMdq =4910 ,
  XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4911 ,
  XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4912 ,
  XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4913 ,
  XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4914 ,
  XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq =4915 ,
  XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq =4916 ,
  XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4917 ,
  XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4918 ,
  XED_IFORM_VFNMADD231SD_XMMdq_XMMq_MEMq =4919 ,
  XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq =4920 ,
  XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4921 ,
  XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4922 ,
  XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4923 ,
  XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4924 ,
  XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd =4925 ,
  XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd =4926 ,
  XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4927 ,
  XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4928 ,
  XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq =4929 ,
  XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq =4930 ,
  XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq =4931 ,
  XED_IFORM_VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq =4932 ,
  XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq =4933 ,
  XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq =4934 ,
  XED_IFORM_VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq =4935 ,
  XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq =4936 ,
  XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq =4937 ,
  XED_IFORM_VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq =4938 ,
  XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq =4939 ,
  XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq =4940 ,
  XED_IFORM_VFNMADDSD_XMMdq_XMMq_MEMq_XMMq =4941 ,
  XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_MEMq =4942 ,
  XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_XMMq =4943 ,
  XED_IFORM_VFNMADDSS_XMMdq_XMMd_MEMd_XMMd =4944 ,
  XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_MEMd =4945 ,
  XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd =4946 ,
  XED_IFORM_VFNMSUB132BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =4947 ,
  XED_IFORM_VFNMSUB132BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =4948 ,
  XED_IFORM_VFNMSUB132BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =4949 ,
  XED_IFORM_VFNMSUB132BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =4950 ,
  XED_IFORM_VFNMSUB132BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =4951 ,
  XED_IFORM_VFNMSUB132BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =4952 ,
  XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq =4953 ,
  XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq =4954 ,
  XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4955 ,
  XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4956 ,
  XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4957 ,
  XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =4958 ,
  XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq =4959 ,
  XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq =4960 ,
  XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =4961 ,
  XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =4962 ,
  XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4963 ,
  XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4964 ,
  XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =4965 ,
  XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =4966 ,
  XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =4967 ,
  XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =4968 ,
  XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_MEMdq =4969 ,
  XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_XMMdq =4970 ,
  XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4971 ,
  XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4972 ,
  XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =4973 ,
  XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =4974 ,
  XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq =4975 ,
  XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq =4976 ,
  XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =4977 ,
  XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =4978 ,
  XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_MEMq =4979 ,
  XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq =4980 ,
  XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4981 ,
  XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4982 ,
  XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =4983 ,
  XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =4984 ,
  XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd =4985 ,
  XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd =4986 ,
  XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =4987 ,
  XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =4988 ,
  XED_IFORM_VFNMSUB213BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =4989 ,
  XED_IFORM_VFNMSUB213BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =4990 ,
  XED_IFORM_VFNMSUB213BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =4991 ,
  XED_IFORM_VFNMSUB213BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =4992 ,
  XED_IFORM_VFNMSUB213BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =4993 ,
  XED_IFORM_VFNMSUB213BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =4994 ,
  XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq =4995 ,
  XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq =4996 ,
  XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =4997 ,
  XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =4998 ,
  XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =4999 ,
  XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =5000 ,
  XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq =5001 ,
  XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq =5002 ,
  XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =5003 ,
  XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =5004 ,
  XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5005 ,
  XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5006 ,
  XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =5007 ,
  XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =5008 ,
  XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =5009 ,
  XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =5010 ,
  XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_MEMdq =5011 ,
  XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_XMMdq =5012 ,
  XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5013 ,
  XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5014 ,
  XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =5015 ,
  XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =5016 ,
  XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq =5017 ,
  XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq =5018 ,
  XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =5019 ,
  XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =5020 ,
  XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_MEMq =5021 ,
  XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq =5022 ,
  XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5023 ,
  XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5024 ,
  XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5025 ,
  XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5026 ,
  XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd =5027 ,
  XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd =5028 ,
  XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5029 ,
  XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5030 ,
  XED_IFORM_VFNMSUB231BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =5031 ,
  XED_IFORM_VFNMSUB231BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =5032 ,
  XED_IFORM_VFNMSUB231BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =5033 ,
  XED_IFORM_VFNMSUB231BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =5034 ,
  XED_IFORM_VFNMSUB231BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =5035 ,
  XED_IFORM_VFNMSUB231BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =5036 ,
  XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq =5037 ,
  XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq =5038 ,
  XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5039 ,
  XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5040 ,
  XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =5041 ,
  XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =5042 ,
  XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq =5043 ,
  XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq =5044 ,
  XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =5045 ,
  XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =5046 ,
  XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5047 ,
  XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5048 ,
  XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =5049 ,
  XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =5050 ,
  XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =5051 ,
  XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =5052 ,
  XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_MEMdq =5053 ,
  XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_XMMdq =5054 ,
  XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5055 ,
  XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5056 ,
  XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =5057 ,
  XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =5058 ,
  XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq =5059 ,
  XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq =5060 ,
  XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =5061 ,
  XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =5062 ,
  XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_MEMq =5063 ,
  XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq =5064 ,
  XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5065 ,
  XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5066 ,
  XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5067 ,
  XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5068 ,
  XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd =5069 ,
  XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd =5070 ,
  XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5071 ,
  XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5072 ,
  XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq =5073 ,
  XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq =5074 ,
  XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq =5075 ,
  XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq =5076 ,
  XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq =5077 ,
  XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq =5078 ,
  XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq =5079 ,
  XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq =5080 ,
  XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq =5081 ,
  XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq =5082 ,
  XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq =5083 ,
  XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq =5084 ,
  XED_IFORM_VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq =5085 ,
  XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq =5086 ,
  XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq =5087 ,
  XED_IFORM_VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd =5088 ,
  XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd =5089 ,
  XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd =5090 ,
  XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL128 =5091 ,
  XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL256 =5092 ,
  XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL512 =5093 ,
  XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_XMMbf16_IMM8_AVX512 =5094 ,
  XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_YMMbf16_IMM8_AVX512 =5095 ,
  XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_ZMMbf16_IMM8_AVX512 =5096 ,
  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128 =5097 ,
  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256 =5098 ,
  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512 =5099 ,
  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 =5100 ,
  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512 =5101 ,
  XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512 =5102 ,
  XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128 =5103 ,
  XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256 =5104 ,
  XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512 =5105 ,
  XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512 =5106 ,
  XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512 =5107 ,
  XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512 =5108 ,
  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128 =5109 ,
  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256 =5110 ,
  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512 =5111 ,
  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 =5112 ,
  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512 =5113 ,
  XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512 =5114 ,
  XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512 =5115 ,
  XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 =5116 ,
  XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512 =5117 ,
  XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512 =5118 ,
  XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512 =5119 ,
  XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 =5120 ,
  XED_IFORM_VFRCZPD_XMMdq_MEMdq =5121 ,
  XED_IFORM_VFRCZPD_XMMdq_XMMdq =5122 ,
  XED_IFORM_VFRCZPD_YMMqq_MEMqq =5123 ,
  XED_IFORM_VFRCZPD_YMMqq_YMMqq =5124 ,
  XED_IFORM_VFRCZPS_XMMdq_MEMdq =5125 ,
  XED_IFORM_VFRCZPS_XMMdq_XMMdq =5126 ,
  XED_IFORM_VFRCZPS_YMMqq_MEMqq =5127 ,
  XED_IFORM_VFRCZPS_YMMqq_YMMqq =5128 ,
  XED_IFORM_VFRCZSD_XMMdq_MEMq =5129 ,
  XED_IFORM_VFRCZSD_XMMdq_XMMq =5130 ,
  XED_IFORM_VFRCZSS_XMMdq_MEMd =5131 ,
  XED_IFORM_VFRCZSS_XMMdq_XMMd =5132 ,
  XED_IFORM_VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 =5133 ,
  XED_IFORM_VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128 =5134 ,
  XED_IFORM_VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 =5135 ,
  XED_IFORM_VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256 =5136 ,
  XED_IFORM_VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 =5137 ,
  XED_IFORM_VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 =5138 ,
  XED_IFORM_VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128 =5139 ,
  XED_IFORM_VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256 =5140 ,
  XED_IFORM_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256 =5141 ,
  XED_IFORM_VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512 =5142 ,
  XED_IFORM_VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 =5143 ,
  XED_IFORM_VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 =5144 ,
  XED_IFORM_VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 =5145 ,
  XED_IFORM_VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 =5146 ,
  XED_IFORM_VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 =5147 ,
  XED_IFORM_VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 =5148 ,
  XED_IFORM_VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 =5149 ,
  XED_IFORM_VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 =5150 ,
  XED_IFORM_VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 =5151 ,
  XED_IFORM_VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128 =5152 ,
  XED_IFORM_VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 =5153 ,
  XED_IFORM_VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256 =5154 ,
  XED_IFORM_VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 =5155 ,
  XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 =5156 ,
  XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256 =5157 ,
  XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128 =5158 ,
  XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256 =5159 ,
  XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512 =5160 ,
  XED_IFORM_VGETEXPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512 =5161 ,
  XED_IFORM_VGETEXPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512 =5162 ,
  XED_IFORM_VGETEXPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512 =5163 ,
  XED_IFORM_VGETEXPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512 =5164 ,
  XED_IFORM_VGETEXPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512 =5165 ,
  XED_IFORM_VGETEXPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512 =5166 ,
  XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512 =5167 ,
  XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512 =5168 ,
  XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512 =5169 ,
  XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512 =5170 ,
  XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512 =5171 ,
  XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512 =5172 ,
  XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512 =5173 ,
  XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512 =5174 ,
  XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512 =5175 ,
  XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512 =5176 ,
  XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512 =5177 ,
  XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512 =5178 ,
  XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512 =5179 ,
  XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512 =5180 ,
  XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512 =5181 ,
  XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512 =5182 ,
  XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512 =5183 ,
  XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512 =5184 ,
  XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5185 ,
  XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5186 ,
  XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5187 ,
  XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5188 ,
  XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5189 ,
  XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5190 ,
  XED_IFORM_VGETMANTBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512 =5191 ,
  XED_IFORM_VGETMANTBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512 =5192 ,
  XED_IFORM_VGETMANTBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512 =5193 ,
  XED_IFORM_VGETMANTBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512 =5194 ,
  XED_IFORM_VGETMANTBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512 =5195 ,
  XED_IFORM_VGETMANTBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512 =5196 ,
  XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 =5197 ,
  XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 =5198 ,
  XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 =5199 ,
  XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 =5200 ,
  XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 =5201 ,
  XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 =5202 ,
  XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 =5203 ,
  XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 =5204 ,
  XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 =5205 ,
  XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 =5206 ,
  XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 =5207 ,
  XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 =5208 ,
  XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 =5209 ,
  XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 =5210 ,
  XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 =5211 ,
  XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 =5212 ,
  XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 =5213 ,
  XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 =5214 ,
  XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =5215 ,
  XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =5216 ,
  XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 =5217 ,
  XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 =5218 ,
  XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =5219 ,
  XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =5220 ,
  XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 =5221 ,
  XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 =5222 ,
  XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8 =5223 ,
  XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8 =5224 ,
  XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 =5225 ,
  XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 =5226 ,
  XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8 =5227 ,
  XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8 =5228 ,
  XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 =5229 ,
  XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 =5230 ,
  XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 =5231 ,
  XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 =5232 ,
  XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8 =5233 ,
  XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8 =5234 ,
  XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 =5235 ,
  XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 =5236 ,
  XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8 =5237 ,
  XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8 =5238 ,
  XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 =5239 ,
  XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 =5240 ,
  XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =5241 ,
  XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =5242 ,
  XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_MEMu8 =5243 ,
  XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_XMMu8 =5244 ,
  XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =5245 ,
  XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =5246 ,
  XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_MEMu8 =5247 ,
  XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_YMMu8 =5248 ,
  XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =5249 ,
  XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =5250 ,
  XED_IFORM_VHADDPD_XMMdq_XMMdq_MEMdq =5251 ,
  XED_IFORM_VHADDPD_XMMdq_XMMdq_XMMdq =5252 ,
  XED_IFORM_VHADDPD_YMMqq_YMMqq_MEMqq =5253 ,
  XED_IFORM_VHADDPD_YMMqq_YMMqq_YMMqq =5254 ,
  XED_IFORM_VHADDPS_XMMdq_XMMdq_MEMdq =5255 ,
  XED_IFORM_VHADDPS_XMMdq_XMMdq_XMMdq =5256 ,
  XED_IFORM_VHADDPS_YMMqq_YMMqq_MEMqq =5257 ,
  XED_IFORM_VHADDPS_YMMqq_YMMqq_YMMqq =5258 ,
  XED_IFORM_VHSUBPD_XMMdq_XMMdq_MEMdq =5259 ,
  XED_IFORM_VHSUBPD_XMMdq_XMMdq_XMMdq =5260 ,
  XED_IFORM_VHSUBPD_YMMqq_YMMqq_MEMqq =5261 ,
  XED_IFORM_VHSUBPD_YMMqq_YMMqq_YMMqq =5262 ,
  XED_IFORM_VHSUBPS_XMMdq_XMMdq_MEMdq =5263 ,
  XED_IFORM_VHSUBPS_XMMdq_XMMdq_XMMdq =5264 ,
  XED_IFORM_VHSUBPS_YMMqq_YMMqq_MEMqq =5265 ,
  XED_IFORM_VHSUBPS_YMMqq_YMMqq_YMMqq =5266 ,
  XED_IFORM_VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb =5267 ,
  XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb =5268 ,
  XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 =5269 ,
  XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512 =5270 ,
  XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 =5271 ,
  XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512 =5272 ,
  XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 =5273 ,
  XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512 =5274 ,
  XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 =5275 ,
  XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512 =5276 ,
  XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 =5277 ,
  XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512 =5278 ,
  XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 =5279 ,
  XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512 =5280 ,
  XED_IFORM_VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb =5281 ,
  XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb =5282 ,
  XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 =5283 ,
  XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512 =5284 ,
  XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 =5285 ,
  XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512 =5286 ,
  XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 =5287 ,
  XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512 =5288 ,
  XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 =5289 ,
  XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512 =5290 ,
  XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 =5291 ,
  XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512 =5292 ,
  XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 =5293 ,
  XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512 =5294 ,
  XED_IFORM_VINSERTPS_XMMdq_XMMdq_MEMd_IMMb =5295 ,
  XED_IFORM_VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb =5296 ,
  XED_IFORM_VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512 =5297 ,
  XED_IFORM_VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512 =5298 ,
  XED_IFORM_VLDDQU_XMMdq_MEMdq =5299 ,
  XED_IFORM_VLDDQU_YMMqq_MEMqq =5300 ,
  XED_IFORM_VLDMXCSR_MEMd =5301 ,
  XED_IFORM_VMASKMOVDQU_XMMxub_XMMxub =5302 ,
  XED_IFORM_VMASKMOVPD_MEMdq_XMMdq_XMMdq =5303 ,
  XED_IFORM_VMASKMOVPD_MEMqq_YMMqq_YMMqq =5304 ,
  XED_IFORM_VMASKMOVPD_XMMdq_XMMdq_MEMdq =5305 ,
  XED_IFORM_VMASKMOVPD_YMMqq_YMMqq_MEMqq =5306 ,
  XED_IFORM_VMASKMOVPS_MEMdq_XMMdq_XMMdq =5307 ,
  XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq =5308 ,
  XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq =5309 ,
  XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq =5310 ,
  XED_IFORM_VMAXBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =5311 ,
  XED_IFORM_VMAXBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =5312 ,
  XED_IFORM_VMAXBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =5313 ,
  XED_IFORM_VMAXBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =5314 ,
  XED_IFORM_VMAXBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =5315 ,
  XED_IFORM_VMAXBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =5316 ,
  XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq =5317 ,
  XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq =5318 ,
  XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5319 ,
  XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5320 ,
  XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =5321 ,
  XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =5322 ,
  XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq =5323 ,
  XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq =5324 ,
  XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =5325 ,
  XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =5326 ,
  XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5327 ,
  XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5328 ,
  XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =5329 ,
  XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =5330 ,
  XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =5331 ,
  XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =5332 ,
  XED_IFORM_VMAXPS_XMMdq_XMMdq_MEMdq =5333 ,
  XED_IFORM_VMAXPS_XMMdq_XMMdq_XMMdq =5334 ,
  XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5335 ,
  XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5336 ,
  XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =5337 ,
  XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =5338 ,
  XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq =5339 ,
  XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq =5340 ,
  XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =5341 ,
  XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =5342 ,
  XED_IFORM_VMAXSD_XMMdq_XMMdq_MEMq =5343 ,
  XED_IFORM_VMAXSD_XMMdq_XMMdq_XMMq =5344 ,
  XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5345 ,
  XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5346 ,
  XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5347 ,
  XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5348 ,
  XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd =5349 ,
  XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd =5350 ,
  XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5351 ,
  XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5352 ,
  XED_IFORM_VMCALL =5353 ,
  XED_IFORM_VMCLEAR_MEMq =5354 ,
  XED_IFORM_VMFUNC =5355 ,
  XED_IFORM_VMINBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =5356 ,
  XED_IFORM_VMINBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =5357 ,
  XED_IFORM_VMINBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =5358 ,
  XED_IFORM_VMINBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =5359 ,
  XED_IFORM_VMINBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =5360 ,
  XED_IFORM_VMINBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =5361 ,
  XED_IFORM_VMINMAXBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_IMM8_AVX512 =5362 ,
  XED_IFORM_VMINMAXBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_IMM8_AVX512 =5363 ,
  XED_IFORM_VMINMAXBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_IMM8_AVX512 =5364 ,
  XED_IFORM_VMINMAXBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_IMM8_AVX512 =5365 ,
  XED_IFORM_VMINMAXBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_IMM8_AVX512 =5366 ,
  XED_IFORM_VMINMAXBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_IMM8_AVX512 =5367 ,
  XED_IFORM_VMINMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =5368 ,
  XED_IFORM_VMINMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =5369 ,
  XED_IFORM_VMINMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 =5370 ,
  XED_IFORM_VMINMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 =5371 ,
  XED_IFORM_VMINMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 =5372 ,
  XED_IFORM_VMINMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 =5373 ,
  XED_IFORM_VMINMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 =5374 ,
  XED_IFORM_VMINMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 =5375 ,
  XED_IFORM_VMINMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_IMM8_AVX512 =5376 ,
  XED_IFORM_VMINMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_IMM8_AVX512 =5377 ,
  XED_IFORM_VMINMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512 =5378 ,
  XED_IFORM_VMINMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512 =5379 ,
  XED_IFORM_VMINMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =5380 ,
  XED_IFORM_VMINMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =5381 ,
  XED_IFORM_VMINMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 =5382 ,
  XED_IFORM_VMINMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 =5383 ,
  XED_IFORM_VMINMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 =5384 ,
  XED_IFORM_VMINMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 =5385 ,
  XED_IFORM_VMINMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =5386 ,
  XED_IFORM_VMINMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =5387 ,
  XED_IFORM_VMINMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 =5388 ,
  XED_IFORM_VMINMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 =5389 ,
  XED_IFORM_VMINMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =5390 ,
  XED_IFORM_VMINMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =5391 ,
  XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq =5392 ,
  XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq =5393 ,
  XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5394 ,
  XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5395 ,
  XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =5396 ,
  XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =5397 ,
  XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq =5398 ,
  XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq =5399 ,
  XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =5400 ,
  XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =5401 ,
  XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5402 ,
  XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5403 ,
  XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =5404 ,
  XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =5405 ,
  XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =5406 ,
  XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =5407 ,
  XED_IFORM_VMINPS_XMMdq_XMMdq_MEMdq =5408 ,
  XED_IFORM_VMINPS_XMMdq_XMMdq_XMMdq =5409 ,
  XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5410 ,
  XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5411 ,
  XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =5412 ,
  XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =5413 ,
  XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq =5414 ,
  XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq =5415 ,
  XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =5416 ,
  XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =5417 ,
  XED_IFORM_VMINSD_XMMdq_XMMdq_MEMq =5418 ,
  XED_IFORM_VMINSD_XMMdq_XMMdq_XMMq =5419 ,
  XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5420 ,
  XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5421 ,
  XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5422 ,
  XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5423 ,
  XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd =5424 ,
  XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd =5425 ,
  XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5426 ,
  XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5427 ,
  XED_IFORM_VMLAUNCH =5428 ,
  XED_IFORM_VMLOAD_ArAX =5429 ,
  XED_IFORM_VMMCALL =5430 ,
  XED_IFORM_VMOVAPD_MEMdq_XMMdq =5431 ,
  XED_IFORM_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512 =5432 ,
  XED_IFORM_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512 =5433 ,
  XED_IFORM_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512 =5434 ,
  XED_IFORM_VMOVAPD_MEMqq_YMMqq =5435 ,
  XED_IFORM_VMOVAPD_XMMdq_MEMdq =5436 ,
  XED_IFORM_VMOVAPD_XMMdq_XMMdq_28 =5437 ,
  XED_IFORM_VMOVAPD_XMMdq_XMMdq_29 =5438 ,
  XED_IFORM_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512 =5439 ,
  XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512 =5440 ,
  XED_IFORM_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512 =5441 ,
  XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512 =5442 ,
  XED_IFORM_VMOVAPD_YMMqq_MEMqq =5443 ,
  XED_IFORM_VMOVAPD_YMMqq_YMMqq_28 =5444 ,
  XED_IFORM_VMOVAPD_YMMqq_YMMqq_29 =5445 ,
  XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512 =5446 ,
  XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512 =5447 ,
  XED_IFORM_VMOVAPS_MEMdq_XMMdq =5448 ,
  XED_IFORM_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512 =5449 ,
  XED_IFORM_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512 =5450 ,
  XED_IFORM_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512 =5451 ,
  XED_IFORM_VMOVAPS_MEMqq_YMMqq =5452 ,
  XED_IFORM_VMOVAPS_XMMdq_MEMdq =5453 ,
  XED_IFORM_VMOVAPS_XMMdq_XMMdq_28 =5454 ,
  XED_IFORM_VMOVAPS_XMMdq_XMMdq_29 =5455 ,
  XED_IFORM_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512 =5456 ,
  XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512 =5457 ,
  XED_IFORM_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512 =5458 ,
  XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512 =5459 ,
  XED_IFORM_VMOVAPS_YMMqq_MEMqq =5460 ,
  XED_IFORM_VMOVAPS_YMMqq_YMMqq_28 =5461 ,
  XED_IFORM_VMOVAPS_YMMqq_YMMqq_29 =5462 ,
  XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512 =5463 ,
  XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512 =5464 ,
  XED_IFORM_VMOVD_GPR32d_XMMd =5465 ,
  XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512 =5466 ,
  XED_IFORM_VMOVD_MEMd_XMMd =5467 ,
  XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512 =5468 ,
  XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512_MOVZXC =5469 ,
  XED_IFORM_VMOVD_XMMdq_GPR32d =5470 ,
  XED_IFORM_VMOVD_XMMdq_MEMd =5471 ,
  XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512 =5472 ,
  XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512 =5473 ,
  XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512_MOVZXC =5474 ,
  XED_IFORM_VMOVD_XMMu32_XMMu32_AVX512_MOVZXC =5475 ,
  XED_IFORM_VMOVDDUP_XMMdq_MEMq =5476 ,
  XED_IFORM_VMOVDDUP_XMMdq_XMMq =5477 ,
  XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512 =5478 ,
  XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512 =5479 ,
  XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512 =5480 ,
  XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512 =5481 ,
  XED_IFORM_VMOVDDUP_YMMqq_MEMqq =5482 ,
  XED_IFORM_VMOVDDUP_YMMqq_YMMqq =5483 ,
  XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512 =5484 ,
  XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512 =5485 ,
  XED_IFORM_VMOVDQA_MEMdq_XMMdq =5486 ,
  XED_IFORM_VMOVDQA_MEMqq_YMMqq =5487 ,
  XED_IFORM_VMOVDQA_XMMdq_MEMdq =5488 ,
  XED_IFORM_VMOVDQA_XMMdq_XMMdq_6F =5489 ,
  XED_IFORM_VMOVDQA_XMMdq_XMMdq_7F =5490 ,
  XED_IFORM_VMOVDQA_YMMqq_MEMqq =5491 ,
  XED_IFORM_VMOVDQA_YMMqq_YMMqq_6F =5492 ,
  XED_IFORM_VMOVDQA_YMMqq_YMMqq_7F =5493 ,
  XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512 =5494 ,
  XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512 =5495 ,
  XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512 =5496 ,
  XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512 =5497 ,
  XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512 =5498 ,
  XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512 =5499 ,
  XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512 =5500 ,
  XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512 =5501 ,
  XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512 =5502 ,
  XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512 =5503 ,
  XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512 =5504 ,
  XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512 =5505 ,
  XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512 =5506 ,
  XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512 =5507 ,
  XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512 =5508 ,
  XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512 =5509 ,
  XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512 =5510 ,
  XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512 =5511 ,
  XED_IFORM_VMOVDQU_MEMdq_XMMdq =5512 ,
  XED_IFORM_VMOVDQU_MEMqq_YMMqq =5513 ,
  XED_IFORM_VMOVDQU_XMMdq_MEMdq =5514 ,
  XED_IFORM_VMOVDQU_XMMdq_XMMdq_6F =5515 ,
  XED_IFORM_VMOVDQU_XMMdq_XMMdq_7F =5516 ,
  XED_IFORM_VMOVDQU_YMMqq_MEMqq =5517 ,
  XED_IFORM_VMOVDQU_YMMqq_YMMqq_6F =5518 ,
  XED_IFORM_VMOVDQU_YMMqq_YMMqq_7F =5519 ,
  XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512 =5520 ,
  XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512 =5521 ,
  XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512 =5522 ,
  XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512 =5523 ,
  XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512 =5524 ,
  XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512 =5525 ,
  XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512 =5526 ,
  XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512 =5527 ,
  XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512 =5528 ,
  XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512 =5529 ,
  XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512 =5530 ,
  XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512 =5531 ,
  XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512 =5532 ,
  XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512 =5533 ,
  XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512 =5534 ,
  XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512 =5535 ,
  XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512 =5536 ,
  XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512 =5537 ,
  XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512 =5538 ,
  XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512 =5539 ,
  XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512 =5540 ,
  XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512 =5541 ,
  XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512 =5542 ,
  XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512 =5543 ,
  XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512 =5544 ,
  XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512 =5545 ,
  XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512 =5546 ,
  XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512 =5547 ,
  XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512 =5548 ,
  XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512 =5549 ,
  XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512 =5550 ,
  XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512 =5551 ,
  XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512 =5552 ,
  XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512 =5553 ,
  XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512 =5554 ,
  XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512 =5555 ,
  XED_IFORM_VMOVHLPS_XMMdq_XMMdq_XMMdq =5556 ,
  XED_IFORM_VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512 =5557 ,
  XED_IFORM_VMOVHPD_MEMf64_XMMf64_AVX512 =5558 ,
  XED_IFORM_VMOVHPD_MEMq_XMMdq =5559 ,
  XED_IFORM_VMOVHPD_XMMdq_XMMq_MEMq =5560 ,
  XED_IFORM_VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512 =5561 ,
  XED_IFORM_VMOVHPS_MEMf32_XMMf32_AVX512 =5562 ,
  XED_IFORM_VMOVHPS_MEMq_XMMdq =5563 ,
  XED_IFORM_VMOVHPS_XMMdq_XMMq_MEMq =5564 ,
  XED_IFORM_VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512 =5565 ,
  XED_IFORM_VMOVLHPS_XMMdq_XMMq_XMMq =5566 ,
  XED_IFORM_VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512 =5567 ,
  XED_IFORM_VMOVLPD_MEMf64_XMMf64_AVX512 =5568 ,
  XED_IFORM_VMOVLPD_MEMq_XMMq =5569 ,
  XED_IFORM_VMOVLPD_XMMdq_XMMdq_MEMq =5570 ,
  XED_IFORM_VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512 =5571 ,
  XED_IFORM_VMOVLPS_MEMf32_XMMf32_AVX512 =5572 ,
  XED_IFORM_VMOVLPS_MEMq_XMMq =5573 ,
  XED_IFORM_VMOVLPS_XMMdq_XMMdq_MEMq =5574 ,
  XED_IFORM_VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512 =5575 ,
  XED_IFORM_VMOVMSKPD_GPR32d_XMMdq =5576 ,
  XED_IFORM_VMOVMSKPD_GPR32d_YMMqq =5577 ,
  XED_IFORM_VMOVMSKPS_GPR32d_XMMdq =5578 ,
  XED_IFORM_VMOVMSKPS_GPR32d_YMMqq =5579 ,
  XED_IFORM_VMOVNTDQ_MEMdq_XMMdq =5580 ,
  XED_IFORM_VMOVNTDQ_MEMqq_YMMqq =5581 ,
  XED_IFORM_VMOVNTDQ_MEMu32_XMMu32_AVX512 =5582 ,
  XED_IFORM_VMOVNTDQ_MEMu32_YMMu32_AVX512 =5583 ,
  XED_IFORM_VMOVNTDQ_MEMu32_ZMMu32_AVX512 =5584 ,
  XED_IFORM_VMOVNTDQA_XMMdq_MEMdq =5585 ,
  XED_IFORM_VMOVNTDQA_XMMu32_MEMu32_AVX512 =5586 ,
  XED_IFORM_VMOVNTDQA_YMMqq_MEMqq =5587 ,
  XED_IFORM_VMOVNTDQA_YMMu32_MEMu32_AVX512 =5588 ,
  XED_IFORM_VMOVNTDQA_ZMMu32_MEMu32_AVX512 =5589 ,
  XED_IFORM_VMOVNTPD_MEMdq_XMMdq =5590 ,
  XED_IFORM_VMOVNTPD_MEMf64_XMMf64_AVX512 =5591 ,
  XED_IFORM_VMOVNTPD_MEMf64_YMMf64_AVX512 =5592 ,
  XED_IFORM_VMOVNTPD_MEMf64_ZMMf64_AVX512 =5593 ,
  XED_IFORM_VMOVNTPD_MEMqq_YMMqq =5594 ,
  XED_IFORM_VMOVNTPS_MEMdq_XMMdq =5595 ,
  XED_IFORM_VMOVNTPS_MEMf32_XMMf32_AVX512 =5596 ,
  XED_IFORM_VMOVNTPS_MEMf32_YMMf32_AVX512 =5597 ,
  XED_IFORM_VMOVNTPS_MEMf32_ZMMf32_AVX512 =5598 ,
  XED_IFORM_VMOVNTPS_MEMqq_YMMqq =5599 ,
  XED_IFORM_VMOVQ_GPR64q_XMMq =5600 ,
  XED_IFORM_VMOVQ_GPR64u64_XMMu64_AVX512 =5601 ,
  XED_IFORM_VMOVQ_MEMq_XMMq_7E =5602 ,
  XED_IFORM_VMOVQ_MEMq_XMMq_D6 =5603 ,
  XED_IFORM_VMOVQ_MEMu64_XMMu64_AVX512 =5604 ,
  XED_IFORM_VMOVQ_XMMdq_GPR64q =5605 ,
  XED_IFORM_VMOVQ_XMMdq_MEMq_6E =5606 ,
  XED_IFORM_VMOVQ_XMMdq_MEMq_7E =5607 ,
  XED_IFORM_VMOVQ_XMMdq_XMMq_7E =5608 ,
  XED_IFORM_VMOVQ_XMMdq_XMMq_D6 =5609 ,
  XED_IFORM_VMOVQ_XMMu64_GPR64u64_AVX512 =5610 ,
  XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512 =5611 ,
  XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512 =5612 ,
  XED_IFORM_VMOVRSB_XMMu8_MASKmskw_MEMu8_AVX512 =5613 ,
  XED_IFORM_VMOVRSB_YMMu8_MASKmskw_MEMu8_AVX512 =5614 ,
  XED_IFORM_VMOVRSB_ZMMu8_MASKmskw_MEMu8_AVX512 =5615 ,
  XED_IFORM_VMOVRSD_XMMu32_MASKmskw_MEMu32_AVX512 =5616 ,
  XED_IFORM_VMOVRSD_YMMu32_MASKmskw_MEMu32_AVX512 =5617 ,
  XED_IFORM_VMOVRSD_ZMMu32_MASKmskw_MEMu32_AVX512 =5618 ,
  XED_IFORM_VMOVRSQ_XMMu64_MASKmskw_MEMu64_AVX512 =5619 ,
  XED_IFORM_VMOVRSQ_YMMu64_MASKmskw_MEMu64_AVX512 =5620 ,
  XED_IFORM_VMOVRSQ_ZMMu64_MASKmskw_MEMu64_AVX512 =5621 ,
  XED_IFORM_VMOVRSW_XMMu16_MASKmskw_MEMu16_AVX512 =5622 ,
  XED_IFORM_VMOVRSW_YMMu16_MASKmskw_MEMu16_AVX512 =5623 ,
  XED_IFORM_VMOVRSW_ZMMu16_MASKmskw_MEMu16_AVX512 =5624 ,
  XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512 =5625 ,
  XED_IFORM_VMOVSD_MEMq_XMMq =5626 ,
  XED_IFORM_VMOVSD_XMMdq_MEMq =5627 ,
  XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_10 =5628 ,
  XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_11 =5629 ,
  XED_IFORM_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512 =5630 ,
  XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5631 ,
  XED_IFORM_VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512 =5632 ,
  XED_IFORM_VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512 =5633 ,
  XED_IFORM_VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5634 ,
  XED_IFORM_VMOVSHDUP_XMMdq_MEMdq =5635 ,
  XED_IFORM_VMOVSHDUP_XMMdq_XMMdq =5636 ,
  XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512 =5637 ,
  XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512 =5638 ,
  XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512 =5639 ,
  XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512 =5640 ,
  XED_IFORM_VMOVSHDUP_YMMqq_MEMqq =5641 ,
  XED_IFORM_VMOVSHDUP_YMMqq_YMMqq =5642 ,
  XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512 =5643 ,
  XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 =5644 ,
  XED_IFORM_VMOVSLDUP_XMMdq_MEMdq =5645 ,
  XED_IFORM_VMOVSLDUP_XMMdq_XMMdq =5646 ,
  XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512 =5647 ,
  XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512 =5648 ,
  XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512 =5649 ,
  XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512 =5650 ,
  XED_IFORM_VMOVSLDUP_YMMqq_MEMqq =5651 ,
  XED_IFORM_VMOVSLDUP_YMMqq_YMMqq =5652 ,
  XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512 =5653 ,
  XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 =5654 ,
  XED_IFORM_VMOVSS_MEMd_XMMd =5655 ,
  XED_IFORM_VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512 =5656 ,
  XED_IFORM_VMOVSS_XMMdq_MEMd =5657 ,
  XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_10 =5658 ,
  XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_11 =5659 ,
  XED_IFORM_VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512 =5660 ,
  XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5661 ,
  XED_IFORM_VMOVUPD_MEMdq_XMMdq =5662 ,
  XED_IFORM_VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512 =5663 ,
  XED_IFORM_VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512 =5664 ,
  XED_IFORM_VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512 =5665 ,
  XED_IFORM_VMOVUPD_MEMqq_YMMqq =5666 ,
  XED_IFORM_VMOVUPD_XMMdq_MEMdq =5667 ,
  XED_IFORM_VMOVUPD_XMMdq_XMMdq_10 =5668 ,
  XED_IFORM_VMOVUPD_XMMdq_XMMdq_11 =5669 ,
  XED_IFORM_VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512 =5670 ,
  XED_IFORM_VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512 =5671 ,
  XED_IFORM_VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512 =5672 ,
  XED_IFORM_VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512 =5673 ,
  XED_IFORM_VMOVUPD_YMMqq_MEMqq =5674 ,
  XED_IFORM_VMOVUPD_YMMqq_YMMqq_10 =5675 ,
  XED_IFORM_VMOVUPD_YMMqq_YMMqq_11 =5676 ,
  XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512 =5677 ,
  XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512 =5678 ,
  XED_IFORM_VMOVUPS_MEMdq_XMMdq =5679 ,
  XED_IFORM_VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512 =5680 ,
  XED_IFORM_VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512 =5681 ,
  XED_IFORM_VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512 =5682 ,
  XED_IFORM_VMOVUPS_MEMqq_YMMqq =5683 ,
  XED_IFORM_VMOVUPS_XMMdq_MEMdq =5684 ,
  XED_IFORM_VMOVUPS_XMMdq_XMMdq_10 =5685 ,
  XED_IFORM_VMOVUPS_XMMdq_XMMdq_11 =5686 ,
  XED_IFORM_VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512 =5687 ,
  XED_IFORM_VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512 =5688 ,
  XED_IFORM_VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512 =5689 ,
  XED_IFORM_VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512 =5690 ,
  XED_IFORM_VMOVUPS_YMMqq_MEMqq =5691 ,
  XED_IFORM_VMOVUPS_YMMqq_YMMqq_10 =5692 ,
  XED_IFORM_VMOVUPS_YMMqq_YMMqq_11 =5693 ,
  XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512 =5694 ,
  XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512 =5695 ,
  XED_IFORM_VMOVW_GPR32f16_XMMf16_AVX512 =5696 ,
  XED_IFORM_VMOVW_MEMf16_XMMf16_AVX512 =5697 ,
  XED_IFORM_VMOVW_MEMu16_XMMu16_AVX512_MOVZXC =5698 ,
  XED_IFORM_VMOVW_XMMf16_GPR32f16_AVX512 =5699 ,
  XED_IFORM_VMOVW_XMMf16_MEMf16_AVX512 =5700 ,
  XED_IFORM_VMOVW_XMMu16_MEMu16_AVX512_MOVZXC =5701 ,
  XED_IFORM_VMOVW_XMMu16_XMMu16_AVX512_MOVZXC =5702 ,
  XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb =5703 ,
  XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb =5704 ,
  XED_IFORM_VMPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 =5705 ,
  XED_IFORM_VMPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 =5706 ,
  XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb =5707 ,
  XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb =5708 ,
  XED_IFORM_VMPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 =5709 ,
  XED_IFORM_VMPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 =5710 ,
  XED_IFORM_VMPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 =5711 ,
  XED_IFORM_VMPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 =5712 ,
  XED_IFORM_VMPTRLD_MEMq =5713 ,
  XED_IFORM_VMPTRST_MEMq =5714 ,
  XED_IFORM_VMREAD_GPR32_GPR32 =5715 ,
  XED_IFORM_VMREAD_GPR64_GPR64 =5716 ,
  XED_IFORM_VMREAD_MEMd_GPR32 =5717 ,
  XED_IFORM_VMREAD_MEMq_GPR64 =5718 ,
  XED_IFORM_VMRESUME =5719 ,
  XED_IFORM_VMRUN_ArAX =5720 ,
  XED_IFORM_VMSAVE =5721 ,
  XED_IFORM_VMULBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =5722 ,
  XED_IFORM_VMULBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =5723 ,
  XED_IFORM_VMULBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =5724 ,
  XED_IFORM_VMULBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =5725 ,
  XED_IFORM_VMULBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =5726 ,
  XED_IFORM_VMULBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =5727 ,
  XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq =5728 ,
  XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq =5729 ,
  XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5730 ,
  XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5731 ,
  XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =5732 ,
  XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =5733 ,
  XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq =5734 ,
  XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq =5735 ,
  XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =5736 ,
  XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =5737 ,
  XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5738 ,
  XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5739 ,
  XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =5740 ,
  XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =5741 ,
  XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =5742 ,
  XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =5743 ,
  XED_IFORM_VMULPS_XMMdq_XMMdq_MEMdq =5744 ,
  XED_IFORM_VMULPS_XMMdq_XMMdq_XMMdq =5745 ,
  XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5746 ,
  XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5747 ,
  XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =5748 ,
  XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =5749 ,
  XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq =5750 ,
  XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq =5751 ,
  XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =5752 ,
  XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =5753 ,
  XED_IFORM_VMULSD_XMMdq_XMMdq_MEMq =5754 ,
  XED_IFORM_VMULSD_XMMdq_XMMdq_XMMq =5755 ,
  XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =5756 ,
  XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =5757 ,
  XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =5758 ,
  XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =5759 ,
  XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd =5760 ,
  XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd =5761 ,
  XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =5762 ,
  XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =5763 ,
  XED_IFORM_VMWRITE_GPR32_GPR32 =5764 ,
  XED_IFORM_VMWRITE_GPR32_MEMd =5765 ,
  XED_IFORM_VMWRITE_GPR64_GPR64 =5766 ,
  XED_IFORM_VMWRITE_GPR64_MEMq =5767 ,
  XED_IFORM_VMXOFF =5768 ,
  XED_IFORM_VMXON_MEMq =5769 ,
  XED_IFORM_VORPD_XMMdq_XMMdq_MEMdq =5770 ,
  XED_IFORM_VORPD_XMMdq_XMMdq_XMMdq =5771 ,
  XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =5772 ,
  XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =5773 ,
  XED_IFORM_VORPD_YMMqq_YMMqq_MEMqq =5774 ,
  XED_IFORM_VORPD_YMMqq_YMMqq_YMMqq =5775 ,
  XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =5776 ,
  XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =5777 ,
  XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =5778 ,
  XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =5779 ,
  XED_IFORM_VORPS_XMMdq_XMMdq_MEMdq =5780 ,
  XED_IFORM_VORPS_XMMdq_XMMdq_XMMdq =5781 ,
  XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =5782 ,
  XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =5783 ,
  XED_IFORM_VORPS_YMMqq_YMMqq_MEMqq =5784 ,
  XED_IFORM_VORPS_YMMqq_YMMqq_YMMqq =5785 ,
  XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =5786 ,
  XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =5787 ,
  XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =5788 ,
  XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =5789 ,
  XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512 =5790 ,
  XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512 =5791 ,
  XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512 =5792 ,
  XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512 =5793 ,
  XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512 =5794 ,
  XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512 =5795 ,
  XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512 =5796 ,
  XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512 =5797 ,
  XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512 =5798 ,
  XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512 =5799 ,
  XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512 =5800 ,
  XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512 =5801 ,
  XED_IFORM_VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 =5802 ,
  XED_IFORM_VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 =5803 ,
  XED_IFORM_VPABSB_XMMdq_MEMdq =5804 ,
  XED_IFORM_VPABSB_XMMdq_XMMdq =5805 ,
  XED_IFORM_VPABSB_XMMi8_MASKmskw_MEMi8_AVX512 =5806 ,
  XED_IFORM_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512 =5807 ,
  XED_IFORM_VPABSB_YMMi8_MASKmskw_MEMi8_AVX512 =5808 ,
  XED_IFORM_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512 =5809 ,
  XED_IFORM_VPABSB_YMMqq_MEMqq =5810 ,
  XED_IFORM_VPABSB_YMMqq_YMMqq =5811 ,
  XED_IFORM_VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512 =5812 ,
  XED_IFORM_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512 =5813 ,
  XED_IFORM_VPABSD_XMMdq_MEMdq =5814 ,
  XED_IFORM_VPABSD_XMMdq_XMMdq =5815 ,
  XED_IFORM_VPABSD_XMMi32_MASKmskw_MEMi32_AVX512 =5816 ,
  XED_IFORM_VPABSD_XMMi32_MASKmskw_XMMi32_AVX512 =5817 ,
  XED_IFORM_VPABSD_YMMi32_MASKmskw_MEMi32_AVX512 =5818 ,
  XED_IFORM_VPABSD_YMMi32_MASKmskw_YMMi32_AVX512 =5819 ,
  XED_IFORM_VPABSD_YMMqq_MEMqq =5820 ,
  XED_IFORM_VPABSD_YMMqq_YMMqq =5821 ,
  XED_IFORM_VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512 =5822 ,
  XED_IFORM_VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512 =5823 ,
  XED_IFORM_VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512 =5824 ,
  XED_IFORM_VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512 =5825 ,
  XED_IFORM_VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512 =5826 ,
  XED_IFORM_VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512 =5827 ,
  XED_IFORM_VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512 =5828 ,
  XED_IFORM_VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512 =5829 ,
  XED_IFORM_VPABSW_XMMdq_MEMdq =5830 ,
  XED_IFORM_VPABSW_XMMdq_XMMdq =5831 ,
  XED_IFORM_VPABSW_XMMi16_MASKmskw_MEMi16_AVX512 =5832 ,
  XED_IFORM_VPABSW_XMMi16_MASKmskw_XMMi16_AVX512 =5833 ,
  XED_IFORM_VPABSW_YMMi16_MASKmskw_MEMi16_AVX512 =5834 ,
  XED_IFORM_VPABSW_YMMi16_MASKmskw_YMMi16_AVX512 =5835 ,
  XED_IFORM_VPABSW_YMMqq_MEMqq =5836 ,
  XED_IFORM_VPABSW_YMMqq_YMMqq =5837 ,
  XED_IFORM_VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512 =5838 ,
  XED_IFORM_VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512 =5839 ,
  XED_IFORM_VPACKSSDW_XMMdq_XMMdq_MEMdq =5840 ,
  XED_IFORM_VPACKSSDW_XMMdq_XMMdq_XMMdq =5841 ,
  XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512 =5842 ,
  XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512 =5843 ,
  XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512 =5844 ,
  XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512 =5845 ,
  XED_IFORM_VPACKSSDW_YMMqq_YMMqq_MEMqq =5846 ,
  XED_IFORM_VPACKSSDW_YMMqq_YMMqq_YMMqq =5847 ,
  XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512 =5848 ,
  XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512 =5849 ,
  XED_IFORM_VPACKSSWB_XMMdq_XMMdq_MEMdq =5850 ,
  XED_IFORM_VPACKSSWB_XMMdq_XMMdq_XMMdq =5851 ,
  XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512 =5852 ,
  XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512 =5853 ,
  XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512 =5854 ,
  XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512 =5855 ,
  XED_IFORM_VPACKSSWB_YMMqq_YMMqq_MEMqq =5856 ,
  XED_IFORM_VPACKSSWB_YMMqq_YMMqq_YMMqq =5857 ,
  XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512 =5858 ,
  XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512 =5859 ,
  XED_IFORM_VPACKUSDW_XMMdq_XMMdq_MEMdq =5860 ,
  XED_IFORM_VPACKUSDW_XMMdq_XMMdq_XMMdq =5861 ,
  XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512 =5862 ,
  XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512 =5863 ,
  XED_IFORM_VPACKUSDW_YMMqq_YMMqq_MEMqq =5864 ,
  XED_IFORM_VPACKUSDW_YMMqq_YMMqq_YMMqq =5865 ,
  XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512 =5866 ,
  XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512 =5867 ,
  XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512 =5868 ,
  XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512 =5869 ,
  XED_IFORM_VPACKUSWB_XMMdq_XMMdq_MEMdq =5870 ,
  XED_IFORM_VPACKUSWB_XMMdq_XMMdq_XMMdq =5871 ,
  XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512 =5872 ,
  XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512 =5873 ,
  XED_IFORM_VPACKUSWB_YMMqq_YMMqq_MEMqq =5874 ,
  XED_IFORM_VPACKUSWB_YMMqq_YMMqq_YMMqq =5875 ,
  XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512 =5876 ,
  XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512 =5877 ,
  XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512 =5878 ,
  XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512 =5879 ,
  XED_IFORM_VPADDB_XMMdq_XMMdq_MEMdq =5880 ,
  XED_IFORM_VPADDB_XMMdq_XMMdq_XMMdq =5881 ,
  XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =5882 ,
  XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =5883 ,
  XED_IFORM_VPADDB_YMMqq_YMMqq_MEMqq =5884 ,
  XED_IFORM_VPADDB_YMMqq_YMMqq_YMMqq =5885 ,
  XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =5886 ,
  XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =5887 ,
  XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =5888 ,
  XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =5889 ,
  XED_IFORM_VPADDD_XMMdq_XMMdq_MEMdq =5890 ,
  XED_IFORM_VPADDD_XMMdq_XMMdq_XMMdq =5891 ,
  XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =5892 ,
  XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =5893 ,
  XED_IFORM_VPADDD_YMMqq_YMMqq_MEMqq =5894 ,
  XED_IFORM_VPADDD_YMMqq_YMMqq_YMMqq =5895 ,
  XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =5896 ,
  XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =5897 ,
  XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =5898 ,
  XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =5899 ,
  XED_IFORM_VPADDQ_XMMdq_XMMdq_MEMdq =5900 ,
  XED_IFORM_VPADDQ_XMMdq_XMMdq_XMMdq =5901 ,
  XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =5902 ,
  XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =5903 ,
  XED_IFORM_VPADDQ_YMMqq_YMMqq_MEMqq =5904 ,
  XED_IFORM_VPADDQ_YMMqq_YMMqq_YMMqq =5905 ,
  XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =5906 ,
  XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =5907 ,
  XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =5908 ,
  XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =5909 ,
  XED_IFORM_VPADDSB_XMMdq_XMMdq_MEMdq =5910 ,
  XED_IFORM_VPADDSB_XMMdq_XMMdq_XMMdq =5911 ,
  XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 =5912 ,
  XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 =5913 ,
  XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 =5914 ,
  XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 =5915 ,
  XED_IFORM_VPADDSB_YMMqq_YMMqq_MEMqq =5916 ,
  XED_IFORM_VPADDSB_YMMqq_YMMqq_YMMqq =5917 ,
  XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 =5918 ,
  XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 =5919 ,
  XED_IFORM_VPADDSW_XMMdq_XMMdq_MEMdq =5920 ,
  XED_IFORM_VPADDSW_XMMdq_XMMdq_XMMdq =5921 ,
  XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 =5922 ,
  XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 =5923 ,
  XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 =5924 ,
  XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 =5925 ,
  XED_IFORM_VPADDSW_YMMqq_YMMqq_MEMqq =5926 ,
  XED_IFORM_VPADDSW_YMMqq_YMMqq_YMMqq =5927 ,
  XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 =5928 ,
  XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 =5929 ,
  XED_IFORM_VPADDUSB_XMMdq_XMMdq_MEMdq =5930 ,
  XED_IFORM_VPADDUSB_XMMdq_XMMdq_XMMdq =5931 ,
  XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =5932 ,
  XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =5933 ,
  XED_IFORM_VPADDUSB_YMMqq_YMMqq_MEMqq =5934 ,
  XED_IFORM_VPADDUSB_YMMqq_YMMqq_YMMqq =5935 ,
  XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =5936 ,
  XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =5937 ,
  XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =5938 ,
  XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =5939 ,
  XED_IFORM_VPADDUSW_XMMdq_XMMdq_MEMdq =5940 ,
  XED_IFORM_VPADDUSW_XMMdq_XMMdq_XMMdq =5941 ,
  XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =5942 ,
  XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =5943 ,
  XED_IFORM_VPADDUSW_YMMqq_YMMqq_MEMqq =5944 ,
  XED_IFORM_VPADDUSW_YMMqq_YMMqq_YMMqq =5945 ,
  XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =5946 ,
  XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =5947 ,
  XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =5948 ,
  XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =5949 ,
  XED_IFORM_VPADDW_XMMdq_XMMdq_MEMdq =5950 ,
  XED_IFORM_VPADDW_XMMdq_XMMdq_XMMdq =5951 ,
  XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =5952 ,
  XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =5953 ,
  XED_IFORM_VPADDW_YMMqq_YMMqq_MEMqq =5954 ,
  XED_IFORM_VPADDW_YMMqq_YMMqq_YMMqq =5955 ,
  XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =5956 ,
  XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =5957 ,
  XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =5958 ,
  XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =5959 ,
  XED_IFORM_VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb =5960 ,
  XED_IFORM_VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb =5961 ,
  XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 =5962 ,
  XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 =5963 ,
  XED_IFORM_VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb =5964 ,
  XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb =5965 ,
  XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 =5966 ,
  XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 =5967 ,
  XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 =5968 ,
  XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 =5969 ,
  XED_IFORM_VPAND_XMMdq_XMMdq_MEMdq =5970 ,
  XED_IFORM_VPAND_XMMdq_XMMdq_XMMdq =5971 ,
  XED_IFORM_VPAND_YMMqq_YMMqq_MEMqq =5972 ,
  XED_IFORM_VPAND_YMMqq_YMMqq_YMMqq =5973 ,
  XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =5974 ,
  XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =5975 ,
  XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =5976 ,
  XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =5977 ,
  XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =5978 ,
  XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =5979 ,
  XED_IFORM_VPANDN_XMMdq_XMMdq_MEMdq =5980 ,
  XED_IFORM_VPANDN_XMMdq_XMMdq_XMMdq =5981 ,
  XED_IFORM_VPANDN_YMMqq_YMMqq_MEMqq =5982 ,
  XED_IFORM_VPANDN_YMMqq_YMMqq_YMMqq =5983 ,
  XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =5984 ,
  XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =5985 ,
  XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =5986 ,
  XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =5987 ,
  XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =5988 ,
  XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =5989 ,
  XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =5990 ,
  XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =5991 ,
  XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =5992 ,
  XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =5993 ,
  XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =5994 ,
  XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =5995 ,
  XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =5996 ,
  XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =5997 ,
  XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =5998 ,
  XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =5999 ,
  XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =6000 ,
  XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =6001 ,
  XED_IFORM_VPAVGB_XMMdq_XMMdq_MEMdq =6002 ,
  XED_IFORM_VPAVGB_XMMdq_XMMdq_XMMdq =6003 ,
  XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =6004 ,
  XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =6005 ,
  XED_IFORM_VPAVGB_YMMqq_YMMqq_MEMqq =6006 ,
  XED_IFORM_VPAVGB_YMMqq_YMMqq_YMMqq =6007 ,
  XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =6008 ,
  XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =6009 ,
  XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =6010 ,
  XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =6011 ,
  XED_IFORM_VPAVGW_XMMdq_XMMdq_MEMdq =6012 ,
  XED_IFORM_VPAVGW_XMMdq_XMMdq_XMMdq =6013 ,
  XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =6014 ,
  XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =6015 ,
  XED_IFORM_VPAVGW_YMMqq_YMMqq_MEMqq =6016 ,
  XED_IFORM_VPAVGW_YMMqq_YMMqq_YMMqq =6017 ,
  XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =6018 ,
  XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =6019 ,
  XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =6020 ,
  XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =6021 ,
  XED_IFORM_VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb =6022 ,
  XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb =6023 ,
  XED_IFORM_VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb =6024 ,
  XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb =6025 ,
  XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =6026 ,
  XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =6027 ,
  XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =6028 ,
  XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =6029 ,
  XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =6030 ,
  XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =6031 ,
  XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =6032 ,
  XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =6033 ,
  XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =6034 ,
  XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =6035 ,
  XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =6036 ,
  XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =6037 ,
  XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =6038 ,
  XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =6039 ,
  XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =6040 ,
  XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =6041 ,
  XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =6042 ,
  XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =6043 ,
  XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =6044 ,
  XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =6045 ,
  XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =6046 ,
  XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =6047 ,
  XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =6048 ,
  XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =6049 ,
  XED_IFORM_VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq =6050 ,
  XED_IFORM_VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq =6051 ,
  XED_IFORM_VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq =6052 ,
  XED_IFORM_VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq =6053 ,
  XED_IFORM_VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb =6054 ,
  XED_IFORM_VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb =6055 ,
  XED_IFORM_VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb =6056 ,
  XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb =6057 ,
  XED_IFORM_VPBROADCASTB_XMMdq_MEMb =6058 ,
  XED_IFORM_VPBROADCASTB_XMMdq_XMMb =6059 ,
  XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512 =6060 ,
  XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512 =6061 ,
  XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512 =6062 ,
  XED_IFORM_VPBROADCASTB_YMMqq_MEMb =6063 ,
  XED_IFORM_VPBROADCASTB_YMMqq_XMMb =6064 ,
  XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512 =6065 ,
  XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512 =6066 ,
  XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512 =6067 ,
  XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512 =6068 ,
  XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512 =6069 ,
  XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512 =6070 ,
  XED_IFORM_VPBROADCASTD_XMMdq_MEMd =6071 ,
  XED_IFORM_VPBROADCASTD_XMMdq_XMMd =6072 ,
  XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512 =6073 ,
  XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512 =6074 ,
  XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512 =6075 ,
  XED_IFORM_VPBROADCASTD_YMMqq_MEMd =6076 ,
  XED_IFORM_VPBROADCASTD_YMMqq_XMMd =6077 ,
  XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512 =6078 ,
  XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512 =6079 ,
  XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512 =6080 ,
  XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512 =6081 ,
  XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512 =6082 ,
  XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512 =6083 ,
  XED_IFORM_VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512 =6084 ,
  XED_IFORM_VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512 =6085 ,
  XED_IFORM_VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD =6086 ,
  XED_IFORM_VPBROADCASTMW2D_XMMu32_MASKu32_AVX512 =6087 ,
  XED_IFORM_VPBROADCASTMW2D_YMMu32_MASKu32_AVX512 =6088 ,
  XED_IFORM_VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD =6089 ,
  XED_IFORM_VPBROADCASTQ_XMMdq_MEMq =6090 ,
  XED_IFORM_VPBROADCASTQ_XMMdq_XMMq =6091 ,
  XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512 =6092 ,
  XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512 =6093 ,
  XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512 =6094 ,
  XED_IFORM_VPBROADCASTQ_YMMqq_MEMq =6095 ,
  XED_IFORM_VPBROADCASTQ_YMMqq_XMMq =6096 ,
  XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512 =6097 ,
  XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512 =6098 ,
  XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512 =6099 ,
  XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512 =6100 ,
  XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512 =6101 ,
  XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512 =6102 ,
  XED_IFORM_VPBROADCASTW_XMMdq_MEMw =6103 ,
  XED_IFORM_VPBROADCASTW_XMMdq_XMMw =6104 ,
  XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512 =6105 ,
  XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512 =6106 ,
  XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512 =6107 ,
  XED_IFORM_VPBROADCASTW_YMMqq_MEMw =6108 ,
  XED_IFORM_VPBROADCASTW_YMMqq_XMMw =6109 ,
  XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512 =6110 ,
  XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512 =6111 ,
  XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512 =6112 ,
  XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512 =6113 ,
  XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512 =6114 ,
  XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512 =6115 ,
  XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb =6116 ,
  XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb =6117 ,
  XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512 =6118 ,
  XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512 =6119 ,
  XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8 =6120 ,
  XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512 =6121 ,
  XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8 =6122 ,
  XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512 =6123 ,
  XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512 =6124 ,
  XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512 =6125 ,
  XED_IFORM_VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq =6126 ,
  XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq =6127 ,
  XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq =6128 ,
  XED_IFORM_VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq =6129 ,
  XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq =6130 ,
  XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq =6131 ,
  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512 =6132 ,
  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512 =6133 ,
  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512 =6134 ,
  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512 =6135 ,
  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512 =6136 ,
  XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512 =6137 ,
  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512 =6138 ,
  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512 =6139 ,
  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512 =6140 ,
  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512 =6141 ,
  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512 =6142 ,
  XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512 =6143 ,
  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 =6144 ,
  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 =6145 ,
  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 =6146 ,
  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 =6147 ,
  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 =6148 ,
  XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 =6149 ,
  XED_IFORM_VPCMPEQB_XMMdq_XMMdq_MEMdq =6150 ,
  XED_IFORM_VPCMPEQB_XMMdq_XMMdq_XMMdq =6151 ,
  XED_IFORM_VPCMPEQB_YMMqq_YMMqq_MEMqq =6152 ,
  XED_IFORM_VPCMPEQB_YMMqq_YMMqq_YMMqq =6153 ,
  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 =6154 ,
  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 =6155 ,
  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 =6156 ,
  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 =6157 ,
  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 =6158 ,
  XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 =6159 ,
  XED_IFORM_VPCMPEQD_XMMdq_XMMdq_MEMdq =6160 ,
  XED_IFORM_VPCMPEQD_XMMdq_XMMdq_XMMdq =6161 ,
  XED_IFORM_VPCMPEQD_YMMqq_YMMqq_MEMqq =6162 ,
  XED_IFORM_VPCMPEQD_YMMqq_YMMqq_YMMqq =6163 ,
  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 =6164 ,
  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 =6165 ,
  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 =6166 ,
  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 =6167 ,
  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 =6168 ,
  XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 =6169 ,
  XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_MEMdq =6170 ,
  XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_XMMdq =6171 ,
  XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_MEMqq =6172 ,
  XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_YMMqq =6173 ,
  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 =6174 ,
  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 =6175 ,
  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 =6176 ,
  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 =6177 ,
  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 =6178 ,
  XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 =6179 ,
  XED_IFORM_VPCMPEQW_XMMdq_XMMdq_MEMdq =6180 ,
  XED_IFORM_VPCMPEQW_XMMdq_XMMdq_XMMdq =6181 ,
  XED_IFORM_VPCMPEQW_YMMqq_YMMqq_MEMqq =6182 ,
  XED_IFORM_VPCMPEQW_YMMqq_YMMqq_YMMqq =6183 ,
  XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb =6184 ,
  XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb =6185 ,
  XED_IFORM_VPCMPESTRI64_XMMdq_MEMdq_IMMb =6186 ,
  XED_IFORM_VPCMPESTRI64_XMMdq_XMMdq_IMMb =6187 ,
  XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb =6188 ,
  XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb =6189 ,
  XED_IFORM_VPCMPESTRM64_XMMdq_MEMdq_IMMb =6190 ,
  XED_IFORM_VPCMPESTRM64_XMMdq_XMMdq_IMMb =6191 ,
  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 =6192 ,
  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 =6193 ,
  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 =6194 ,
  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 =6195 ,
  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 =6196 ,
  XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 =6197 ,
  XED_IFORM_VPCMPGTB_XMMdq_XMMdq_MEMdq =6198 ,
  XED_IFORM_VPCMPGTB_XMMdq_XMMdq_XMMdq =6199 ,
  XED_IFORM_VPCMPGTB_YMMqq_YMMqq_MEMqq =6200 ,
  XED_IFORM_VPCMPGTB_YMMqq_YMMqq_YMMqq =6201 ,
  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512 =6202 ,
  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512 =6203 ,
  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512 =6204 ,
  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512 =6205 ,
  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512 =6206 ,
  XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512 =6207 ,
  XED_IFORM_VPCMPGTD_XMMdq_XMMdq_MEMdq =6208 ,
  XED_IFORM_VPCMPGTD_XMMdq_XMMdq_XMMdq =6209 ,
  XED_IFORM_VPCMPGTD_YMMqq_YMMqq_MEMqq =6210 ,
  XED_IFORM_VPCMPGTD_YMMqq_YMMqq_YMMqq =6211 ,
  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512 =6212 ,
  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512 =6213 ,
  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512 =6214 ,
  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512 =6215 ,
  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512 =6216 ,
  XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512 =6217 ,
  XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_MEMdq =6218 ,
  XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_XMMdq =6219 ,
  XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_MEMqq =6220 ,
  XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_YMMqq =6221 ,
  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 =6222 ,
  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 =6223 ,
  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 =6224 ,
  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 =6225 ,
  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 =6226 ,
  XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 =6227 ,
  XED_IFORM_VPCMPGTW_XMMdq_XMMdq_MEMdq =6228 ,
  XED_IFORM_VPCMPGTW_XMMdq_XMMdq_XMMdq =6229 ,
  XED_IFORM_VPCMPGTW_YMMqq_YMMqq_MEMqq =6230 ,
  XED_IFORM_VPCMPGTW_YMMqq_YMMqq_YMMqq =6231 ,
  XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb =6232 ,
  XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb =6233 ,
  XED_IFORM_VPCMPISTRI64_XMMdq_MEMdq_IMMb =6234 ,
  XED_IFORM_VPCMPISTRI64_XMMdq_XMMdq_IMMb =6235 ,
  XED_IFORM_VPCMPISTRM_XMMdq_MEMdq_IMMb =6236 ,
  XED_IFORM_VPCMPISTRM_XMMdq_XMMdq_IMMb =6237 ,
  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512 =6238 ,
  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512 =6239 ,
  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512 =6240 ,
  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512 =6241 ,
  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512 =6242 ,
  XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512 =6243 ,
  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 =6244 ,
  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 =6245 ,
  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 =6246 ,
  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 =6247 ,
  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 =6248 ,
  XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 =6249 ,
  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 =6250 ,
  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 =6251 ,
  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 =6252 ,
  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 =6253 ,
  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 =6254 ,
  XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 =6255 ,
  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 =6256 ,
  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 =6257 ,
  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 =6258 ,
  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 =6259 ,
  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 =6260 ,
  XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 =6261 ,
  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 =6262 ,
  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 =6263 ,
  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 =6264 ,
  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 =6265 ,
  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 =6266 ,
  XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 =6267 ,
  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512 =6268 ,
  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512 =6269 ,
  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512 =6270 ,
  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512 =6271 ,
  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512 =6272 ,
  XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512 =6273 ,
  XED_IFORM_VPCOMB_XMMdq_XMMdq_MEMdq_IMMb =6274 ,
  XED_IFORM_VPCOMB_XMMdq_XMMdq_XMMdq_IMMb =6275 ,
  XED_IFORM_VPCOMD_XMMdq_XMMdq_MEMdq_IMMb =6276 ,
  XED_IFORM_VPCOMD_XMMdq_XMMdq_XMMdq_IMMb =6277 ,
  XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512 =6278 ,
  XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512 =6279 ,
  XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512 =6280 ,
  XED_IFORM_VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512 =6281 ,
  XED_IFORM_VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512 =6282 ,
  XED_IFORM_VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512 =6283 ,
  XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512 =6284 ,
  XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512 =6285 ,
  XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512 =6286 ,
  XED_IFORM_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512 =6287 ,
  XED_IFORM_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512 =6288 ,
  XED_IFORM_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512 =6289 ,
  XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512 =6290 ,
  XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512 =6291 ,
  XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512 =6292 ,
  XED_IFORM_VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512 =6293 ,
  XED_IFORM_VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512 =6294 ,
  XED_IFORM_VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512 =6295 ,
  XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512 =6296 ,
  XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512 =6297 ,
  XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512 =6298 ,
  XED_IFORM_VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512 =6299 ,
  XED_IFORM_VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512 =6300 ,
  XED_IFORM_VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512 =6301 ,
  XED_IFORM_VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb =6302 ,
  XED_IFORM_VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb =6303 ,
  XED_IFORM_VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb =6304 ,
  XED_IFORM_VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb =6305 ,
  XED_IFORM_VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb =6306 ,
  XED_IFORM_VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb =6307 ,
  XED_IFORM_VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb =6308 ,
  XED_IFORM_VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb =6309 ,
  XED_IFORM_VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb =6310 ,
  XED_IFORM_VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb =6311 ,
  XED_IFORM_VPCOMW_XMMdq_XMMdq_MEMdq_IMMb =6312 ,
  XED_IFORM_VPCOMW_XMMdq_XMMdq_XMMdq_IMMb =6313 ,
  XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512 =6314 ,
  XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512 =6315 ,
  XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512 =6316 ,
  XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512 =6317 ,
  XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD =6318 ,
  XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD =6319 ,
  XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512 =6320 ,
  XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512 =6321 ,
  XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512 =6322 ,
  XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512 =6323 ,
  XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD =6324 ,
  XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD =6325 ,
  XED_IFORM_VPDPBSSD_XMMi32_MASKmskw_XMM4i8_MEM4i8_AVX512 =6326 ,
  XED_IFORM_VPDPBSSD_XMMi32_MASKmskw_XMM4i8_XMM4i8_AVX512 =6327 ,
  XED_IFORM_VPDPBSSD_XMMi32_XMM4i8_MEM4i8 =6328 ,
  XED_IFORM_VPDPBSSD_XMMi32_XMM4i8_XMM4i8 =6329 ,
  XED_IFORM_VPDPBSSD_YMMi32_MASKmskw_YMM4i8_MEM4i8_AVX512 =6330 ,
  XED_IFORM_VPDPBSSD_YMMi32_MASKmskw_YMM4i8_YMM4i8_AVX512 =6331 ,
  XED_IFORM_VPDPBSSD_YMMi32_YMM4i8_MEM4i8 =6332 ,
  XED_IFORM_VPDPBSSD_YMMi32_YMM4i8_YMM4i8 =6333 ,
  XED_IFORM_VPDPBSSD_ZMMi32_MASKmskw_ZMM4i8_MEM4i8_AVX512 =6334 ,
  XED_IFORM_VPDPBSSD_ZMMi32_MASKmskw_ZMM4i8_ZMM4i8_AVX512 =6335 ,
  XED_IFORM_VPDPBSSDS_XMMi32_MASKmskw_XMM4i8_MEM4i8_AVX512 =6336 ,
  XED_IFORM_VPDPBSSDS_XMMi32_MASKmskw_XMM4i8_XMM4i8_AVX512 =6337 ,
  XED_IFORM_VPDPBSSDS_XMMi32_XMM4i8_MEM4i8 =6338 ,
  XED_IFORM_VPDPBSSDS_XMMi32_XMM4i8_XMM4i8 =6339 ,
  XED_IFORM_VPDPBSSDS_YMMi32_MASKmskw_YMM4i8_MEM4i8_AVX512 =6340 ,
  XED_IFORM_VPDPBSSDS_YMMi32_MASKmskw_YMM4i8_YMM4i8_AVX512 =6341 ,
  XED_IFORM_VPDPBSSDS_YMMi32_YMM4i8_MEM4i8 =6342 ,
  XED_IFORM_VPDPBSSDS_YMMi32_YMM4i8_YMM4i8 =6343 ,
  XED_IFORM_VPDPBSSDS_ZMMi32_MASKmskw_ZMM4i8_MEM4i8_AVX512 =6344 ,
  XED_IFORM_VPDPBSSDS_ZMMi32_MASKmskw_ZMM4i8_ZMM4i8_AVX512 =6345 ,
  XED_IFORM_VPDPBSUD_XMMi32_MASKmskw_XMM4i8_MEM4u8_AVX512 =6346 ,
  XED_IFORM_VPDPBSUD_XMMi32_MASKmskw_XMM4i8_XMM4u8_AVX512 =6347 ,
  XED_IFORM_VPDPBSUD_XMMi32_XMM4i8_MEM4u8 =6348 ,
  XED_IFORM_VPDPBSUD_XMMi32_XMM4i8_XMM4u8 =6349 ,
  XED_IFORM_VPDPBSUD_YMMi32_MASKmskw_YMM4i8_MEM4u8_AVX512 =6350 ,
  XED_IFORM_VPDPBSUD_YMMi32_MASKmskw_YMM4i8_YMM4u8_AVX512 =6351 ,
  XED_IFORM_VPDPBSUD_YMMi32_YMM4i8_MEM4u8 =6352 ,
  XED_IFORM_VPDPBSUD_YMMi32_YMM4i8_YMM4u8 =6353 ,
  XED_IFORM_VPDPBSUD_ZMMi32_MASKmskw_ZMM4i8_MEM4u8_AVX512 =6354 ,
  XED_IFORM_VPDPBSUD_ZMMi32_MASKmskw_ZMM4i8_ZMM4u8_AVX512 =6355 ,
  XED_IFORM_VPDPBSUDS_XMMi32_MASKmskw_XMM4i8_MEM4u8_AVX512 =6356 ,
  XED_IFORM_VPDPBSUDS_XMMi32_MASKmskw_XMM4i8_XMM4u8_AVX512 =6357 ,
  XED_IFORM_VPDPBSUDS_XMMi32_XMM4i8_MEM4u8 =6358 ,
  XED_IFORM_VPDPBSUDS_XMMi32_XMM4i8_XMM4u8 =6359 ,
  XED_IFORM_VPDPBSUDS_YMMi32_MASKmskw_YMM4i8_MEM4u8_AVX512 =6360 ,
  XED_IFORM_VPDPBSUDS_YMMi32_MASKmskw_YMM4i8_YMM4u8_AVX512 =6361 ,
  XED_IFORM_VPDPBSUDS_YMMi32_YMM4i8_MEM4u8 =6362 ,
  XED_IFORM_VPDPBSUDS_YMMi32_YMM4i8_YMM4u8 =6363 ,
  XED_IFORM_VPDPBSUDS_ZMMi32_MASKmskw_ZMM4i8_MEM4u8_AVX512 =6364 ,
  XED_IFORM_VPDPBSUDS_ZMMi32_MASKmskw_ZMM4i8_ZMM4u8_AVX512 =6365 ,
  XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 =6366 ,
  XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 =6367 ,
  XED_IFORM_VPDPBUSD_XMMi32_XMMu32_MEMu32 =6368 ,
  XED_IFORM_VPDPBUSD_XMMi32_XMMu32_XMMu32 =6369 ,
  XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 =6370 ,
  XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 =6371 ,
  XED_IFORM_VPDPBUSD_YMMi32_YMMu32_MEMu32 =6372 ,
  XED_IFORM_VPDPBUSD_YMMi32_YMMu32_YMMu32 =6373 ,
  XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 =6374 ,
  XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 =6375 ,
  XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 =6376 ,
  XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 =6377 ,
  XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_MEMu32 =6378 ,
  XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_XMMu32 =6379 ,
  XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 =6380 ,
  XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 =6381 ,
  XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_MEMu32 =6382 ,
  XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_YMMu32 =6383 ,
  XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 =6384 ,
  XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 =6385 ,
  XED_IFORM_VPDPBUUD_XMMu32_MASKmskw_XMM4u8_MEM4u8_AVX512 =6386 ,
  XED_IFORM_VPDPBUUD_XMMu32_MASKmskw_XMM4u8_XMM4u8_AVX512 =6387 ,
  XED_IFORM_VPDPBUUD_XMMu32_XMM4u8_MEM4u8 =6388 ,
  XED_IFORM_VPDPBUUD_XMMu32_XMM4u8_XMM4u8 =6389 ,
  XED_IFORM_VPDPBUUD_YMMu32_MASKmskw_YMM4u8_MEM4u8_AVX512 =6390 ,
  XED_IFORM_VPDPBUUD_YMMu32_MASKmskw_YMM4u8_YMM4u8_AVX512 =6391 ,
  XED_IFORM_VPDPBUUD_YMMu32_YMM4u8_MEM4u8 =6392 ,
  XED_IFORM_VPDPBUUD_YMMu32_YMM4u8_YMM4u8 =6393 ,
  XED_IFORM_VPDPBUUD_ZMMu32_MASKmskw_ZMM4u8_MEM4u8_AVX512 =6394 ,
  XED_IFORM_VPDPBUUD_ZMMu32_MASKmskw_ZMM4u8_ZMM4u8_AVX512 =6395 ,
  XED_IFORM_VPDPBUUDS_XMMu32_MASKmskw_XMM4u8_MEM4u8_AVX512 =6396 ,
  XED_IFORM_VPDPBUUDS_XMMu32_MASKmskw_XMM4u8_XMM4u8_AVX512 =6397 ,
  XED_IFORM_VPDPBUUDS_XMMu32_XMM4u8_MEM4u8 =6398 ,
  XED_IFORM_VPDPBUUDS_XMMu32_XMM4u8_XMM4u8 =6399 ,
  XED_IFORM_VPDPBUUDS_YMMu32_MASKmskw_YMM4u8_MEM4u8_AVX512 =6400 ,
  XED_IFORM_VPDPBUUDS_YMMu32_MASKmskw_YMM4u8_YMM4u8_AVX512 =6401 ,
  XED_IFORM_VPDPBUUDS_YMMu32_YMM4u8_MEM4u8 =6402 ,
  XED_IFORM_VPDPBUUDS_YMMu32_YMM4u8_YMM4u8 =6403 ,
  XED_IFORM_VPDPBUUDS_ZMMu32_MASKmskw_ZMM4u8_MEM4u8_AVX512 =6404 ,
  XED_IFORM_VPDPBUUDS_ZMMu32_MASKmskw_ZMM4u8_ZMM4u8_AVX512 =6405 ,
  XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 =6406 ,
  XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 =6407 ,
  XED_IFORM_VPDPWSSD_XMMi32_XMMu32_MEMu32 =6408 ,
  XED_IFORM_VPDPWSSD_XMMi32_XMMu32_XMMu32 =6409 ,
  XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 =6410 ,
  XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 =6411 ,
  XED_IFORM_VPDPWSSD_YMMi32_YMMu32_MEMu32 =6412 ,
  XED_IFORM_VPDPWSSD_YMMi32_YMMu32_YMMu32 =6413 ,
  XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 =6414 ,
  XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 =6415 ,
  XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 =6416 ,
  XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 =6417 ,
  XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_MEMu32 =6418 ,
  XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_XMMu32 =6419 ,
  XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 =6420 ,
  XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 =6421 ,
  XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_MEMu32 =6422 ,
  XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_YMMu32 =6423 ,
  XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 =6424 ,
  XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 =6425 ,
  XED_IFORM_VPDPWSUD_XMMi32_MASKmskw_XMM2i16_MEM2u16_AVX512 =6426 ,
  XED_IFORM_VPDPWSUD_XMMi32_MASKmskw_XMM2i16_XMM2u16_AVX512 =6427 ,
  XED_IFORM_VPDPWSUD_XMMi32_XMM2i16_MEM2u16 =6428 ,
  XED_IFORM_VPDPWSUD_XMMi32_XMM2i16_XMM2u16 =6429 ,
  XED_IFORM_VPDPWSUD_YMMi32_MASKmskw_YMM2i16_MEM2u16_AVX512 =6430 ,
  XED_IFORM_VPDPWSUD_YMMi32_MASKmskw_YMM2i16_YMM2u16_AVX512 =6431 ,
  XED_IFORM_VPDPWSUD_YMMi32_YMM2i16_MEM2u16 =6432 ,
  XED_IFORM_VPDPWSUD_YMMi32_YMM2i16_YMM2u16 =6433 ,
  XED_IFORM_VPDPWSUD_ZMMi32_MASKmskw_ZMM2i16_MEM2u16_AVX512 =6434 ,
  XED_IFORM_VPDPWSUD_ZMMi32_MASKmskw_ZMM2i16_ZMM2u16_AVX512 =6435 ,
  XED_IFORM_VPDPWSUDS_XMMi32_MASKmskw_XMM2i16_MEM2u16_AVX512 =6436 ,
  XED_IFORM_VPDPWSUDS_XMMi32_MASKmskw_XMM2i16_XMM2u16_AVX512 =6437 ,
  XED_IFORM_VPDPWSUDS_XMMi32_XMM2i16_MEM2u16 =6438 ,
  XED_IFORM_VPDPWSUDS_XMMi32_XMM2i16_XMM2u16 =6439 ,
  XED_IFORM_VPDPWSUDS_YMMi32_MASKmskw_YMM2i16_MEM2u16_AVX512 =6440 ,
  XED_IFORM_VPDPWSUDS_YMMi32_MASKmskw_YMM2i16_YMM2u16_AVX512 =6441 ,
  XED_IFORM_VPDPWSUDS_YMMi32_YMM2i16_MEM2u16 =6442 ,
  XED_IFORM_VPDPWSUDS_YMMi32_YMM2i16_YMM2u16 =6443 ,
  XED_IFORM_VPDPWSUDS_ZMMi32_MASKmskw_ZMM2i16_MEM2u16_AVX512 =6444 ,
  XED_IFORM_VPDPWSUDS_ZMMi32_MASKmskw_ZMM2i16_ZMM2u16_AVX512 =6445 ,
  XED_IFORM_VPDPWUSD_XMMi32_MASKmskw_XMM2u16_MEM2i16_AVX512 =6446 ,
  XED_IFORM_VPDPWUSD_XMMi32_MASKmskw_XMM2u16_XMM2i16_AVX512 =6447 ,
  XED_IFORM_VPDPWUSD_XMMi32_XMM2u16_MEM2i16 =6448 ,
  XED_IFORM_VPDPWUSD_XMMi32_XMM2u16_XMM2i16 =6449 ,
  XED_IFORM_VPDPWUSD_YMMi32_MASKmskw_YMM2u16_MEM2i16_AVX512 =6450 ,
  XED_IFORM_VPDPWUSD_YMMi32_MASKmskw_YMM2u16_YMM2i16_AVX512 =6451 ,
  XED_IFORM_VPDPWUSD_YMMi32_YMM2u16_MEM2i16 =6452 ,
  XED_IFORM_VPDPWUSD_YMMi32_YMM2u16_YMM2i16 =6453 ,
  XED_IFORM_VPDPWUSD_ZMMi32_MASKmskw_ZMM2u16_MEM2i16_AVX512 =6454 ,
  XED_IFORM_VPDPWUSD_ZMMi32_MASKmskw_ZMM2u16_ZMM2i16_AVX512 =6455 ,
  XED_IFORM_VPDPWUSDS_XMMi32_MASKmskw_XMM2u16_MEM2i16_AVX512 =6456 ,
  XED_IFORM_VPDPWUSDS_XMMi32_MASKmskw_XMM2u16_XMM2i16_AVX512 =6457 ,
  XED_IFORM_VPDPWUSDS_XMMi32_XMM2u16_MEM2i16 =6458 ,
  XED_IFORM_VPDPWUSDS_XMMi32_XMM2u16_XMM2i16 =6459 ,
  XED_IFORM_VPDPWUSDS_YMMi32_MASKmskw_YMM2u16_MEM2i16_AVX512 =6460 ,
  XED_IFORM_VPDPWUSDS_YMMi32_MASKmskw_YMM2u16_YMM2i16_AVX512 =6461 ,
  XED_IFORM_VPDPWUSDS_YMMi32_YMM2u16_MEM2i16 =6462 ,
  XED_IFORM_VPDPWUSDS_YMMi32_YMM2u16_YMM2i16 =6463 ,
  XED_IFORM_VPDPWUSDS_ZMMi32_MASKmskw_ZMM2u16_MEM2i16_AVX512 =6464 ,
  XED_IFORM_VPDPWUSDS_ZMMi32_MASKmskw_ZMM2u16_ZMM2i16_AVX512 =6465 ,
  XED_IFORM_VPDPWUUD_XMMu32_MASKmskw_XMM2u16_MEM2u16_AVX512 =6466 ,
  XED_IFORM_VPDPWUUD_XMMu32_MASKmskw_XMM2u16_XMM2u16_AVX512 =6467 ,
  XED_IFORM_VPDPWUUD_XMMu32_XMM2u16_MEM2u16 =6468 ,
  XED_IFORM_VPDPWUUD_XMMu32_XMM2u16_XMM2u16 =6469 ,
  XED_IFORM_VPDPWUUD_YMMu32_MASKmskw_YMM2u16_MEM2u16_AVX512 =6470 ,
  XED_IFORM_VPDPWUUD_YMMu32_MASKmskw_YMM2u16_YMM2u16_AVX512 =6471 ,
  XED_IFORM_VPDPWUUD_YMMu32_YMM2u16_MEM2u16 =6472 ,
  XED_IFORM_VPDPWUUD_YMMu32_YMM2u16_YMM2u16 =6473 ,
  XED_IFORM_VPDPWUUD_ZMMu32_MASKmskw_ZMM2u16_MEM2u16_AVX512 =6474 ,
  XED_IFORM_VPDPWUUD_ZMMu32_MASKmskw_ZMM2u16_ZMM2u16_AVX512 =6475 ,
  XED_IFORM_VPDPWUUDS_XMMu32_MASKmskw_XMM2u16_MEM2u16_AVX512 =6476 ,
  XED_IFORM_VPDPWUUDS_XMMu32_MASKmskw_XMM2u16_XMM2u16_AVX512 =6477 ,
  XED_IFORM_VPDPWUUDS_XMMu32_XMM2u16_MEM2u16 =6478 ,
  XED_IFORM_VPDPWUUDS_XMMu32_XMM2u16_XMM2u16 =6479 ,
  XED_IFORM_VPDPWUUDS_YMMu32_MASKmskw_YMM2u16_MEM2u16_AVX512 =6480 ,
  XED_IFORM_VPDPWUUDS_YMMu32_MASKmskw_YMM2u16_YMM2u16_AVX512 =6481 ,
  XED_IFORM_VPDPWUUDS_YMMu32_YMM2u16_MEM2u16 =6482 ,
  XED_IFORM_VPDPWUUDS_YMMu32_YMM2u16_YMM2u16 =6483 ,
  XED_IFORM_VPDPWUUDS_ZMMu32_MASKmskw_ZMM2u16_MEM2u16_AVX512 =6484 ,
  XED_IFORM_VPDPWUUDS_ZMMu32_MASKmskw_ZMM2u16_ZMM2u16_AVX512 =6485 ,
  XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb =6486 ,
  XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb =6487 ,
  XED_IFORM_VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb =6488 ,
  XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb =6489 ,
  XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =6490 ,
  XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =6491 ,
  XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =6492 ,
  XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =6493 ,
  XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =6494 ,
  XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =6495 ,
  XED_IFORM_VPERMD_YMMqq_YMMqq_MEMqq =6496 ,
  XED_IFORM_VPERMD_YMMqq_YMMqq_YMMqq =6497 ,
  XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =6498 ,
  XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =6499 ,
  XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =6500 ,
  XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =6501 ,
  XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =6502 ,
  XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =6503 ,
  XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =6504 ,
  XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =6505 ,
  XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =6506 ,
  XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =6507 ,
  XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =6508 ,
  XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =6509 ,
  XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =6510 ,
  XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =6511 ,
  XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =6512 ,
  XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =6513 ,
  XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =6514 ,
  XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =6515 ,
  XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =6516 ,
  XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =6517 ,
  XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =6518 ,
  XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =6519 ,
  XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =6520 ,
  XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =6521 ,
  XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =6522 ,
  XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =6523 ,
  XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =6524 ,
  XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =6525 ,
  XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =6526 ,
  XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =6527 ,
  XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =6528 ,
  XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =6529 ,
  XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =6530 ,
  XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =6531 ,
  XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =6532 ,
  XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =6533 ,
  XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =6534 ,
  XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =6535 ,
  XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =6536 ,
  XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =6537 ,
  XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb =6538 ,
  XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb =6539 ,
  XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb =6540 ,
  XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb =6541 ,
  XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb =6542 ,
  XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb =6543 ,
  XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb =6544 ,
  XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb =6545 ,
  XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb =6546 ,
  XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb =6547 ,
  XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb =6548 ,
  XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb =6549 ,
  XED_IFORM_VPERMILPD_XMMdq_MEMdq_IMMb =6550 ,
  XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb =6551 ,
  XED_IFORM_VPERMILPD_XMMdq_XMMdq_MEMdq =6552 ,
  XED_IFORM_VPERMILPD_XMMdq_XMMdq_XMMdq =6553 ,
  XED_IFORM_VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 =6554 ,
  XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 =6555 ,
  XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =6556 ,
  XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =6557 ,
  XED_IFORM_VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 =6558 ,
  XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 =6559 ,
  XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =6560 ,
  XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =6561 ,
  XED_IFORM_VPERMILPD_YMMqq_MEMqq_IMMb =6562 ,
  XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb =6563 ,
  XED_IFORM_VPERMILPD_YMMqq_YMMqq_MEMqq =6564 ,
  XED_IFORM_VPERMILPD_YMMqq_YMMqq_YMMqq =6565 ,
  XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 =6566 ,
  XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 =6567 ,
  XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =6568 ,
  XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =6569 ,
  XED_IFORM_VPERMILPS_XMMdq_MEMdq_IMMb =6570 ,
  XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb =6571 ,
  XED_IFORM_VPERMILPS_XMMdq_XMMdq_MEMdq =6572 ,
  XED_IFORM_VPERMILPS_XMMdq_XMMdq_XMMdq =6573 ,
  XED_IFORM_VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 =6574 ,
  XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 =6575 ,
  XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =6576 ,
  XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =6577 ,
  XED_IFORM_VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 =6578 ,
  XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 =6579 ,
  XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =6580 ,
  XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =6581 ,
  XED_IFORM_VPERMILPS_YMMqq_MEMqq_IMMb =6582 ,
  XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb =6583 ,
  XED_IFORM_VPERMILPS_YMMqq_YMMqq_MEMqq =6584 ,
  XED_IFORM_VPERMILPS_YMMqq_YMMqq_YMMqq =6585 ,
  XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 =6586 ,
  XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 =6587 ,
  XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =6588 ,
  XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =6589 ,
  XED_IFORM_VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 =6590 ,
  XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 =6591 ,
  XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =6592 ,
  XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =6593 ,
  XED_IFORM_VPERMPD_YMMqq_MEMqq_IMMb =6594 ,
  XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb =6595 ,
  XED_IFORM_VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 =6596 ,
  XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 =6597 ,
  XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =6598 ,
  XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =6599 ,
  XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =6600 ,
  XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =6601 ,
  XED_IFORM_VPERMPS_YMMqq_YMMqq_MEMqq =6602 ,
  XED_IFORM_VPERMPS_YMMqq_YMMqq_YMMqq =6603 ,
  XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =6604 ,
  XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =6605 ,
  XED_IFORM_VPERMQ_YMMqq_MEMqq_IMMb =6606 ,
  XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb =6607 ,
  XED_IFORM_VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 =6608 ,
  XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 =6609 ,
  XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =6610 ,
  XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =6611 ,
  XED_IFORM_VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 =6612 ,
  XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 =6613 ,
  XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =6614 ,
  XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =6615 ,
  XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =6616 ,
  XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =6617 ,
  XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =6618 ,
  XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =6619 ,
  XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =6620 ,
  XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =6621 ,
  XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =6622 ,
  XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =6623 ,
  XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =6624 ,
  XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =6625 ,
  XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =6626 ,
  XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =6627 ,
  XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =6628 ,
  XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =6629 ,
  XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =6630 ,
  XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =6631 ,
  XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =6632 ,
  XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =6633 ,
  XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =6634 ,
  XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =6635 ,
  XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =6636 ,
  XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =6637 ,
  XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =6638 ,
  XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =6639 ,
  XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =6640 ,
  XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =6641 ,
  XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =6642 ,
  XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =6643 ,
  XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =6644 ,
  XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =6645 ,
  XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =6646 ,
  XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =6647 ,
  XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =6648 ,
  XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =6649 ,
  XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =6650 ,
  XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =6651 ,
  XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =6652 ,
  XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =6653 ,
  XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =6654 ,
  XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =6655 ,
  XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =6656 ,
  XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =6657 ,
  XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512 =6658 ,
  XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512 =6659 ,
  XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512 =6660 ,
  XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512 =6661 ,
  XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512 =6662 ,
  XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512 =6663 ,
  XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512 =6664 ,
  XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512 =6665 ,
  XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512 =6666 ,
  XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512 =6667 ,
  XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512 =6668 ,
  XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512 =6669 ,
  XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512 =6670 ,
  XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512 =6671 ,
  XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512 =6672 ,
  XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512 =6673 ,
  XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512 =6674 ,
  XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512 =6675 ,
  XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512 =6676 ,
  XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512 =6677 ,
  XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512 =6678 ,
  XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512 =6679 ,
  XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512 =6680 ,
  XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512 =6681 ,
  XED_IFORM_VPEXTRB_GPR32d_XMMdq_IMMb =6682 ,
  XED_IFORM_VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512 =6683 ,
  XED_IFORM_VPEXTRB_MEMb_XMMdq_IMMb =6684 ,
  XED_IFORM_VPEXTRB_MEMu8_XMMu8_IMM8_AVX512 =6685 ,
  XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb =6686 ,
  XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512 =6687 ,
  XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb =6688 ,
  XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 =6689 ,
  XED_IFORM_VPEXTRQ_GPR64q_XMMdq_IMMb =6690 ,
  XED_IFORM_VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512 =6691 ,
  XED_IFORM_VPEXTRQ_MEMq_XMMdq_IMMb =6692 ,
  XED_IFORM_VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512 =6693 ,
  XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_15 =6694 ,
  XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_C5 =6695 ,
  XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512 =6696 ,
  XED_IFORM_VPEXTRW_MEMu16_XMMu16_IMM8_AVX512 =6697 ,
  XED_IFORM_VPEXTRW_MEMw_XMMdq_IMMb =6698 ,
  XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5 =6699 ,
  XED_IFORM_VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 =6700 ,
  XED_IFORM_VPGATHERDD_XMMu32_MEMd_XMMi32_VL128 =6701 ,
  XED_IFORM_VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256 =6702 ,
  XED_IFORM_VPGATHERDD_YMMu32_MEMd_YMMi32_VL256 =6703 ,
  XED_IFORM_VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512 =6704 ,
  XED_IFORM_VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 =6705 ,
  XED_IFORM_VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128 =6706 ,
  XED_IFORM_VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 =6707 ,
  XED_IFORM_VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256 =6708 ,
  XED_IFORM_VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 =6709 ,
  XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 =6710 ,
  XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256 =6711 ,
  XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL128 =6712 ,
  XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL256 =6713 ,
  XED_IFORM_VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512 =6714 ,
  XED_IFORM_VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 =6715 ,
  XED_IFORM_VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128 =6716 ,
  XED_IFORM_VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 =6717 ,
  XED_IFORM_VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256 =6718 ,
  XED_IFORM_VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 =6719 ,
  XED_IFORM_VPHADDBD_XMMdq_MEMdq =6720 ,
  XED_IFORM_VPHADDBD_XMMdq_XMMdq =6721 ,
  XED_IFORM_VPHADDBQ_XMMdq_MEMdq =6722 ,
  XED_IFORM_VPHADDBQ_XMMdq_XMMdq =6723 ,
  XED_IFORM_VPHADDBW_XMMdq_MEMdq =6724 ,
  XED_IFORM_VPHADDBW_XMMdq_XMMdq =6725 ,
  XED_IFORM_VPHADDD_XMMdq_XMMdq_MEMdq =6726 ,
  XED_IFORM_VPHADDD_XMMdq_XMMdq_XMMdq =6727 ,
  XED_IFORM_VPHADDD_YMMqq_YMMqq_MEMqq =6728 ,
  XED_IFORM_VPHADDD_YMMqq_YMMqq_YMMqq =6729 ,
  XED_IFORM_VPHADDDQ_XMMdq_MEMdq =6730 ,
  XED_IFORM_VPHADDDQ_XMMdq_XMMdq =6731 ,
  XED_IFORM_VPHADDSW_XMMdq_XMMdq_MEMdq =6732 ,
  XED_IFORM_VPHADDSW_XMMdq_XMMdq_XMMdq =6733 ,
  XED_IFORM_VPHADDSW_YMMqq_YMMqq_MEMqq =6734 ,
  XED_IFORM_VPHADDSW_YMMqq_YMMqq_YMMqq =6735 ,
  XED_IFORM_VPHADDUBD_XMMdq_MEMdq =6736 ,
  XED_IFORM_VPHADDUBD_XMMdq_XMMdq =6737 ,
  XED_IFORM_VPHADDUBQ_XMMdq_MEMdq =6738 ,
  XED_IFORM_VPHADDUBQ_XMMdq_XMMdq =6739 ,
  XED_IFORM_VPHADDUBW_XMMdq_MEMdq =6740 ,
  XED_IFORM_VPHADDUBW_XMMdq_XMMdq =6741 ,
  XED_IFORM_VPHADDUDQ_XMMdq_MEMdq =6742 ,
  XED_IFORM_VPHADDUDQ_XMMdq_XMMdq =6743 ,
  XED_IFORM_VPHADDUWD_XMMdq_MEMdq =6744 ,
  XED_IFORM_VPHADDUWD_XMMdq_XMMdq =6745 ,
  XED_IFORM_VPHADDUWQ_XMMdq_MEMdq =6746 ,
  XED_IFORM_VPHADDUWQ_XMMdq_XMMdq =6747 ,
  XED_IFORM_VPHADDW_XMMdq_XMMdq_MEMdq =6748 ,
  XED_IFORM_VPHADDW_XMMdq_XMMdq_XMMdq =6749 ,
  XED_IFORM_VPHADDW_YMMqq_YMMqq_MEMqq =6750 ,
  XED_IFORM_VPHADDW_YMMqq_YMMqq_YMMqq =6751 ,
  XED_IFORM_VPHADDWD_XMMdq_MEMdq =6752 ,
  XED_IFORM_VPHADDWD_XMMdq_XMMdq =6753 ,
  XED_IFORM_VPHADDWQ_XMMdq_MEMdq =6754 ,
  XED_IFORM_VPHADDWQ_XMMdq_XMMdq =6755 ,
  XED_IFORM_VPHMINPOSUW_XMMdq_MEMdq =6756 ,
  XED_IFORM_VPHMINPOSUW_XMMdq_XMMdq =6757 ,
  XED_IFORM_VPHSUBBW_XMMdq_MEMdq =6758 ,
  XED_IFORM_VPHSUBBW_XMMdq_XMMdq =6759 ,
  XED_IFORM_VPHSUBD_XMMdq_XMMdq_MEMdq =6760 ,
  XED_IFORM_VPHSUBD_XMMdq_XMMdq_XMMdq =6761 ,
  XED_IFORM_VPHSUBD_YMMqq_YMMqq_MEMqq =6762 ,
  XED_IFORM_VPHSUBD_YMMqq_YMMqq_YMMqq =6763 ,
  XED_IFORM_VPHSUBDQ_XMMdq_MEMdq =6764 ,
  XED_IFORM_VPHSUBDQ_XMMdq_XMMdq =6765 ,
  XED_IFORM_VPHSUBSW_XMMdq_XMMdq_MEMdq =6766 ,
  XED_IFORM_VPHSUBSW_XMMdq_XMMdq_XMMdq =6767 ,
  XED_IFORM_VPHSUBSW_YMMqq_YMMqq_MEMqq =6768 ,
  XED_IFORM_VPHSUBSW_YMMqq_YMMqq_YMMqq =6769 ,
  XED_IFORM_VPHSUBW_XMMdq_XMMdq_MEMdq =6770 ,
  XED_IFORM_VPHSUBW_XMMdq_XMMdq_XMMdq =6771 ,
  XED_IFORM_VPHSUBW_YMMqq_YMMqq_MEMqq =6772 ,
  XED_IFORM_VPHSUBW_YMMqq_YMMqq_YMMqq =6773 ,
  XED_IFORM_VPHSUBWD_XMMdq_MEMdq =6774 ,
  XED_IFORM_VPHSUBWD_XMMdq_XMMdq =6775 ,
  XED_IFORM_VPINSRB_XMMdq_XMMdq_GPR32d_IMMb =6776 ,
  XED_IFORM_VPINSRB_XMMdq_XMMdq_MEMb_IMMb =6777 ,
  XED_IFORM_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512 =6778 ,
  XED_IFORM_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512 =6779 ,
  XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb =6780 ,
  XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb =6781 ,
  XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512 =6782 ,
  XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 =6783 ,
  XED_IFORM_VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb =6784 ,
  XED_IFORM_VPINSRQ_XMMdq_XMMdq_MEMq_IMMb =6785 ,
  XED_IFORM_VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512 =6786 ,
  XED_IFORM_VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512 =6787 ,
  XED_IFORM_VPINSRW_XMMdq_XMMdq_GPR32d_IMMb =6788 ,
  XED_IFORM_VPINSRW_XMMdq_XMMdq_MEMw_IMMb =6789 ,
  XED_IFORM_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512 =6790 ,
  XED_IFORM_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512 =6791 ,
  XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512 =6792 ,
  XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512 =6793 ,
  XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512 =6794 ,
  XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512 =6795 ,
  XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD =6796 ,
  XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD =6797 ,
  XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 =6798 ,
  XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 =6799 ,
  XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 =6800 ,
  XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 =6801 ,
  XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD =6802 ,
  XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD =6803 ,
  XED_IFORM_VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq =6804 ,
  XED_IFORM_VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq =6805 ,
  XED_IFORM_VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq =6806 ,
  XED_IFORM_VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq =6807 ,
  XED_IFORM_VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq =6808 ,
  XED_IFORM_VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq =6809 ,
  XED_IFORM_VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq =6810 ,
  XED_IFORM_VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq =6811 ,
  XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq =6812 ,
  XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq =6813 ,
  XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq =6814 ,
  XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq =6815 ,
  XED_IFORM_VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq =6816 ,
  XED_IFORM_VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq =6817 ,
  XED_IFORM_VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq =6818 ,
  XED_IFORM_VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq =6819 ,
  XED_IFORM_VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq =6820 ,
  XED_IFORM_VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq =6821 ,
  XED_IFORM_VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq =6822 ,
  XED_IFORM_VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq =6823 ,
  XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq =6824 ,
  XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq =6825 ,
  XED_IFORM_VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq =6826 ,
  XED_IFORM_VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq =6827 ,
  XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =6828 ,
  XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =6829 ,
  XED_IFORM_VPMADD52HUQ_XMMu64_XMMu64_MEMu64 =6830 ,
  XED_IFORM_VPMADD52HUQ_XMMu64_XMMu64_XMMu64 =6831 ,
  XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =6832 ,
  XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =6833 ,
  XED_IFORM_VPMADD52HUQ_YMMu64_YMMu64_MEMu64 =6834 ,
  XED_IFORM_VPMADD52HUQ_YMMu64_YMMu64_YMMu64 =6835 ,
  XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =6836 ,
  XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =6837 ,
  XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =6838 ,
  XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =6839 ,
  XED_IFORM_VPMADD52LUQ_XMMu64_XMMu64_MEMu64 =6840 ,
  XED_IFORM_VPMADD52LUQ_XMMu64_XMMu64_XMMu64 =6841 ,
  XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =6842 ,
  XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =6843 ,
  XED_IFORM_VPMADD52LUQ_YMMu64_YMMu64_MEMu64 =6844 ,
  XED_IFORM_VPMADD52LUQ_YMMu64_YMMu64_YMMu64 =6845 ,
  XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =6846 ,
  XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =6847 ,
  XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_MEMdq =6848 ,
  XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_XMMdq =6849 ,
  XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 =6850 ,
  XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 =6851 ,
  XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 =6852 ,
  XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 =6853 ,
  XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_MEMqq =6854 ,
  XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_YMMqq =6855 ,
  XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 =6856 ,
  XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 =6857 ,
  XED_IFORM_VPMADDWD_XMMdq_XMMdq_MEMdq =6858 ,
  XED_IFORM_VPMADDWD_XMMdq_XMMdq_XMMdq =6859 ,
  XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512 =6860 ,
  XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512 =6861 ,
  XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512 =6862 ,
  XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512 =6863 ,
  XED_IFORM_VPMADDWD_YMMqq_YMMqq_MEMqq =6864 ,
  XED_IFORM_VPMADDWD_YMMqq_YMMqq_YMMqq =6865 ,
  XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512 =6866 ,
  XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512 =6867 ,
  XED_IFORM_VPMASKMOVD_MEMdq_XMMdq_XMMdq =6868 ,
  XED_IFORM_VPMASKMOVD_MEMqq_YMMqq_YMMqq =6869 ,
  XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq =6870 ,
  XED_IFORM_VPMASKMOVD_YMMqq_YMMqq_MEMqq =6871 ,
  XED_IFORM_VPMASKMOVQ_MEMdq_XMMdq_XMMdq =6872 ,
  XED_IFORM_VPMASKMOVQ_MEMqq_YMMqq_YMMqq =6873 ,
  XED_IFORM_VPMASKMOVQ_XMMdq_XMMdq_MEMdq =6874 ,
  XED_IFORM_VPMASKMOVQ_YMMqq_YMMqq_MEMqq =6875 ,
  XED_IFORM_VPMAXSB_XMMdq_XMMdq_MEMdq =6876 ,
  XED_IFORM_VPMAXSB_XMMdq_XMMdq_XMMdq =6877 ,
  XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 =6878 ,
  XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 =6879 ,
  XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 =6880 ,
  XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 =6881 ,
  XED_IFORM_VPMAXSB_YMMqq_YMMqq_MEMqq =6882 ,
  XED_IFORM_VPMAXSB_YMMqq_YMMqq_YMMqq =6883 ,
  XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 =6884 ,
  XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 =6885 ,
  XED_IFORM_VPMAXSD_XMMdq_XMMdq_MEMdq =6886 ,
  XED_IFORM_VPMAXSD_XMMdq_XMMdq_XMMdq =6887 ,
  XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 =6888 ,
  XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 =6889 ,
  XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 =6890 ,
  XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 =6891 ,
  XED_IFORM_VPMAXSD_YMMqq_YMMqq_MEMqq =6892 ,
  XED_IFORM_VPMAXSD_YMMqq_YMMqq_YMMqq =6893 ,
  XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 =6894 ,
  XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 =6895 ,
  XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 =6896 ,
  XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 =6897 ,
  XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 =6898 ,
  XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 =6899 ,
  XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 =6900 ,
  XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 =6901 ,
  XED_IFORM_VPMAXSW_XMMdq_XMMdq_MEMdq =6902 ,
  XED_IFORM_VPMAXSW_XMMdq_XMMdq_XMMdq =6903 ,
  XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 =6904 ,
  XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 =6905 ,
  XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 =6906 ,
  XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 =6907 ,
  XED_IFORM_VPMAXSW_YMMqq_YMMqq_MEMqq =6908 ,
  XED_IFORM_VPMAXSW_YMMqq_YMMqq_YMMqq =6909 ,
  XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 =6910 ,
  XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 =6911 ,
  XED_IFORM_VPMAXUB_XMMdq_XMMdq_MEMdq =6912 ,
  XED_IFORM_VPMAXUB_XMMdq_XMMdq_XMMdq =6913 ,
  XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =6914 ,
  XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =6915 ,
  XED_IFORM_VPMAXUB_YMMqq_YMMqq_MEMqq =6916 ,
  XED_IFORM_VPMAXUB_YMMqq_YMMqq_YMMqq =6917 ,
  XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =6918 ,
  XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =6919 ,
  XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =6920 ,
  XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =6921 ,
  XED_IFORM_VPMAXUD_XMMdq_XMMdq_MEMdq =6922 ,
  XED_IFORM_VPMAXUD_XMMdq_XMMdq_XMMdq =6923 ,
  XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =6924 ,
  XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =6925 ,
  XED_IFORM_VPMAXUD_YMMqq_YMMqq_MEMqq =6926 ,
  XED_IFORM_VPMAXUD_YMMqq_YMMqq_YMMqq =6927 ,
  XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =6928 ,
  XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =6929 ,
  XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =6930 ,
  XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =6931 ,
  XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =6932 ,
  XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =6933 ,
  XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =6934 ,
  XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =6935 ,
  XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =6936 ,
  XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =6937 ,
  XED_IFORM_VPMAXUW_XMMdq_XMMdq_MEMdq =6938 ,
  XED_IFORM_VPMAXUW_XMMdq_XMMdq_XMMdq =6939 ,
  XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =6940 ,
  XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =6941 ,
  XED_IFORM_VPMAXUW_YMMqq_YMMqq_MEMqq =6942 ,
  XED_IFORM_VPMAXUW_YMMqq_YMMqq_YMMqq =6943 ,
  XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =6944 ,
  XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =6945 ,
  XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =6946 ,
  XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =6947 ,
  XED_IFORM_VPMINSB_XMMdq_XMMdq_MEMdq =6948 ,
  XED_IFORM_VPMINSB_XMMdq_XMMdq_XMMdq =6949 ,
  XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 =6950 ,
  XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 =6951 ,
  XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 =6952 ,
  XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 =6953 ,
  XED_IFORM_VPMINSB_YMMqq_YMMqq_MEMqq =6954 ,
  XED_IFORM_VPMINSB_YMMqq_YMMqq_YMMqq =6955 ,
  XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 =6956 ,
  XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 =6957 ,
  XED_IFORM_VPMINSD_XMMdq_XMMdq_MEMdq =6958 ,
  XED_IFORM_VPMINSD_XMMdq_XMMdq_XMMdq =6959 ,
  XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 =6960 ,
  XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 =6961 ,
  XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 =6962 ,
  XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 =6963 ,
  XED_IFORM_VPMINSD_YMMqq_YMMqq_MEMqq =6964 ,
  XED_IFORM_VPMINSD_YMMqq_YMMqq_YMMqq =6965 ,
  XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 =6966 ,
  XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 =6967 ,
  XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 =6968 ,
  XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 =6969 ,
  XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 =6970 ,
  XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 =6971 ,
  XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 =6972 ,
  XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 =6973 ,
  XED_IFORM_VPMINSW_XMMdq_XMMdq_MEMdq =6974 ,
  XED_IFORM_VPMINSW_XMMdq_XMMdq_XMMdq =6975 ,
  XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 =6976 ,
  XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 =6977 ,
  XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 =6978 ,
  XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 =6979 ,
  XED_IFORM_VPMINSW_YMMqq_YMMqq_MEMqq =6980 ,
  XED_IFORM_VPMINSW_YMMqq_YMMqq_YMMqq =6981 ,
  XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 =6982 ,
  XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 =6983 ,
  XED_IFORM_VPMINUB_XMMdq_XMMdq_MEMdq =6984 ,
  XED_IFORM_VPMINUB_XMMdq_XMMdq_XMMdq =6985 ,
  XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =6986 ,
  XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =6987 ,
  XED_IFORM_VPMINUB_YMMqq_YMMqq_MEMqq =6988 ,
  XED_IFORM_VPMINUB_YMMqq_YMMqq_YMMqq =6989 ,
  XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =6990 ,
  XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =6991 ,
  XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =6992 ,
  XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =6993 ,
  XED_IFORM_VPMINUD_XMMdq_XMMdq_MEMdq =6994 ,
  XED_IFORM_VPMINUD_XMMdq_XMMdq_XMMdq =6995 ,
  XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =6996 ,
  XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =6997 ,
  XED_IFORM_VPMINUD_YMMqq_YMMqq_MEMqq =6998 ,
  XED_IFORM_VPMINUD_YMMqq_YMMqq_YMMqq =6999 ,
  XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7000 ,
  XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7001 ,
  XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7002 ,
  XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7003 ,
  XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7004 ,
  XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7005 ,
  XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7006 ,
  XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7007 ,
  XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7008 ,
  XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7009 ,
  XED_IFORM_VPMINUW_XMMdq_XMMdq_MEMdq =7010 ,
  XED_IFORM_VPMINUW_XMMdq_XMMdq_XMMdq =7011 ,
  XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7012 ,
  XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7013 ,
  XED_IFORM_VPMINUW_YMMqq_YMMqq_MEMqq =7014 ,
  XED_IFORM_VPMINUW_YMMqq_YMMqq_YMMqq =7015 ,
  XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7016 ,
  XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =7017 ,
  XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7018 ,
  XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =7019 ,
  XED_IFORM_VPMOVB2M_MASKmskw_XMMu8_AVX512 =7020 ,
  XED_IFORM_VPMOVB2M_MASKmskw_YMMu8_AVX512 =7021 ,
  XED_IFORM_VPMOVB2M_MASKmskw_ZMMu8_AVX512 =7022 ,
  XED_IFORM_VPMOVD2M_MASKmskw_XMMu32_AVX512 =7023 ,
  XED_IFORM_VPMOVD2M_MASKmskw_YMMu32_AVX512 =7024 ,
  XED_IFORM_VPMOVD2M_MASKmskw_ZMMu32_AVX512 =7025 ,
  XED_IFORM_VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512 =7026 ,
  XED_IFORM_VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512 =7027 ,
  XED_IFORM_VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512 =7028 ,
  XED_IFORM_VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512 =7029 ,
  XED_IFORM_VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512 =7030 ,
  XED_IFORM_VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512 =7031 ,
  XED_IFORM_VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512 =7032 ,
  XED_IFORM_VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512 =7033 ,
  XED_IFORM_VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512 =7034 ,
  XED_IFORM_VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512 =7035 ,
  XED_IFORM_VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512 =7036 ,
  XED_IFORM_VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512 =7037 ,
  XED_IFORM_VPMOVM2B_XMMu8_MASKmskw_AVX512 =7038 ,
  XED_IFORM_VPMOVM2B_YMMu8_MASKmskw_AVX512 =7039 ,
  XED_IFORM_VPMOVM2B_ZMMu8_MASKmskw_AVX512 =7040 ,
  XED_IFORM_VPMOVM2D_XMMu32_MASKmskw_AVX512 =7041 ,
  XED_IFORM_VPMOVM2D_YMMu32_MASKmskw_AVX512 =7042 ,
  XED_IFORM_VPMOVM2D_ZMMu32_MASKmskw_AVX512 =7043 ,
  XED_IFORM_VPMOVM2Q_XMMu64_MASKmskw_AVX512 =7044 ,
  XED_IFORM_VPMOVM2Q_YMMu64_MASKmskw_AVX512 =7045 ,
  XED_IFORM_VPMOVM2Q_ZMMu64_MASKmskw_AVX512 =7046 ,
  XED_IFORM_VPMOVM2W_XMMu16_MASKmskw_AVX512 =7047 ,
  XED_IFORM_VPMOVM2W_YMMu16_MASKmskw_AVX512 =7048 ,
  XED_IFORM_VPMOVM2W_ZMMu16_MASKmskw_AVX512 =7049 ,
  XED_IFORM_VPMOVMSKB_GPR32d_XMMdq =7050 ,
  XED_IFORM_VPMOVMSKB_GPR32d_YMMqq =7051 ,
  XED_IFORM_VPMOVQ2M_MASKmskw_XMMu64_AVX512 =7052 ,
  XED_IFORM_VPMOVQ2M_MASKmskw_YMMu64_AVX512 =7053 ,
  XED_IFORM_VPMOVQ2M_MASKmskw_ZMMu64_AVX512 =7054 ,
  XED_IFORM_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512 =7055 ,
  XED_IFORM_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512 =7056 ,
  XED_IFORM_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512 =7057 ,
  XED_IFORM_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512 =7058 ,
  XED_IFORM_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512 =7059 ,
  XED_IFORM_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512 =7060 ,
  XED_IFORM_VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512 =7061 ,
  XED_IFORM_VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512 =7062 ,
  XED_IFORM_VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512 =7063 ,
  XED_IFORM_VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512 =7064 ,
  XED_IFORM_VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512 =7065 ,
  XED_IFORM_VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512 =7066 ,
  XED_IFORM_VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512 =7067 ,
  XED_IFORM_VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512 =7068 ,
  XED_IFORM_VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512 =7069 ,
  XED_IFORM_VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512 =7070 ,
  XED_IFORM_VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512 =7071 ,
  XED_IFORM_VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512 =7072 ,
  XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512 =7073 ,
  XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512 =7074 ,
  XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512 =7075 ,
  XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512 =7076 ,
  XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512 =7077 ,
  XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512 =7078 ,
  XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512 =7079 ,
  XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512 =7080 ,
  XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512 =7081 ,
  XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512 =7082 ,
  XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512 =7083 ,
  XED_IFORM_VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512 =7084 ,
  XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512 =7085 ,
  XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512 =7086 ,
  XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512 =7087 ,
  XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512 =7088 ,
  XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512 =7089 ,
  XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512 =7090 ,
  XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512 =7091 ,
  XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512 =7092 ,
  XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512 =7093 ,
  XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512 =7094 ,
  XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512 =7095 ,
  XED_IFORM_VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512 =7096 ,
  XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512 =7097 ,
  XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512 =7098 ,
  XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512 =7099 ,
  XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512 =7100 ,
  XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512 =7101 ,
  XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512 =7102 ,
  XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512 =7103 ,
  XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512 =7104 ,
  XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512 =7105 ,
  XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512 =7106 ,
  XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512 =7107 ,
  XED_IFORM_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512 =7108 ,
  XED_IFORM_VPMOVSXBD_XMMdq_MEMd =7109 ,
  XED_IFORM_VPMOVSXBD_XMMdq_XMMd =7110 ,
  XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512 =7111 ,
  XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512 =7112 ,
  XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512 =7113 ,
  XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512 =7114 ,
  XED_IFORM_VPMOVSXBD_YMMqq_MEMq =7115 ,
  XED_IFORM_VPMOVSXBD_YMMqq_XMMq =7116 ,
  XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512 =7117 ,
  XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512 =7118 ,
  XED_IFORM_VPMOVSXBQ_XMMdq_MEMw =7119 ,
  XED_IFORM_VPMOVSXBQ_XMMdq_XMMw =7120 ,
  XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512 =7121 ,
  XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512 =7122 ,
  XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512 =7123 ,
  XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512 =7124 ,
  XED_IFORM_VPMOVSXBQ_YMMqq_MEMd =7125 ,
  XED_IFORM_VPMOVSXBQ_YMMqq_XMMd =7126 ,
  XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 =7127 ,
  XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 =7128 ,
  XED_IFORM_VPMOVSXBW_XMMdq_MEMq =7129 ,
  XED_IFORM_VPMOVSXBW_XMMdq_XMMq =7130 ,
  XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512 =7131 ,
  XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512 =7132 ,
  XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512 =7133 ,
  XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512 =7134 ,
  XED_IFORM_VPMOVSXBW_YMMqq_MEMdq =7135 ,
  XED_IFORM_VPMOVSXBW_YMMqq_XMMdq =7136 ,
  XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512 =7137 ,
  XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512 =7138 ,
  XED_IFORM_VPMOVSXDQ_XMMdq_MEMq =7139 ,
  XED_IFORM_VPMOVSXDQ_XMMdq_XMMq =7140 ,
  XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512 =7141 ,
  XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512 =7142 ,
  XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512 =7143 ,
  XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512 =7144 ,
  XED_IFORM_VPMOVSXDQ_YMMqq_MEMdq =7145 ,
  XED_IFORM_VPMOVSXDQ_YMMqq_XMMdq =7146 ,
  XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 =7147 ,
  XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 =7148 ,
  XED_IFORM_VPMOVSXWD_XMMdq_MEMq =7149 ,
  XED_IFORM_VPMOVSXWD_XMMdq_XMMq =7150 ,
  XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512 =7151 ,
  XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512 =7152 ,
  XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512 =7153 ,
  XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512 =7154 ,
  XED_IFORM_VPMOVSXWD_YMMqq_MEMdq =7155 ,
  XED_IFORM_VPMOVSXWD_YMMqq_XMMdq =7156 ,
  XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512 =7157 ,
  XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512 =7158 ,
  XED_IFORM_VPMOVSXWQ_XMMdq_MEMd =7159 ,
  XED_IFORM_VPMOVSXWQ_XMMdq_XMMd =7160 ,
  XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512 =7161 ,
  XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512 =7162 ,
  XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512 =7163 ,
  XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512 =7164 ,
  XED_IFORM_VPMOVSXWQ_YMMqq_MEMq =7165 ,
  XED_IFORM_VPMOVSXWQ_YMMqq_XMMq =7166 ,
  XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 =7167 ,
  XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 =7168 ,
  XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512 =7169 ,
  XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512 =7170 ,
  XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512 =7171 ,
  XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512 =7172 ,
  XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512 =7173 ,
  XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512 =7174 ,
  XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512 =7175 ,
  XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512 =7176 ,
  XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512 =7177 ,
  XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512 =7178 ,
  XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512 =7179 ,
  XED_IFORM_VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512 =7180 ,
  XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512 =7181 ,
  XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512 =7182 ,
  XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512 =7183 ,
  XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512 =7184 ,
  XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512 =7185 ,
  XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512 =7186 ,
  XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512 =7187 ,
  XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512 =7188 ,
  XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512 =7189 ,
  XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512 =7190 ,
  XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512 =7191 ,
  XED_IFORM_VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512 =7192 ,
  XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512 =7193 ,
  XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512 =7194 ,
  XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512 =7195 ,
  XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512 =7196 ,
  XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512 =7197 ,
  XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512 =7198 ,
  XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512 =7199 ,
  XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512 =7200 ,
  XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512 =7201 ,
  XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512 =7202 ,
  XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512 =7203 ,
  XED_IFORM_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512 =7204 ,
  XED_IFORM_VPMOVW2M_MASKmskw_XMMu16_AVX512 =7205 ,
  XED_IFORM_VPMOVW2M_MASKmskw_YMMu16_AVX512 =7206 ,
  XED_IFORM_VPMOVW2M_MASKmskw_ZMMu16_AVX512 =7207 ,
  XED_IFORM_VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512 =7208 ,
  XED_IFORM_VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512 =7209 ,
  XED_IFORM_VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512 =7210 ,
  XED_IFORM_VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512 =7211 ,
  XED_IFORM_VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512 =7212 ,
  XED_IFORM_VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512 =7213 ,
  XED_IFORM_VPMOVZXBD_XMMdq_MEMd =7214 ,
  XED_IFORM_VPMOVZXBD_XMMdq_XMMd =7215 ,
  XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512 =7216 ,
  XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512 =7217 ,
  XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512 =7218 ,
  XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512 =7219 ,
  XED_IFORM_VPMOVZXBD_YMMqq_MEMq =7220 ,
  XED_IFORM_VPMOVZXBD_YMMqq_XMMq =7221 ,
  XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512 =7222 ,
  XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512 =7223 ,
  XED_IFORM_VPMOVZXBQ_XMMdq_MEMw =7224 ,
  XED_IFORM_VPMOVZXBQ_XMMdq_XMMw =7225 ,
  XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512 =7226 ,
  XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512 =7227 ,
  XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512 =7228 ,
  XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512 =7229 ,
  XED_IFORM_VPMOVZXBQ_YMMqq_MEMd =7230 ,
  XED_IFORM_VPMOVZXBQ_YMMqq_XMMd =7231 ,
  XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 =7232 ,
  XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 =7233 ,
  XED_IFORM_VPMOVZXBW_XMMdq_MEMq =7234 ,
  XED_IFORM_VPMOVZXBW_XMMdq_XMMq =7235 ,
  XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512 =7236 ,
  XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512 =7237 ,
  XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512 =7238 ,
  XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512 =7239 ,
  XED_IFORM_VPMOVZXBW_YMMqq_MEMdq =7240 ,
  XED_IFORM_VPMOVZXBW_YMMqq_XMMdq =7241 ,
  XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512 =7242 ,
  XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512 =7243 ,
  XED_IFORM_VPMOVZXDQ_XMMdq_MEMq =7244 ,
  XED_IFORM_VPMOVZXDQ_XMMdq_XMMq =7245 ,
  XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512 =7246 ,
  XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512 =7247 ,
  XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512 =7248 ,
  XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512 =7249 ,
  XED_IFORM_VPMOVZXDQ_YMMqq_MEMdq =7250 ,
  XED_IFORM_VPMOVZXDQ_YMMqq_XMMdq =7251 ,
  XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 =7252 ,
  XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 =7253 ,
  XED_IFORM_VPMOVZXWD_XMMdq_MEMq =7254 ,
  XED_IFORM_VPMOVZXWD_XMMdq_XMMq =7255 ,
  XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512 =7256 ,
  XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512 =7257 ,
  XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512 =7258 ,
  XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512 =7259 ,
  XED_IFORM_VPMOVZXWD_YMMqq_MEMdq =7260 ,
  XED_IFORM_VPMOVZXWD_YMMqq_XMMdq =7261 ,
  XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512 =7262 ,
  XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512 =7263 ,
  XED_IFORM_VPMOVZXWQ_XMMdq_MEMd =7264 ,
  XED_IFORM_VPMOVZXWQ_XMMdq_XMMd =7265 ,
  XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512 =7266 ,
  XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512 =7267 ,
  XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512 =7268 ,
  XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512 =7269 ,
  XED_IFORM_VPMOVZXWQ_YMMqq_MEMq =7270 ,
  XED_IFORM_VPMOVZXWQ_YMMqq_XMMq =7271 ,
  XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 =7272 ,
  XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 =7273 ,
  XED_IFORM_VPMULDQ_XMMdq_XMMdq_MEMdq =7274 ,
  XED_IFORM_VPMULDQ_XMMdq_XMMdq_XMMdq =7275 ,
  XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 =7276 ,
  XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 =7277 ,
  XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 =7278 ,
  XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 =7279 ,
  XED_IFORM_VPMULDQ_YMMqq_YMMqq_MEMqq =7280 ,
  XED_IFORM_VPMULDQ_YMMqq_YMMqq_YMMqq =7281 ,
  XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 =7282 ,
  XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 =7283 ,
  XED_IFORM_VPMULHRSW_XMMdq_XMMdq_MEMdq =7284 ,
  XED_IFORM_VPMULHRSW_XMMdq_XMMdq_XMMdq =7285 ,
  XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 =7286 ,
  XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 =7287 ,
  XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 =7288 ,
  XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 =7289 ,
  XED_IFORM_VPMULHRSW_YMMqq_YMMqq_MEMqq =7290 ,
  XED_IFORM_VPMULHRSW_YMMqq_YMMqq_YMMqq =7291 ,
  XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 =7292 ,
  XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 =7293 ,
  XED_IFORM_VPMULHUW_XMMdq_XMMdq_MEMdq =7294 ,
  XED_IFORM_VPMULHUW_XMMdq_XMMdq_XMMdq =7295 ,
  XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7296 ,
  XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7297 ,
  XED_IFORM_VPMULHUW_YMMqq_YMMqq_MEMqq =7298 ,
  XED_IFORM_VPMULHUW_YMMqq_YMMqq_YMMqq =7299 ,
  XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7300 ,
  XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =7301 ,
  XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7302 ,
  XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =7303 ,
  XED_IFORM_VPMULHW_XMMdq_XMMdq_MEMdq =7304 ,
  XED_IFORM_VPMULHW_XMMdq_XMMdq_XMMdq =7305 ,
  XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7306 ,
  XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7307 ,
  XED_IFORM_VPMULHW_YMMqq_YMMqq_MEMqq =7308 ,
  XED_IFORM_VPMULHW_YMMqq_YMMqq_YMMqq =7309 ,
  XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7310 ,
  XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =7311 ,
  XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7312 ,
  XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =7313 ,
  XED_IFORM_VPMULLD_XMMdq_XMMdq_MEMdq =7314 ,
  XED_IFORM_VPMULLD_XMMdq_XMMdq_XMMdq =7315 ,
  XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7316 ,
  XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7317 ,
  XED_IFORM_VPMULLD_YMMqq_YMMqq_MEMqq =7318 ,
  XED_IFORM_VPMULLD_YMMqq_YMMqq_YMMqq =7319 ,
  XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7320 ,
  XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7321 ,
  XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7322 ,
  XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7323 ,
  XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7324 ,
  XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7325 ,
  XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7326 ,
  XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7327 ,
  XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7328 ,
  XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7329 ,
  XED_IFORM_VPMULLW_XMMdq_XMMdq_MEMdq =7330 ,
  XED_IFORM_VPMULLW_XMMdq_XMMdq_XMMdq =7331 ,
  XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7332 ,
  XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7333 ,
  XED_IFORM_VPMULLW_YMMqq_YMMqq_MEMqq =7334 ,
  XED_IFORM_VPMULLW_YMMqq_YMMqq_YMMqq =7335 ,
  XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7336 ,
  XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =7337 ,
  XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7338 ,
  XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =7339 ,
  XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512 =7340 ,
  XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512 =7341 ,
  XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512 =7342 ,
  XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512 =7343 ,
  XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512 =7344 ,
  XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512 =7345 ,
  XED_IFORM_VPMULUDQ_XMMdq_XMMdq_MEMdq =7346 ,
  XED_IFORM_VPMULUDQ_XMMdq_XMMdq_XMMdq =7347 ,
  XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7348 ,
  XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7349 ,
  XED_IFORM_VPMULUDQ_YMMqq_YMMqq_MEMqq =7350 ,
  XED_IFORM_VPMULUDQ_YMMqq_YMMqq_YMMqq =7351 ,
  XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7352 ,
  XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7353 ,
  XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7354 ,
  XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7355 ,
  XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512 =7356 ,
  XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512 =7357 ,
  XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512 =7358 ,
  XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512 =7359 ,
  XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512 =7360 ,
  XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512 =7361 ,
  XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512 =7362 ,
  XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512 =7363 ,
  XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512 =7364 ,
  XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512 =7365 ,
  XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512 =7366 ,
  XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512 =7367 ,
  XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 =7368 ,
  XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 =7369 ,
  XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 =7370 ,
  XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 =7371 ,
  XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512 =7372 ,
  XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512 =7373 ,
  XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512 =7374 ,
  XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512 =7375 ,
  XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512 =7376 ,
  XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512 =7377 ,
  XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512 =7378 ,
  XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512 =7379 ,
  XED_IFORM_VPOR_XMMdq_XMMdq_MEMdq =7380 ,
  XED_IFORM_VPOR_XMMdq_XMMdq_XMMdq =7381 ,
  XED_IFORM_VPOR_YMMqq_YMMqq_MEMqq =7382 ,
  XED_IFORM_VPOR_YMMqq_YMMqq_YMMqq =7383 ,
  XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7384 ,
  XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7385 ,
  XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7386 ,
  XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7387 ,
  XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7388 ,
  XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7389 ,
  XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7390 ,
  XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7391 ,
  XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7392 ,
  XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7393 ,
  XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7394 ,
  XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7395 ,
  XED_IFORM_VPPERM_XMMdq_XMMdq_MEMdq_XMMdq =7396 ,
  XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_MEMdq =7397 ,
  XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_XMMdq =7398 ,
  XED_IFORM_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7399 ,
  XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 =7400 ,
  XED_IFORM_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7401 ,
  XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 =7402 ,
  XED_IFORM_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7403 ,
  XED_IFORM_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 =7404 ,
  XED_IFORM_VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7405 ,
  XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 =7406 ,
  XED_IFORM_VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7407 ,
  XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 =7408 ,
  XED_IFORM_VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7409 ,
  XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 =7410 ,
  XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7411 ,
  XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7412 ,
  XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7413 ,
  XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7414 ,
  XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7415 ,
  XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7416 ,
  XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7417 ,
  XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7418 ,
  XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7419 ,
  XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7420 ,
  XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7421 ,
  XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7422 ,
  XED_IFORM_VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7423 ,
  XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 =7424 ,
  XED_IFORM_VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7425 ,
  XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 =7426 ,
  XED_IFORM_VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7427 ,
  XED_IFORM_VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 =7428 ,
  XED_IFORM_VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7429 ,
  XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 =7430 ,
  XED_IFORM_VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7431 ,
  XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 =7432 ,
  XED_IFORM_VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7433 ,
  XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 =7434 ,
  XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7435 ,
  XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7436 ,
  XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7437 ,
  XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7438 ,
  XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7439 ,
  XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7440 ,
  XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7441 ,
  XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7442 ,
  XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7443 ,
  XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7444 ,
  XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7445 ,
  XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7446 ,
  XED_IFORM_VPROTB_XMMdq_MEMdq_IMMb =7447 ,
  XED_IFORM_VPROTB_XMMdq_MEMdq_XMMdq =7448 ,
  XED_IFORM_VPROTB_XMMdq_XMMdq_IMMb =7449 ,
  XED_IFORM_VPROTB_XMMdq_XMMdq_MEMdq =7450 ,
  XED_IFORM_VPROTB_XMMdq_XMMdq_XMMdq =7451 ,
  XED_IFORM_VPROTD_XMMdq_MEMdq_IMMb =7452 ,
  XED_IFORM_VPROTD_XMMdq_MEMdq_XMMdq =7453 ,
  XED_IFORM_VPROTD_XMMdq_XMMdq_IMMb =7454 ,
  XED_IFORM_VPROTD_XMMdq_XMMdq_MEMdq =7455 ,
  XED_IFORM_VPROTD_XMMdq_XMMdq_XMMdq =7456 ,
  XED_IFORM_VPROTQ_XMMdq_MEMdq_IMMb =7457 ,
  XED_IFORM_VPROTQ_XMMdq_MEMdq_XMMdq =7458 ,
  XED_IFORM_VPROTQ_XMMdq_XMMdq_IMMb =7459 ,
  XED_IFORM_VPROTQ_XMMdq_XMMdq_MEMdq =7460 ,
  XED_IFORM_VPROTQ_XMMdq_XMMdq_XMMdq =7461 ,
  XED_IFORM_VPROTW_XMMdq_MEMdq_IMMb =7462 ,
  XED_IFORM_VPROTW_XMMdq_MEMdq_XMMdq =7463 ,
  XED_IFORM_VPROTW_XMMdq_XMMdq_IMMb =7464 ,
  XED_IFORM_VPROTW_XMMdq_XMMdq_MEMdq =7465 ,
  XED_IFORM_VPROTW_XMMdq_XMMdq_XMMdq =7466 ,
  XED_IFORM_VPSADBW_XMMdq_XMMdq_MEMdq =7467 ,
  XED_IFORM_VPSADBW_XMMdq_XMMdq_XMMdq =7468 ,
  XED_IFORM_VPSADBW_XMMu16_XMMu8_MEMu8_AVX512 =7469 ,
  XED_IFORM_VPSADBW_XMMu16_XMMu8_XMMu8_AVX512 =7470 ,
  XED_IFORM_VPSADBW_YMMqq_YMMqq_MEMqq =7471 ,
  XED_IFORM_VPSADBW_YMMqq_YMMqq_YMMqq =7472 ,
  XED_IFORM_VPSADBW_YMMu16_YMMu8_MEMu8_AVX512 =7473 ,
  XED_IFORM_VPSADBW_YMMu16_YMMu8_YMMu8_AVX512 =7474 ,
  XED_IFORM_VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512 =7475 ,
  XED_IFORM_VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512 =7476 ,
  XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 =7477 ,
  XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256 =7478 ,
  XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512 =7479 ,
  XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 =7480 ,
  XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 =7481 ,
  XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 =7482 ,
  XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 =7483 ,
  XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256 =7484 ,
  XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512 =7485 ,
  XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 =7486 ,
  XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 =7487 ,
  XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 =7488 ,
  XED_IFORM_VPSHAB_XMMdq_MEMdq_XMMdq =7489 ,
  XED_IFORM_VPSHAB_XMMdq_XMMdq_MEMdq =7490 ,
  XED_IFORM_VPSHAB_XMMdq_XMMdq_XMMdq =7491 ,
  XED_IFORM_VPSHAD_XMMdq_MEMdq_XMMdq =7492 ,
  XED_IFORM_VPSHAD_XMMdq_XMMdq_MEMdq =7493 ,
  XED_IFORM_VPSHAD_XMMdq_XMMdq_XMMdq =7494 ,
  XED_IFORM_VPSHAQ_XMMdq_MEMdq_XMMdq =7495 ,
  XED_IFORM_VPSHAQ_XMMdq_XMMdq_MEMdq =7496 ,
  XED_IFORM_VPSHAQ_XMMdq_XMMdq_XMMdq =7497 ,
  XED_IFORM_VPSHAW_XMMdq_MEMdq_XMMdq =7498 ,
  XED_IFORM_VPSHAW_XMMdq_XMMdq_MEMdq =7499 ,
  XED_IFORM_VPSHAW_XMMdq_XMMdq_XMMdq =7500 ,
  XED_IFORM_VPSHLB_XMMdq_MEMdq_XMMdq =7501 ,
  XED_IFORM_VPSHLB_XMMdq_XMMdq_MEMdq =7502 ,
  XED_IFORM_VPSHLB_XMMdq_XMMdq_XMMdq =7503 ,
  XED_IFORM_VPSHLD_XMMdq_MEMdq_XMMdq =7504 ,
  XED_IFORM_VPSHLD_XMMdq_XMMdq_MEMdq =7505 ,
  XED_IFORM_VPSHLD_XMMdq_XMMdq_XMMdq =7506 ,
  XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 =7507 ,
  XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 =7508 ,
  XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 =7509 ,
  XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 =7510 ,
  XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 =7511 ,
  XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 =7512 ,
  XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 =7513 ,
  XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 =7514 ,
  XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 =7515 ,
  XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 =7516 ,
  XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 =7517 ,
  XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 =7518 ,
  XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7519 ,
  XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7520 ,
  XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7521 ,
  XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7522 ,
  XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7523 ,
  XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7524 ,
  XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7525 ,
  XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7526 ,
  XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7527 ,
  XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7528 ,
  XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7529 ,
  XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7530 ,
  XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7531 ,
  XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7532 ,
  XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7533 ,
  XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =7534 ,
  XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7535 ,
  XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =7536 ,
  XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 =7537 ,
  XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 =7538 ,
  XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 =7539 ,
  XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 =7540 ,
  XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 =7541 ,
  XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 =7542 ,
  XED_IFORM_VPSHLQ_XMMdq_MEMdq_XMMdq =7543 ,
  XED_IFORM_VPSHLQ_XMMdq_XMMdq_MEMdq =7544 ,
  XED_IFORM_VPSHLQ_XMMdq_XMMdq_XMMdq =7545 ,
  XED_IFORM_VPSHLW_XMMdq_MEMdq_XMMdq =7546 ,
  XED_IFORM_VPSHLW_XMMdq_XMMdq_MEMdq =7547 ,
  XED_IFORM_VPSHLW_XMMdq_XMMdq_XMMdq =7548 ,
  XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 =7549 ,
  XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 =7550 ,
  XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 =7551 ,
  XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 =7552 ,
  XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 =7553 ,
  XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 =7554 ,
  XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 =7555 ,
  XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 =7556 ,
  XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 =7557 ,
  XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 =7558 ,
  XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 =7559 ,
  XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 =7560 ,
  XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7561 ,
  XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7562 ,
  XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7563 ,
  XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7564 ,
  XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7565 ,
  XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7566 ,
  XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7567 ,
  XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7568 ,
  XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7569 ,
  XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7570 ,
  XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7571 ,
  XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7572 ,
  XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7573 ,
  XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7574 ,
  XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7575 ,
  XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =7576 ,
  XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7577 ,
  XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =7578 ,
  XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 =7579 ,
  XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 =7580 ,
  XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 =7581 ,
  XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 =7582 ,
  XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 =7583 ,
  XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 =7584 ,
  XED_IFORM_VPSHUFB_XMMdq_XMMdq_MEMdq =7585 ,
  XED_IFORM_VPSHUFB_XMMdq_XMMdq_XMMdq =7586 ,
  XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =7587 ,
  XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =7588 ,
  XED_IFORM_VPSHUFB_YMMqq_YMMqq_MEMqq =7589 ,
  XED_IFORM_VPSHUFB_YMMqq_YMMqq_YMMqq =7590 ,
  XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =7591 ,
  XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =7592 ,
  XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =7593 ,
  XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =7594 ,
  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512 =7595 ,
  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512 =7596 ,
  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512 =7597 ,
  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512 =7598 ,
  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512 =7599 ,
  XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512 =7600 ,
  XED_IFORM_VPSHUFD_XMMdq_MEMdq_IMMb =7601 ,
  XED_IFORM_VPSHUFD_XMMdq_XMMdq_IMMb =7602 ,
  XED_IFORM_VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7603 ,
  XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 =7604 ,
  XED_IFORM_VPSHUFD_YMMqq_MEMqq_IMMb =7605 ,
  XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb =7606 ,
  XED_IFORM_VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7607 ,
  XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 =7608 ,
  XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7609 ,
  XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 =7610 ,
  XED_IFORM_VPSHUFHW_XMMdq_MEMdq_IMMb =7611 ,
  XED_IFORM_VPSHUFHW_XMMdq_XMMdq_IMMb =7612 ,
  XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7613 ,
  XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 =7614 ,
  XED_IFORM_VPSHUFHW_YMMqq_MEMqq_IMMb =7615 ,
  XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb =7616 ,
  XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7617 ,
  XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 =7618 ,
  XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7619 ,
  XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 =7620 ,
  XED_IFORM_VPSHUFLW_XMMdq_MEMdq_IMMb =7621 ,
  XED_IFORM_VPSHUFLW_XMMdq_XMMdq_IMMb =7622 ,
  XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7623 ,
  XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 =7624 ,
  XED_IFORM_VPSHUFLW_YMMqq_MEMqq_IMMb =7625 ,
  XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb =7626 ,
  XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7627 ,
  XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 =7628 ,
  XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7629 ,
  XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 =7630 ,
  XED_IFORM_VPSIGNB_XMMdq_XMMdq_MEMdq =7631 ,
  XED_IFORM_VPSIGNB_XMMdq_XMMdq_XMMdq =7632 ,
  XED_IFORM_VPSIGNB_YMMqq_YMMqq_MEMqq =7633 ,
  XED_IFORM_VPSIGNB_YMMqq_YMMqq_YMMqq =7634 ,
  XED_IFORM_VPSIGND_XMMdq_XMMdq_MEMdq =7635 ,
  XED_IFORM_VPSIGND_XMMdq_XMMdq_XMMdq =7636 ,
  XED_IFORM_VPSIGND_YMMqq_YMMqq_MEMqq =7637 ,
  XED_IFORM_VPSIGND_YMMqq_YMMqq_YMMqq =7638 ,
  XED_IFORM_VPSIGNW_XMMdq_XMMdq_MEMdq =7639 ,
  XED_IFORM_VPSIGNW_XMMdq_XMMdq_XMMdq =7640 ,
  XED_IFORM_VPSIGNW_YMMqq_YMMqq_MEMqq =7641 ,
  XED_IFORM_VPSIGNW_YMMqq_YMMqq_YMMqq =7642 ,
  XED_IFORM_VPSLLD_XMMdq_XMMdq_IMMb =7643 ,
  XED_IFORM_VPSLLD_XMMdq_XMMdq_MEMdq =7644 ,
  XED_IFORM_VPSLLD_XMMdq_XMMdq_XMMdq =7645 ,
  XED_IFORM_VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7646 ,
  XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 =7647 ,
  XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7648 ,
  XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7649 ,
  XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb =7650 ,
  XED_IFORM_VPSLLD_YMMqq_YMMqq_MEMdq =7651 ,
  XED_IFORM_VPSLLD_YMMqq_YMMqq_XMMq =7652 ,
  XED_IFORM_VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7653 ,
  XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 =7654 ,
  XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7655 ,
  XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 =7656 ,
  XED_IFORM_VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7657 ,
  XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 =7658 ,
  XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7659 ,
  XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 =7660 ,
  XED_IFORM_VPSLLDQ_XMMdq_XMMdq_IMMb =7661 ,
  XED_IFORM_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512 =7662 ,
  XED_IFORM_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512 =7663 ,
  XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb =7664 ,
  XED_IFORM_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512 =7665 ,
  XED_IFORM_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512 =7666 ,
  XED_IFORM_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512 =7667 ,
  XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512 =7668 ,
  XED_IFORM_VPSLLQ_XMMdq_XMMdq_IMMb =7669 ,
  XED_IFORM_VPSLLQ_XMMdq_XMMdq_MEMdq =7670 ,
  XED_IFORM_VPSLLQ_XMMdq_XMMdq_XMMdq =7671 ,
  XED_IFORM_VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7672 ,
  XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 =7673 ,
  XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7674 ,
  XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7675 ,
  XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb =7676 ,
  XED_IFORM_VPSLLQ_YMMqq_YMMqq_MEMdq =7677 ,
  XED_IFORM_VPSLLQ_YMMqq_YMMqq_XMMq =7678 ,
  XED_IFORM_VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7679 ,
  XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 =7680 ,
  XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7681 ,
  XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 =7682 ,
  XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7683 ,
  XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 =7684 ,
  XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7685 ,
  XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 =7686 ,
  XED_IFORM_VPSLLVD_XMMdq_XMMdq_MEMdq =7687 ,
  XED_IFORM_VPSLLVD_XMMdq_XMMdq_XMMdq =7688 ,
  XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7689 ,
  XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7690 ,
  XED_IFORM_VPSLLVD_YMMqq_YMMqq_MEMqq =7691 ,
  XED_IFORM_VPSLLVD_YMMqq_YMMqq_YMMqq =7692 ,
  XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7693 ,
  XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7694 ,
  XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7695 ,
  XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7696 ,
  XED_IFORM_VPSLLVQ_XMMdq_XMMdq_MEMdq =7697 ,
  XED_IFORM_VPSLLVQ_XMMdq_XMMdq_XMMdq =7698 ,
  XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7699 ,
  XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7700 ,
  XED_IFORM_VPSLLVQ_YMMqq_YMMqq_MEMqq =7701 ,
  XED_IFORM_VPSLLVQ_YMMqq_YMMqq_YMMqq =7702 ,
  XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7703 ,
  XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7704 ,
  XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7705 ,
  XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7706 ,
  XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7707 ,
  XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7708 ,
  XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7709 ,
  XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =7710 ,
  XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7711 ,
  XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =7712 ,
  XED_IFORM_VPSLLW_XMMdq_XMMdq_IMMb =7713 ,
  XED_IFORM_VPSLLW_XMMdq_XMMdq_MEMdq =7714 ,
  XED_IFORM_VPSLLW_XMMdq_XMMdq_XMMdq =7715 ,
  XED_IFORM_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7716 ,
  XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 =7717 ,
  XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7718 ,
  XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7719 ,
  XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb =7720 ,
  XED_IFORM_VPSLLW_YMMqq_YMMqq_MEMdq =7721 ,
  XED_IFORM_VPSLLW_YMMqq_YMMqq_XMMq =7722 ,
  XED_IFORM_VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7723 ,
  XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 =7724 ,
  XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7725 ,
  XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 =7726 ,
  XED_IFORM_VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7727 ,
  XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 =7728 ,
  XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7729 ,
  XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 =7730 ,
  XED_IFORM_VPSRAD_XMMdq_XMMdq_IMMb =7731 ,
  XED_IFORM_VPSRAD_XMMdq_XMMdq_MEMdq =7732 ,
  XED_IFORM_VPSRAD_XMMdq_XMMdq_XMMdq =7733 ,
  XED_IFORM_VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7734 ,
  XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 =7735 ,
  XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7736 ,
  XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7737 ,
  XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb =7738 ,
  XED_IFORM_VPSRAD_YMMqq_YMMqq_MEMdq =7739 ,
  XED_IFORM_VPSRAD_YMMqq_YMMqq_XMMq =7740 ,
  XED_IFORM_VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7741 ,
  XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 =7742 ,
  XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7743 ,
  XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 =7744 ,
  XED_IFORM_VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7745 ,
  XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 =7746 ,
  XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7747 ,
  XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 =7748 ,
  XED_IFORM_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7749 ,
  XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 =7750 ,
  XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7751 ,
  XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7752 ,
  XED_IFORM_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7753 ,
  XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 =7754 ,
  XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7755 ,
  XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 =7756 ,
  XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7757 ,
  XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 =7758 ,
  XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7759 ,
  XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 =7760 ,
  XED_IFORM_VPSRAVD_XMMdq_XMMdq_MEMdq =7761 ,
  XED_IFORM_VPSRAVD_XMMdq_XMMdq_XMMdq =7762 ,
  XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7763 ,
  XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7764 ,
  XED_IFORM_VPSRAVD_YMMqq_YMMqq_MEMqq =7765 ,
  XED_IFORM_VPSRAVD_YMMqq_YMMqq_YMMqq =7766 ,
  XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7767 ,
  XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7768 ,
  XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7769 ,
  XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7770 ,
  XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7771 ,
  XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7772 ,
  XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7773 ,
  XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7774 ,
  XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7775 ,
  XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7776 ,
  XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7777 ,
  XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7778 ,
  XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7779 ,
  XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =7780 ,
  XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7781 ,
  XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =7782 ,
  XED_IFORM_VPSRAW_XMMdq_XMMdq_IMMb =7783 ,
  XED_IFORM_VPSRAW_XMMdq_XMMdq_MEMdq =7784 ,
  XED_IFORM_VPSRAW_XMMdq_XMMdq_XMMdq =7785 ,
  XED_IFORM_VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7786 ,
  XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 =7787 ,
  XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7788 ,
  XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7789 ,
  XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb =7790 ,
  XED_IFORM_VPSRAW_YMMqq_YMMqq_MEMdq =7791 ,
  XED_IFORM_VPSRAW_YMMqq_YMMqq_XMMq =7792 ,
  XED_IFORM_VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7793 ,
  XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 =7794 ,
  XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7795 ,
  XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 =7796 ,
  XED_IFORM_VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7797 ,
  XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 =7798 ,
  XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7799 ,
  XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 =7800 ,
  XED_IFORM_VPSRLD_XMMdq_XMMdq_IMMb =7801 ,
  XED_IFORM_VPSRLD_XMMdq_XMMdq_MEMdq =7802 ,
  XED_IFORM_VPSRLD_XMMdq_XMMdq_XMMdq =7803 ,
  XED_IFORM_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7804 ,
  XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 =7805 ,
  XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7806 ,
  XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7807 ,
  XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb =7808 ,
  XED_IFORM_VPSRLD_YMMqq_YMMqq_MEMdq =7809 ,
  XED_IFORM_VPSRLD_YMMqq_YMMqq_XMMq =7810 ,
  XED_IFORM_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7811 ,
  XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 =7812 ,
  XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7813 ,
  XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 =7814 ,
  XED_IFORM_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 =7815 ,
  XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 =7816 ,
  XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7817 ,
  XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 =7818 ,
  XED_IFORM_VPSRLDQ_XMMdq_XMMdq_IMMb =7819 ,
  XED_IFORM_VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512 =7820 ,
  XED_IFORM_VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512 =7821 ,
  XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb =7822 ,
  XED_IFORM_VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512 =7823 ,
  XED_IFORM_VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512 =7824 ,
  XED_IFORM_VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512 =7825 ,
  XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512 =7826 ,
  XED_IFORM_VPSRLQ_XMMdq_XMMdq_IMMb =7827 ,
  XED_IFORM_VPSRLQ_XMMdq_XMMdq_MEMdq =7828 ,
  XED_IFORM_VPSRLQ_XMMdq_XMMdq_XMMdq =7829 ,
  XED_IFORM_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7830 ,
  XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 =7831 ,
  XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7832 ,
  XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7833 ,
  XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb =7834 ,
  XED_IFORM_VPSRLQ_YMMqq_YMMqq_MEMdq =7835 ,
  XED_IFORM_VPSRLQ_YMMqq_YMMqq_XMMq =7836 ,
  XED_IFORM_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7837 ,
  XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 =7838 ,
  XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7839 ,
  XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 =7840 ,
  XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 =7841 ,
  XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 =7842 ,
  XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7843 ,
  XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 =7844 ,
  XED_IFORM_VPSRLVD_XMMdq_XMMdq_MEMdq =7845 ,
  XED_IFORM_VPSRLVD_XMMdq_XMMdq_XMMdq =7846 ,
  XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7847 ,
  XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7848 ,
  XED_IFORM_VPSRLVD_YMMqq_YMMqq_MEMqq =7849 ,
  XED_IFORM_VPSRLVD_YMMqq_YMMqq_YMMqq =7850 ,
  XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7851 ,
  XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7852 ,
  XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7853 ,
  XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7854 ,
  XED_IFORM_VPSRLVQ_XMMdq_XMMdq_MEMdq =7855 ,
  XED_IFORM_VPSRLVQ_XMMdq_XMMdq_XMMdq =7856 ,
  XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7857 ,
  XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7858 ,
  XED_IFORM_VPSRLVQ_YMMqq_YMMqq_MEMqq =7859 ,
  XED_IFORM_VPSRLVQ_YMMqq_YMMqq_YMMqq =7860 ,
  XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7861 ,
  XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7862 ,
  XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7863 ,
  XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7864 ,
  XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7865 ,
  XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7866 ,
  XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7867 ,
  XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =7868 ,
  XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7869 ,
  XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =7870 ,
  XED_IFORM_VPSRLW_XMMdq_XMMdq_IMMb =7871 ,
  XED_IFORM_VPSRLW_XMMdq_XMMdq_MEMdq =7872 ,
  XED_IFORM_VPSRLW_XMMdq_XMMdq_XMMdq =7873 ,
  XED_IFORM_VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7874 ,
  XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 =7875 ,
  XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7876 ,
  XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7877 ,
  XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb =7878 ,
  XED_IFORM_VPSRLW_YMMqq_YMMqq_MEMdq =7879 ,
  XED_IFORM_VPSRLW_YMMqq_YMMqq_XMMq =7880 ,
  XED_IFORM_VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7881 ,
  XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 =7882 ,
  XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7883 ,
  XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 =7884 ,
  XED_IFORM_VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 =7885 ,
  XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 =7886 ,
  XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7887 ,
  XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 =7888 ,
  XED_IFORM_VPSUBB_XMMdq_XMMdq_MEMdq =7889 ,
  XED_IFORM_VPSUBB_XMMdq_XMMdq_XMMdq =7890 ,
  XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =7891 ,
  XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =7892 ,
  XED_IFORM_VPSUBB_YMMqq_YMMqq_MEMqq =7893 ,
  XED_IFORM_VPSUBB_YMMqq_YMMqq_YMMqq =7894 ,
  XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =7895 ,
  XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =7896 ,
  XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =7897 ,
  XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =7898 ,
  XED_IFORM_VPSUBD_XMMdq_XMMdq_MEMdq =7899 ,
  XED_IFORM_VPSUBD_XMMdq_XMMdq_XMMdq =7900 ,
  XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =7901 ,
  XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =7902 ,
  XED_IFORM_VPSUBD_YMMqq_YMMqq_MEMqq =7903 ,
  XED_IFORM_VPSUBD_YMMqq_YMMqq_YMMqq =7904 ,
  XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =7905 ,
  XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =7906 ,
  XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =7907 ,
  XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =7908 ,
  XED_IFORM_VPSUBQ_XMMdq_XMMdq_MEMdq =7909 ,
  XED_IFORM_VPSUBQ_XMMdq_XMMdq_XMMdq =7910 ,
  XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =7911 ,
  XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =7912 ,
  XED_IFORM_VPSUBQ_YMMqq_YMMqq_MEMqq =7913 ,
  XED_IFORM_VPSUBQ_YMMqq_YMMqq_YMMqq =7914 ,
  XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =7915 ,
  XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =7916 ,
  XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =7917 ,
  XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =7918 ,
  XED_IFORM_VPSUBSB_XMMdq_XMMdq_MEMdq =7919 ,
  XED_IFORM_VPSUBSB_XMMdq_XMMdq_XMMdq =7920 ,
  XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 =7921 ,
  XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 =7922 ,
  XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 =7923 ,
  XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 =7924 ,
  XED_IFORM_VPSUBSB_YMMqq_YMMqq_MEMqq =7925 ,
  XED_IFORM_VPSUBSB_YMMqq_YMMqq_YMMqq =7926 ,
  XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 =7927 ,
  XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 =7928 ,
  XED_IFORM_VPSUBSW_XMMdq_XMMdq_MEMdq =7929 ,
  XED_IFORM_VPSUBSW_XMMdq_XMMdq_XMMdq =7930 ,
  XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 =7931 ,
  XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 =7932 ,
  XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 =7933 ,
  XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 =7934 ,
  XED_IFORM_VPSUBSW_YMMqq_YMMqq_MEMqq =7935 ,
  XED_IFORM_VPSUBSW_YMMqq_YMMqq_YMMqq =7936 ,
  XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 =7937 ,
  XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 =7938 ,
  XED_IFORM_VPSUBUSB_XMMdq_XMMdq_MEMdq =7939 ,
  XED_IFORM_VPSUBUSB_XMMdq_XMMdq_XMMdq =7940 ,
  XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =7941 ,
  XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =7942 ,
  XED_IFORM_VPSUBUSB_YMMqq_YMMqq_MEMqq =7943 ,
  XED_IFORM_VPSUBUSB_YMMqq_YMMqq_YMMqq =7944 ,
  XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =7945 ,
  XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =7946 ,
  XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =7947 ,
  XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =7948 ,
  XED_IFORM_VPSUBUSW_XMMdq_XMMdq_MEMdq =7949 ,
  XED_IFORM_VPSUBUSW_XMMdq_XMMdq_XMMdq =7950 ,
  XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7951 ,
  XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7952 ,
  XED_IFORM_VPSUBUSW_YMMqq_YMMqq_MEMqq =7953 ,
  XED_IFORM_VPSUBUSW_YMMqq_YMMqq_YMMqq =7954 ,
  XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7955 ,
  XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =7956 ,
  XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7957 ,
  XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =7958 ,
  XED_IFORM_VPSUBW_XMMdq_XMMdq_MEMdq =7959 ,
  XED_IFORM_VPSUBW_XMMdq_XMMdq_XMMdq =7960 ,
  XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =7961 ,
  XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =7962 ,
  XED_IFORM_VPSUBW_YMMqq_YMMqq_MEMqq =7963 ,
  XED_IFORM_VPSUBW_YMMqq_YMMqq_YMMqq =7964 ,
  XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =7965 ,
  XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =7966 ,
  XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =7967 ,
  XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =7968 ,
  XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 =7969 ,
  XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 =7970 ,
  XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 =7971 ,
  XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 =7972 ,
  XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 =7973 ,
  XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 =7974 ,
  XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 =7975 ,
  XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 =7976 ,
  XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 =7977 ,
  XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 =7978 ,
  XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 =7979 ,
  XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 =7980 ,
  XED_IFORM_VPTEST_XMMdq_MEMdq =7981 ,
  XED_IFORM_VPTEST_XMMdq_XMMdq =7982 ,
  XED_IFORM_VPTEST_YMMqq_MEMqq =7983 ,
  XED_IFORM_VPTEST_YMMqq_YMMqq =7984 ,
  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 =7985 ,
  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 =7986 ,
  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 =7987 ,
  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 =7988 ,
  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 =7989 ,
  XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 =7990 ,
  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 =7991 ,
  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 =7992 ,
  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 =7993 ,
  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 =7994 ,
  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 =7995 ,
  XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 =7996 ,
  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 =7997 ,
  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 =7998 ,
  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 =7999 ,
  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 =8000 ,
  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 =8001 ,
  XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 =8002 ,
  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 =8003 ,
  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 =8004 ,
  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 =8005 ,
  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 =8006 ,
  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 =8007 ,
  XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 =8008 ,
  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 =8009 ,
  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 =8010 ,
  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 =8011 ,
  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 =8012 ,
  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 =8013 ,
  XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 =8014 ,
  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 =8015 ,
  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 =8016 ,
  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 =8017 ,
  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 =8018 ,
  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 =8019 ,
  XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 =8020 ,
  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 =8021 ,
  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 =8022 ,
  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 =8023 ,
  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 =8024 ,
  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 =8025 ,
  XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 =8026 ,
  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 =8027 ,
  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 =8028 ,
  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 =8029 ,
  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 =8030 ,
  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 =8031 ,
  XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 =8032 ,
  XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_MEMdq =8033 ,
  XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_XMMdq =8034 ,
  XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =8035 ,
  XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =8036 ,
  XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_MEMqq =8037 ,
  XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_YMMqq =8038 ,
  XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =8039 ,
  XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =8040 ,
  XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =8041 ,
  XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =8042 ,
  XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_MEMdq =8043 ,
  XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_XMMdq =8044 ,
  XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =8045 ,
  XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =8046 ,
  XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_MEMqq =8047 ,
  XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_YMMqq =8048 ,
  XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =8049 ,
  XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =8050 ,
  XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =8051 ,
  XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =8052 ,
  XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq =8053 ,
  XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq =8054 ,
  XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =8055 ,
  XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =8056 ,
  XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq =8057 ,
  XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq =8058 ,
  XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =8059 ,
  XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =8060 ,
  XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =8061 ,
  XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =8062 ,
  XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_MEMdq =8063 ,
  XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_XMMdq =8064 ,
  XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =8065 ,
  XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =8066 ,
  XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_MEMqq =8067 ,
  XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_YMMqq =8068 ,
  XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =8069 ,
  XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =8070 ,
  XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =8071 ,
  XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =8072 ,
  XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_MEMdq =8073 ,
  XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_XMMdq =8074 ,
  XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 =8075 ,
  XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 =8076 ,
  XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_MEMqq =8077 ,
  XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_YMMqq =8078 ,
  XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 =8079 ,
  XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 =8080 ,
  XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 =8081 ,
  XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 =8082 ,
  XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_MEMdq =8083 ,
  XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_XMMdq =8084 ,
  XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =8085 ,
  XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =8086 ,
  XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_MEMqq =8087 ,
  XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_YMMqq =8088 ,
  XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =8089 ,
  XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =8090 ,
  XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =8091 ,
  XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =8092 ,
  XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq =8093 ,
  XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq =8094 ,
  XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =8095 ,
  XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =8096 ,
  XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq =8097 ,
  XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq =8098 ,
  XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =8099 ,
  XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =8100 ,
  XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =8101 ,
  XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =8102 ,
  XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_MEMdq =8103 ,
  XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_XMMdq =8104 ,
  XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 =8105 ,
  XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 =8106 ,
  XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_MEMqq =8107 ,
  XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_YMMqq =8108 ,
  XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 =8109 ,
  XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 =8110 ,
  XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 =8111 ,
  XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 =8112 ,
  XED_IFORM_VPXOR_XMMdq_XMMdq_MEMdq =8113 ,
  XED_IFORM_VPXOR_XMMdq_XMMdq_XMMdq =8114 ,
  XED_IFORM_VPXOR_YMMqq_YMMqq_MEMqq =8115 ,
  XED_IFORM_VPXOR_YMMqq_YMMqq_YMMqq =8116 ,
  XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =8117 ,
  XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =8118 ,
  XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =8119 ,
  XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =8120 ,
  XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =8121 ,
  XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =8122 ,
  XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =8123 ,
  XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =8124 ,
  XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =8125 ,
  XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =8126 ,
  XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =8127 ,
  XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =8128 ,
  XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =8129 ,
  XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =8130 ,
  XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 =8131 ,
  XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 =8132 ,
  XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 =8133 ,
  XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 =8134 ,
  XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =8135 ,
  XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =8136 ,
  XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 =8137 ,
  XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 =8138 ,
  XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 =8139 ,
  XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 =8140 ,
  XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =8141 ,
  XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =8142 ,
  XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =8143 ,
  XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =8144 ,
  XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512 =8145 ,
  XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512 =8146 ,
  XED_IFORM_VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512 =8147 ,
  XED_IFORM_VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512 =8148 ,
  XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512 =8149 ,
  XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 =8150 ,
  XED_IFORM_VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512 =8151 ,
  XED_IFORM_VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512 =8152 ,
  XED_IFORM_VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512 =8153 ,
  XED_IFORM_VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512 =8154 ,
  XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512 =8155 ,
  XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 =8156 ,
  XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =8157 ,
  XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =8158 ,
  XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =8159 ,
  XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =8160 ,
  XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER =8161 ,
  XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER =8162 ,
  XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER =8163 ,
  XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER =8164 ,
  XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER =8165 ,
  XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER =8166 ,
  XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER =8167 ,
  XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER =8168 ,
  XED_IFORM_VRCPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512 =8169 ,
  XED_IFORM_VRCPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512 =8170 ,
  XED_IFORM_VRCPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512 =8171 ,
  XED_IFORM_VRCPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512 =8172 ,
  XED_IFORM_VRCPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512 =8173 ,
  XED_IFORM_VRCPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512 =8174 ,
  XED_IFORM_VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512 =8175 ,
  XED_IFORM_VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512 =8176 ,
  XED_IFORM_VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512 =8177 ,
  XED_IFORM_VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512 =8178 ,
  XED_IFORM_VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512 =8179 ,
  XED_IFORM_VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512 =8180 ,
  XED_IFORM_VRCPPS_XMMdq_MEMdq =8181 ,
  XED_IFORM_VRCPPS_XMMdq_XMMdq =8182 ,
  XED_IFORM_VRCPPS_YMMqq_MEMqq =8183 ,
  XED_IFORM_VRCPPS_YMMqq_YMMqq =8184 ,
  XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =8185 ,
  XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =8186 ,
  XED_IFORM_VRCPSS_XMMdq_XMMdq_MEMd =8187 ,
  XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd =8188 ,
  XED_IFORM_VREDUCEBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512 =8189 ,
  XED_IFORM_VREDUCEBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512 =8190 ,
  XED_IFORM_VREDUCEBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512 =8191 ,
  XED_IFORM_VREDUCEBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512 =8192 ,
  XED_IFORM_VREDUCEBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512 =8193 ,
  XED_IFORM_VREDUCEBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512 =8194 ,
  XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 =8195 ,
  XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 =8196 ,
  XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 =8197 ,
  XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 =8198 ,
  XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 =8199 ,
  XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 =8200 ,
  XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 =8201 ,
  XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 =8202 ,
  XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 =8203 ,
  XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 =8204 ,
  XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 =8205 ,
  XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 =8206 ,
  XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 =8207 ,
  XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 =8208 ,
  XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 =8209 ,
  XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 =8210 ,
  XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 =8211 ,
  XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 =8212 ,
  XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =8213 ,
  XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =8214 ,
  XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 =8215 ,
  XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 =8216 ,
  XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =8217 ,
  XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =8218 ,
  XED_IFORM_VRNDSCALEBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512 =8219 ,
  XED_IFORM_VRNDSCALEBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512 =8220 ,
  XED_IFORM_VRNDSCALEBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512 =8221 ,
  XED_IFORM_VRNDSCALEBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512 =8222 ,
  XED_IFORM_VRNDSCALEBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512 =8223 ,
  XED_IFORM_VRNDSCALEBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512 =8224 ,
  XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 =8225 ,
  XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 =8226 ,
  XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 =8227 ,
  XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 =8228 ,
  XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 =8229 ,
  XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 =8230 ,
  XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 =8231 ,
  XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 =8232 ,
  XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 =8233 ,
  XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 =8234 ,
  XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 =8235 ,
  XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 =8236 ,
  XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 =8237 ,
  XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 =8238 ,
  XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 =8239 ,
  XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 =8240 ,
  XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 =8241 ,
  XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 =8242 ,
  XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =8243 ,
  XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =8244 ,
  XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 =8245 ,
  XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 =8246 ,
  XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =8247 ,
  XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =8248 ,
  XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb =8249 ,
  XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb =8250 ,
  XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb =8251 ,
  XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb =8252 ,
  XED_IFORM_VROUNDPS_XMMdq_MEMdq_IMMb =8253 ,
  XED_IFORM_VROUNDPS_XMMdq_XMMdq_IMMb =8254 ,
  XED_IFORM_VROUNDPS_YMMqq_MEMqq_IMMb =8255 ,
  XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb =8256 ,
  XED_IFORM_VROUNDSD_XMMdq_XMMdq_MEMq_IMMb =8257 ,
  XED_IFORM_VROUNDSD_XMMdq_XMMdq_XMMq_IMMb =8258 ,
  XED_IFORM_VROUNDSS_XMMdq_XMMdq_MEMd_IMMb =8259 ,
  XED_IFORM_VROUNDSS_XMMdq_XMMdq_XMMd_IMMb =8260 ,
  XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512 =8261 ,
  XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512 =8262 ,
  XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512 =8263 ,
  XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512 =8264 ,
  XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512 =8265 ,
  XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 =8266 ,
  XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512 =8267 ,
  XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512 =8268 ,
  XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512 =8269 ,
  XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512 =8270 ,
  XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512 =8271 ,
  XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 =8272 ,
  XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =8273 ,
  XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =8274 ,
  XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =8275 ,
  XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =8276 ,
  XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER =8277 ,
  XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER =8278 ,
  XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER =8279 ,
  XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER =8280 ,
  XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER =8281 ,
  XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER =8282 ,
  XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER =8283 ,
  XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER =8284 ,
  XED_IFORM_VRSQRTBF16_XMMbf16_MASKmskw_MEMbf16_AVX512 =8285 ,
  XED_IFORM_VRSQRTBF16_XMMbf16_MASKmskw_XMMbf16_AVX512 =8286 ,
  XED_IFORM_VRSQRTBF16_YMMbf16_MASKmskw_MEMbf16_AVX512 =8287 ,
  XED_IFORM_VRSQRTBF16_YMMbf16_MASKmskw_YMMbf16_AVX512 =8288 ,
  XED_IFORM_VRSQRTBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512 =8289 ,
  XED_IFORM_VRSQRTBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512 =8290 ,
  XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512 =8291 ,
  XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512 =8292 ,
  XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512 =8293 ,
  XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512 =8294 ,
  XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512 =8295 ,
  XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512 =8296 ,
  XED_IFORM_VRSQRTPS_XMMdq_MEMdq =8297 ,
  XED_IFORM_VRSQRTPS_XMMdq_XMMdq =8298 ,
  XED_IFORM_VRSQRTPS_YMMqq_MEMqq =8299 ,
  XED_IFORM_VRSQRTPS_YMMqq_YMMqq =8300 ,
  XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =8301 ,
  XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =8302 ,
  XED_IFORM_VRSQRTSS_XMMdq_XMMdq_MEMd =8303 ,
  XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd =8304 ,
  XED_IFORM_VSCALEFBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =8305 ,
  XED_IFORM_VSCALEFBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =8306 ,
  XED_IFORM_VSCALEFBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =8307 ,
  XED_IFORM_VSCALEFBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =8308 ,
  XED_IFORM_VSCALEFBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =8309 ,
  XED_IFORM_VSCALEFBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =8310 ,
  XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =8311 ,
  XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =8312 ,
  XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =8313 ,
  XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =8314 ,
  XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =8315 ,
  XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =8316 ,
  XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =8317 ,
  XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =8318 ,
  XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =8319 ,
  XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =8320 ,
  XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =8321 ,
  XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =8322 ,
  XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =8323 ,
  XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =8324 ,
  XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =8325 ,
  XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =8326 ,
  XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =8327 ,
  XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =8328 ,
  XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =8329 ,
  XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =8330 ,
  XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =8331 ,
  XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =8332 ,
  XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =8333 ,
  XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =8334 ,
  XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 =8335 ,
  XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 =8336 ,
  XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 =8337 ,
  XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 =8338 ,
  XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256 =8339 ,
  XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512 =8340 ,
  XED_IFORM_VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 =8341 ,
  XED_IFORM_VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 =8342 ,
  XED_IFORM_VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 =8343 ,
  XED_IFORM_VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 =8344 ,
  XED_IFORM_VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 =8345 ,
  XED_IFORM_VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 =8346 ,
  XED_IFORM_VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 =8347 ,
  XED_IFORM_VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 =8348 ,
  XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 =8349 ,
  XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 =8350 ,
  XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 =8351 ,
  XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 =8352 ,
  XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256 =8353 ,
  XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512 =8354 ,
  XED_IFORM_VSHA512MSG1_YMMu64_XMMu64 =8355 ,
  XED_IFORM_VSHA512MSG2_YMMu64_YMMu64 =8356 ,
  XED_IFORM_VSHA512RNDS2_YMMu64_YMMu64_XMMu64 =8357 ,
  XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 =8358 ,
  XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 =8359 ,
  XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 =8360 ,
  XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 =8361 ,
  XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 =8362 ,
  XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 =8363 ,
  XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 =8364 ,
  XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 =8365 ,
  XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 =8366 ,
  XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 =8367 ,
  XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 =8368 ,
  XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 =8369 ,
  XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 =8370 ,
  XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 =8371 ,
  XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 =8372 ,
  XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 =8373 ,
  XED_IFORM_VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb =8374 ,
  XED_IFORM_VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb =8375 ,
  XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 =8376 ,
  XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 =8377 ,
  XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 =8378 ,
  XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 =8379 ,
  XED_IFORM_VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb =8380 ,
  XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb =8381 ,
  XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 =8382 ,
  XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 =8383 ,
  XED_IFORM_VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb =8384 ,
  XED_IFORM_VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb =8385 ,
  XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 =8386 ,
  XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 =8387 ,
  XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 =8388 ,
  XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 =8389 ,
  XED_IFORM_VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb =8390 ,
  XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb =8391 ,
  XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 =8392 ,
  XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 =8393 ,
  XED_IFORM_VSM3MSG1_XMMu32_XMMu32_MEMu32 =8394 ,
  XED_IFORM_VSM3MSG1_XMMu32_XMMu32_XMMu32 =8395 ,
  XED_IFORM_VSM3MSG2_XMMu32_XMMu32_MEMu32 =8396 ,
  XED_IFORM_VSM3MSG2_XMMu32_XMMu32_XMMu32 =8397 ,
  XED_IFORM_VSM3RNDS2_XMMu32_XMMu32_MEMu32_IMM8 =8398 ,
  XED_IFORM_VSM3RNDS2_XMMu32_XMMu32_XMMu32_IMM8 =8399 ,
  XED_IFORM_VSM4KEY4_XMMu32_XMMu32_MEMu32 =8400 ,
  XED_IFORM_VSM4KEY4_XMMu32_XMMu32_MEMu32_AVX512 =8401 ,
  XED_IFORM_VSM4KEY4_XMMu32_XMMu32_XMMu32 =8402 ,
  XED_IFORM_VSM4KEY4_XMMu32_XMMu32_XMMu32_AVX512 =8403 ,
  XED_IFORM_VSM4KEY4_YMMu32_YMMu32_MEMu32 =8404 ,
  XED_IFORM_VSM4KEY4_YMMu32_YMMu32_MEMu32_AVX512 =8405 ,
  XED_IFORM_VSM4KEY4_YMMu32_YMMu32_YMMu32 =8406 ,
  XED_IFORM_VSM4KEY4_YMMu32_YMMu32_YMMu32_AVX512 =8407 ,
  XED_IFORM_VSM4KEY4_ZMMu32_ZMMu32_MEMu32_AVX512 =8408 ,
  XED_IFORM_VSM4KEY4_ZMMu32_ZMMu32_ZMMu32_AVX512 =8409 ,
  XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_MEMu32 =8410 ,
  XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_MEMu32_AVX512 =8411 ,
  XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_XMMu32 =8412 ,
  XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_XMMu32_AVX512 =8413 ,
  XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_MEMu32 =8414 ,
  XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_MEMu32_AVX512 =8415 ,
  XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_YMMu32 =8416 ,
  XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_YMMu32_AVX512 =8417 ,
  XED_IFORM_VSM4RNDS4_ZMMu32_ZMMu32_MEMu32_AVX512 =8418 ,
  XED_IFORM_VSM4RNDS4_ZMMu32_ZMMu32_ZMMu32_AVX512 =8419 ,
  XED_IFORM_VSQRTBF16_XMMbf16_MASKmskw_MEMbf16_AVX512 =8420 ,
  XED_IFORM_VSQRTBF16_XMMbf16_MASKmskw_XMMbf16_AVX512 =8421 ,
  XED_IFORM_VSQRTBF16_YMMbf16_MASKmskw_MEMbf16_AVX512 =8422 ,
  XED_IFORM_VSQRTBF16_YMMbf16_MASKmskw_YMMbf16_AVX512 =8423 ,
  XED_IFORM_VSQRTBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512 =8424 ,
  XED_IFORM_VSQRTBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512 =8425 ,
  XED_IFORM_VSQRTPD_XMMdq_MEMdq =8426 ,
  XED_IFORM_VSQRTPD_XMMdq_XMMdq =8427 ,
  XED_IFORM_VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512 =8428 ,
  XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512 =8429 ,
  XED_IFORM_VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512 =8430 ,
  XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512 =8431 ,
  XED_IFORM_VSQRTPD_YMMqq_MEMqq =8432 ,
  XED_IFORM_VSQRTPD_YMMqq_YMMqq =8433 ,
  XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512 =8434 ,
  XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512 =8435 ,
  XED_IFORM_VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512 =8436 ,
  XED_IFORM_VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512 =8437 ,
  XED_IFORM_VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512 =8438 ,
  XED_IFORM_VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512 =8439 ,
  XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512 =8440 ,
  XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512 =8441 ,
  XED_IFORM_VSQRTPS_XMMdq_MEMdq =8442 ,
  XED_IFORM_VSQRTPS_XMMdq_XMMdq =8443 ,
  XED_IFORM_VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512 =8444 ,
  XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512 =8445 ,
  XED_IFORM_VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512 =8446 ,
  XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512 =8447 ,
  XED_IFORM_VSQRTPS_YMMqq_MEMqq =8448 ,
  XED_IFORM_VSQRTPS_YMMqq_YMMqq =8449 ,
  XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512 =8450 ,
  XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512 =8451 ,
  XED_IFORM_VSQRTSD_XMMdq_XMMdq_MEMq =8452 ,
  XED_IFORM_VSQRTSD_XMMdq_XMMdq_XMMq =8453 ,
  XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =8454 ,
  XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =8455 ,
  XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =8456 ,
  XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =8457 ,
  XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd =8458 ,
  XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd =8459 ,
  XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =8460 ,
  XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =8461 ,
  XED_IFORM_VSTMXCSR_MEMd =8462 ,
  XED_IFORM_VSUBBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 =8463 ,
  XED_IFORM_VSUBBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 =8464 ,
  XED_IFORM_VSUBBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 =8465 ,
  XED_IFORM_VSUBBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 =8466 ,
  XED_IFORM_VSUBBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 =8467 ,
  XED_IFORM_VSUBBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 =8468 ,
  XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq =8469 ,
  XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq =8470 ,
  XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =8471 ,
  XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =8472 ,
  XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =8473 ,
  XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =8474 ,
  XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq =8475 ,
  XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq =8476 ,
  XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =8477 ,
  XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =8478 ,
  XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =8479 ,
  XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =8480 ,
  XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 =8481 ,
  XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 =8482 ,
  XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 =8483 ,
  XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 =8484 ,
  XED_IFORM_VSUBPS_XMMdq_XMMdq_MEMdq =8485 ,
  XED_IFORM_VSUBPS_XMMdq_XMMdq_XMMdq =8486 ,
  XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =8487 ,
  XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =8488 ,
  XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =8489 ,
  XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =8490 ,
  XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq =8491 ,
  XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq =8492 ,
  XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =8493 ,
  XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =8494 ,
  XED_IFORM_VSUBSD_XMMdq_XMMdq_MEMq =8495 ,
  XED_IFORM_VSUBSD_XMMdq_XMMdq_XMMq =8496 ,
  XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =8497 ,
  XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =8498 ,
  XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 =8499 ,
  XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 =8500 ,
  XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd =8501 ,
  XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd =8502 ,
  XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =8503 ,
  XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =8504 ,
  XED_IFORM_VTESTPD_XMMdq_MEMdq =8505 ,
  XED_IFORM_VTESTPD_XMMdq_XMMdq =8506 ,
  XED_IFORM_VTESTPD_YMMqq_MEMqq =8507 ,
  XED_IFORM_VTESTPD_YMMqq_YMMqq =8508 ,
  XED_IFORM_VTESTPS_XMMdq_MEMdq =8509 ,
  XED_IFORM_VTESTPS_XMMdq_XMMdq =8510 ,
  XED_IFORM_VTESTPS_YMMqq_MEMqq =8511 ,
  XED_IFORM_VTESTPS_YMMqq_YMMqq =8512 ,
  XED_IFORM_VUCOMISD_XMMdq_MEMq =8513 ,
  XED_IFORM_VUCOMISD_XMMdq_XMMq =8514 ,
  XED_IFORM_VUCOMISD_XMMf64_MEMf64_AVX512 =8515 ,
  XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512 =8516 ,
  XED_IFORM_VUCOMISH_XMMf16_MEMf16_AVX512 =8517 ,
  XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512 =8518 ,
  XED_IFORM_VUCOMISS_XMMdq_MEMd =8519 ,
  XED_IFORM_VUCOMISS_XMMdq_XMMd =8520 ,
  XED_IFORM_VUCOMISS_XMMf32_MEMf32_AVX512 =8521 ,
  XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512 =8522 ,
  XED_IFORM_VUCOMXSD_XMMf64_MEMf64_AVX512 =8523 ,
  XED_IFORM_VUCOMXSD_XMMf64_XMMf64_AVX512 =8524 ,
  XED_IFORM_VUCOMXSH_XMMf16_MEMf16_AVX512 =8525 ,
  XED_IFORM_VUCOMXSH_XMMf16_XMMf16_AVX512 =8526 ,
  XED_IFORM_VUCOMXSS_XMMf32_MEMf32_AVX512 =8527 ,
  XED_IFORM_VUCOMXSS_XMMf32_XMMf32_AVX512 =8528 ,
  XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq =8529 ,
  XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq =8530 ,
  XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =8531 ,
  XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =8532 ,
  XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =8533 ,
  XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =8534 ,
  XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_MEMqq =8535 ,
  XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_YMMqq =8536 ,
  XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =8537 ,
  XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =8538 ,
  XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_MEMdq =8539 ,
  XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_XMMdq =8540 ,
  XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =8541 ,
  XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =8542 ,
  XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =8543 ,
  XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =8544 ,
  XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_MEMqq =8545 ,
  XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_YMMqq =8546 ,
  XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =8547 ,
  XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =8548 ,
  XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_MEMdq =8549 ,
  XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_XMMdq =8550 ,
  XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 =8551 ,
  XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 =8552 ,
  XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 =8553 ,
  XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 =8554 ,
  XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_MEMqq =8555 ,
  XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_YMMqq =8556 ,
  XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 =8557 ,
  XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 =8558 ,
  XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_MEMdq =8559 ,
  XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_XMMdq =8560 ,
  XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 =8561 ,
  XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 =8562 ,
  XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 =8563 ,
  XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 =8564 ,
  XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_MEMqq =8565 ,
  XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_YMMqq =8566 ,
  XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 =8567 ,
  XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 =8568 ,
  XED_IFORM_VXORPD_XMMdq_XMMdq_MEMdq =8569 ,
  XED_IFORM_VXORPD_XMMdq_XMMdq_XMMdq =8570 ,
  XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 =8571 ,
  XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 =8572 ,
  XED_IFORM_VXORPD_YMMqq_YMMqq_MEMqq =8573 ,
  XED_IFORM_VXORPD_YMMqq_YMMqq_YMMqq =8574 ,
  XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 =8575 ,
  XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 =8576 ,
  XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 =8577 ,
  XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 =8578 ,
  XED_IFORM_VXORPS_XMMdq_XMMdq_MEMdq =8579 ,
  XED_IFORM_VXORPS_XMMdq_XMMdq_XMMdq =8580 ,
  XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 =8581 ,
  XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 =8582 ,
  XED_IFORM_VXORPS_YMMqq_YMMqq_MEMqq =8583 ,
  XED_IFORM_VXORPS_YMMqq_YMMqq_YMMqq =8584 ,
  XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 =8585 ,
  XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 =8586 ,
  XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 =8587 ,
  XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 =8588 ,
  XED_IFORM_VZEROALL =8589 ,
  XED_IFORM_VZEROUPPER =8590 ,
  XED_IFORM_WBINVD =8591 ,
  XED_IFORM_WBNOINVD =8592 ,
  XED_IFORM_WRFSBASE_GPRy =8593 ,
  XED_IFORM_WRGSBASE_GPRy =8594 ,
  XED_IFORM_WRMSR =8595 ,
  XED_IFORM_WRMSRLIST =8596 ,
  XED_IFORM_WRMSRNS =8597 ,
  XED_IFORM_WRMSRNS_IMM32_GPR64u64 =8598 ,
  XED_IFORM_WRMSRNS_IMM32_GPR64u64_APX =8599 ,
  XED_IFORM_WRPKRU =8600 ,
  XED_IFORM_WRSSD_MEMu32_GPR32u32 =8601 ,
  XED_IFORM_WRSSD_MEMu32_GPR32u32_APX =8602 ,
  XED_IFORM_WRSSQ_MEMu64_GPR64u64 =8603 ,
  XED_IFORM_WRSSQ_MEMu64_GPR64u64_APX =8604 ,
  XED_IFORM_WRUSSD_MEMu32_GPR32u32 =8605 ,
  XED_IFORM_WRUSSD_MEMu32_GPR32u32_APX =8606 ,
  XED_IFORM_WRUSSQ_MEMu64_GPR64u64 =8607 ,
  XED_IFORM_WRUSSQ_MEMu64_GPR64u64_APX =8608 ,
  XED_IFORM_XABORT_IMMb =8609 ,
  XED_IFORM_XADD_GPR8_GPR8 =8610 ,
  XED_IFORM_XADD_GPRv_GPRv =8611 ,
  XED_IFORM_XADD_MEMb_GPR8 =8612 ,
  XED_IFORM_XADD_MEMv_GPRv =8613 ,
  XED_IFORM_XADD_LOCK_MEMb_GPR8 =8614 ,
  XED_IFORM_XADD_LOCK_MEMv_GPRv =8615 ,
  XED_IFORM_XBEGIN_RELBRz =8616 ,
  XED_IFORM_XCHG_GPR8_GPR8 =8617 ,
  XED_IFORM_XCHG_GPRv_GPRv =8618 ,
  XED_IFORM_XCHG_GPRv_OrAX =8619 ,
  XED_IFORM_XCHG_MEMb_GPR8 =8620 ,
  XED_IFORM_XCHG_MEMv_GPRv =8621 ,
  XED_IFORM_XEND =8622 ,
  XED_IFORM_XGETBV =8623 ,
  XED_IFORM_XLAT =8624 ,
  XED_IFORM_XOR_AL_IMMb =8625 ,
  XED_IFORM_XOR_GPR8_GPR8_30 =8626 ,
  XED_IFORM_XOR_GPR8_GPR8_32 =8627 ,
  XED_IFORM_XOR_GPR8_IMMb_80r6 =8628 ,
  XED_IFORM_XOR_GPR8_IMMb_82r6 =8629 ,
  XED_IFORM_XOR_GPR8_MEMb =8630 ,
  XED_IFORM_XOR_GPR8i8_GPR8i8_APX =8631 ,
  XED_IFORM_XOR_GPR8i8_GPR8i8_GPR8i8_APX =8632 ,
  XED_IFORM_XOR_GPR8i8_GPR8i8_IMM8_APX =8633 ,
  XED_IFORM_XOR_GPR8i8_GPR8i8_MEMi8_APX =8634 ,
  XED_IFORM_XOR_GPR8i8_IMM8_APX =8635 ,
  XED_IFORM_XOR_GPR8i8_MEMi8_APX =8636 ,
  XED_IFORM_XOR_GPR8i8_MEMi8_GPR8i8_APX =8637 ,
  XED_IFORM_XOR_GPR8i8_MEMi8_IMM8_APX =8638 ,
  XED_IFORM_XOR_GPRv_GPRv_31 =8639 ,
  XED_IFORM_XOR_GPRv_GPRv_33 =8640 ,
  XED_IFORM_XOR_GPRv_GPRv_APX =8641 ,
  XED_IFORM_XOR_GPRv_GPRv_GPRv_APX =8642 ,
  XED_IFORM_XOR_GPRv_GPRv_IMM8_APX =8643 ,
  XED_IFORM_XOR_GPRv_GPRv_IMMz_APX =8644 ,
  XED_IFORM_XOR_GPRv_GPRv_MEMv_APX =8645 ,
  XED_IFORM_XOR_GPRv_IMM8_APX =8646 ,
  XED_IFORM_XOR_GPRv_IMMb =8647 ,
  XED_IFORM_XOR_GPRv_IMMz =8648 ,
  XED_IFORM_XOR_GPRv_IMMz_APX =8649 ,
  XED_IFORM_XOR_GPRv_MEMv =8650 ,
  XED_IFORM_XOR_GPRv_MEMv_APX =8651 ,
  XED_IFORM_XOR_GPRv_MEMv_GPRv_APX =8652 ,
  XED_IFORM_XOR_GPRv_MEMv_IMM8_APX =8653 ,
  XED_IFORM_XOR_GPRv_MEMv_IMMz_APX =8654 ,
  XED_IFORM_XOR_MEMb_GPR8 =8655 ,
  XED_IFORM_XOR_MEMb_IMMb_80r6 =8656 ,
  XED_IFORM_XOR_MEMb_IMMb_82r6 =8657 ,
  XED_IFORM_XOR_MEMi8_GPR8i8_APX =8658 ,
  XED_IFORM_XOR_MEMi8_IMM8_APX =8659 ,
  XED_IFORM_XOR_MEMv_GPRv =8660 ,
  XED_IFORM_XOR_MEMv_GPRv_APX =8661 ,
  XED_IFORM_XOR_MEMv_IMM8_APX =8662 ,
  XED_IFORM_XOR_MEMv_IMMb =8663 ,
  XED_IFORM_XOR_MEMv_IMMz =8664 ,
  XED_IFORM_XOR_MEMv_IMMz_APX =8665 ,
  XED_IFORM_XOR_OrAX_IMMz =8666 ,
  XED_IFORM_XORPD_XMMxuq_MEMxuq =8667 ,
  XED_IFORM_XORPD_XMMxuq_XMMxuq =8668 ,
  XED_IFORM_XORPS_XMMxud_MEMxud =8669 ,
  XED_IFORM_XORPS_XMMxud_XMMxud =8670 ,
  XED_IFORM_XOR_LOCK_MEMb_GPR8 =8671 ,
  XED_IFORM_XOR_LOCK_MEMb_IMMb_80r6 =8672 ,
  XED_IFORM_XOR_LOCK_MEMb_IMMb_82r6 =8673 ,
  XED_IFORM_XOR_LOCK_MEMv_GPRv =8674 ,
  XED_IFORM_XOR_LOCK_MEMv_IMMb =8675 ,
  XED_IFORM_XOR_LOCK_MEMv_IMMz =8676 ,
  XED_IFORM_XRESLDTRK =8677 ,
  XED_IFORM_XRSTOR_MEMmxsave =8678 ,
  XED_IFORM_XRSTOR64_MEMmxsave =8679 ,
  XED_IFORM_XRSTORS_MEMmxsave =8680 ,
  XED_IFORM_XRSTORS64_MEMmxsave =8681 ,
  XED_IFORM_XSAVE_MEMmxsave =8682 ,
  XED_IFORM_XSAVE64_MEMmxsave =8683 ,
  XED_IFORM_XSAVEC_MEMmxsave =8684 ,
  XED_IFORM_XSAVEC64_MEMmxsave =8685 ,
  XED_IFORM_XSAVEOPT_MEMmxsave =8686 ,
  XED_IFORM_XSAVEOPT64_MEMmxsave =8687 ,
  XED_IFORM_XSAVES_MEMmxsave =8688 ,
  XED_IFORM_XSAVES64_MEMmxsave =8689 ,
  XED_IFORM_XSETBV =8690 ,
  XED_IFORM_XSTORE =8691 ,
  XED_IFORM_XSUSLDTRK =8692 ,
  XED_IFORM_XTEST =8693 ,
  XED_IFORM_LAST
}
 

Functions

XED_DLL_EXPORT xed_iform_enum_t str2xed_iform_enum_t (const char *s)
 This converts strings to xed_iform_enum_t types.
 
XED_DLL_EXPORT const char * xed_iform_enum_t2str (const xed_iform_enum_t p)
 This converts strings to xed_iform_enum_t types.
 
XED_DLL_EXPORT xed_iform_enum_t xed_iform_enum_t_last (void)
 Returns the last element of the enumeration.
 

Macro Definition Documentation

◆ XED_IFORM_AAA_DEFINED

#define XED_IFORM_AAA_DEFINED   1

◆ XED_IFORM_AAD_IMMb_DEFINED

#define XED_IFORM_AAD_IMMb_DEFINED   1

◆ XED_IFORM_AADD_MEM32_GPR32_DEFINED

#define XED_IFORM_AADD_MEM32_GPR32_DEFINED   1

◆ XED_IFORM_AADD_MEM64_GPR64_DEFINED

#define XED_IFORM_AADD_MEM64_GPR64_DEFINED   1

◆ XED_IFORM_AADD_MEMi32_GPR32i32_APX_DEFINED

#define XED_IFORM_AADD_MEMi32_GPR32i32_APX_DEFINED   1

◆ XED_IFORM_AADD_MEMi64_GPR64i64_APX_DEFINED

#define XED_IFORM_AADD_MEMi64_GPR64i64_APX_DEFINED   1

◆ XED_IFORM_AAM_IMMb_DEFINED

#define XED_IFORM_AAM_IMMb_DEFINED   1

◆ XED_IFORM_AAND_MEM32_GPR32_DEFINED

#define XED_IFORM_AAND_MEM32_GPR32_DEFINED   1

◆ XED_IFORM_AAND_MEM64_GPR64_DEFINED

#define XED_IFORM_AAND_MEM64_GPR64_DEFINED   1

◆ XED_IFORM_AAND_MEMi32_GPR32i32_APX_DEFINED

#define XED_IFORM_AAND_MEMi32_GPR32i32_APX_DEFINED   1

◆ XED_IFORM_AAND_MEMi64_GPR64i64_APX_DEFINED

#define XED_IFORM_AAND_MEMi64_GPR64i64_APX_DEFINED   1

◆ XED_IFORM_AAS_DEFINED

#define XED_IFORM_AAS_DEFINED   1

◆ XED_IFORM_ADC_AL_IMMb_DEFINED

#define XED_IFORM_ADC_AL_IMMb_DEFINED   1

◆ XED_IFORM_ADC_GPR8_GPR8_10_DEFINED

#define XED_IFORM_ADC_GPR8_GPR8_10_DEFINED   1

◆ XED_IFORM_ADC_GPR8_GPR8_12_DEFINED

#define XED_IFORM_ADC_GPR8_GPR8_12_DEFINED   1

◆ XED_IFORM_ADC_GPR8_IMMb_80r2_DEFINED

#define XED_IFORM_ADC_GPR8_IMMb_80r2_DEFINED   1

◆ XED_IFORM_ADC_GPR8_IMMb_82r2_DEFINED

#define XED_IFORM_ADC_GPR8_IMMb_82r2_DEFINED   1

◆ XED_IFORM_ADC_GPR8_MEMb_DEFINED

#define XED_IFORM_ADC_GPR8_MEMb_DEFINED   1

◆ XED_IFORM_ADC_GPR8i8_GPR8i8_APX_DEFINED

#define XED_IFORM_ADC_GPR8i8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_ADC_GPR8i8_GPR8i8_GPR8i8_APX_DEFINED

#define XED_IFORM_ADC_GPR8i8_GPR8i8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_ADC_GPR8i8_GPR8i8_IMM8_APX_DEFINED

#define XED_IFORM_ADC_GPR8i8_GPR8i8_IMM8_APX_DEFINED   1

◆ XED_IFORM_ADC_GPR8i8_GPR8i8_MEMi8_APX_DEFINED

#define XED_IFORM_ADC_GPR8i8_GPR8i8_MEMi8_APX_DEFINED   1

◆ XED_IFORM_ADC_GPR8i8_IMM8_APX_DEFINED

#define XED_IFORM_ADC_GPR8i8_IMM8_APX_DEFINED   1

◆ XED_IFORM_ADC_GPR8i8_MEMi8_APX_DEFINED

#define XED_IFORM_ADC_GPR8i8_MEMi8_APX_DEFINED   1

◆ XED_IFORM_ADC_GPR8i8_MEMi8_GPR8i8_APX_DEFINED

#define XED_IFORM_ADC_GPR8i8_MEMi8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_ADC_GPR8i8_MEMi8_IMM8_APX_DEFINED

#define XED_IFORM_ADC_GPR8i8_MEMi8_IMM8_APX_DEFINED   1

◆ XED_IFORM_ADC_GPRv_GPRv_11_DEFINED

#define XED_IFORM_ADC_GPRv_GPRv_11_DEFINED   1

◆ XED_IFORM_ADC_GPRv_GPRv_13_DEFINED

#define XED_IFORM_ADC_GPRv_GPRv_13_DEFINED   1

◆ XED_IFORM_ADC_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_ADC_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_ADC_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_ADC_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_ADC_GPRv_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_ADC_GPRv_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_ADC_GPRv_GPRv_IMMz_APX_DEFINED

#define XED_IFORM_ADC_GPRv_GPRv_IMMz_APX_DEFINED   1

◆ XED_IFORM_ADC_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_ADC_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_ADC_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_ADC_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_ADC_GPRv_IMMb_DEFINED

#define XED_IFORM_ADC_GPRv_IMMb_DEFINED   1

◆ XED_IFORM_ADC_GPRv_IMMz_APX_DEFINED

#define XED_IFORM_ADC_GPRv_IMMz_APX_DEFINED   1

◆ XED_IFORM_ADC_GPRv_IMMz_DEFINED

#define XED_IFORM_ADC_GPRv_IMMz_DEFINED   1

◆ XED_IFORM_ADC_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_ADC_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_ADC_GPRv_MEMv_DEFINED

#define XED_IFORM_ADC_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_ADC_GPRv_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_ADC_GPRv_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_ADC_GPRv_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_ADC_GPRv_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_ADC_GPRv_MEMv_IMMz_APX_DEFINED

#define XED_IFORM_ADC_GPRv_MEMv_IMMz_APX_DEFINED   1

◆ XED_IFORM_ADC_LOCK_MEMb_GPR8_DEFINED

#define XED_IFORM_ADC_LOCK_MEMb_GPR8_DEFINED   1

◆ XED_IFORM_ADC_LOCK_MEMb_IMMb_80r2_DEFINED

#define XED_IFORM_ADC_LOCK_MEMb_IMMb_80r2_DEFINED   1

◆ XED_IFORM_ADC_LOCK_MEMb_IMMb_82r2_DEFINED

#define XED_IFORM_ADC_LOCK_MEMb_IMMb_82r2_DEFINED   1

◆ XED_IFORM_ADC_LOCK_MEMv_GPRv_DEFINED

#define XED_IFORM_ADC_LOCK_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_ADC_LOCK_MEMv_IMMb_DEFINED

#define XED_IFORM_ADC_LOCK_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_ADC_LOCK_MEMv_IMMz_DEFINED

#define XED_IFORM_ADC_LOCK_MEMv_IMMz_DEFINED   1

◆ XED_IFORM_ADC_MEMb_GPR8_DEFINED

#define XED_IFORM_ADC_MEMb_GPR8_DEFINED   1

◆ XED_IFORM_ADC_MEMb_IMMb_80r2_DEFINED

#define XED_IFORM_ADC_MEMb_IMMb_80r2_DEFINED   1

◆ XED_IFORM_ADC_MEMb_IMMb_82r2_DEFINED

#define XED_IFORM_ADC_MEMb_IMMb_82r2_DEFINED   1

◆ XED_IFORM_ADC_MEMi8_GPR8i8_APX_DEFINED

#define XED_IFORM_ADC_MEMi8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_ADC_MEMi8_IMM8_APX_DEFINED

#define XED_IFORM_ADC_MEMi8_IMM8_APX_DEFINED   1

◆ XED_IFORM_ADC_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_ADC_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_ADC_MEMv_GPRv_DEFINED

#define XED_IFORM_ADC_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_ADC_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_ADC_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_ADC_MEMv_IMMb_DEFINED

#define XED_IFORM_ADC_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_ADC_MEMv_IMMz_APX_DEFINED

#define XED_IFORM_ADC_MEMv_IMMz_APX_DEFINED   1

◆ XED_IFORM_ADC_MEMv_IMMz_DEFINED

#define XED_IFORM_ADC_MEMv_IMMz_DEFINED   1

◆ XED_IFORM_ADC_OrAX_IMMz_DEFINED

#define XED_IFORM_ADC_OrAX_IMMz_DEFINED   1

◆ XED_IFORM_ADCX_GPR32d_GPR32d_DEFINED

#define XED_IFORM_ADCX_GPR32d_GPR32d_DEFINED   1

◆ XED_IFORM_ADCX_GPR32d_MEMd_DEFINED

#define XED_IFORM_ADCX_GPR32d_MEMd_DEFINED   1

◆ XED_IFORM_ADCX_GPR32i32_GPR32i32_APX_DEFINED

#define XED_IFORM_ADCX_GPR32i32_GPR32i32_APX_DEFINED   1

◆ XED_IFORM_ADCX_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED

#define XED_IFORM_ADCX_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED   1

◆ XED_IFORM_ADCX_GPR32i32_GPR32i32_MEMi32_APX_DEFINED

#define XED_IFORM_ADCX_GPR32i32_GPR32i32_MEMi32_APX_DEFINED   1

◆ XED_IFORM_ADCX_GPR32i32_MEMi32_APX_DEFINED

#define XED_IFORM_ADCX_GPR32i32_MEMi32_APX_DEFINED   1

◆ XED_IFORM_ADCX_GPR64i64_GPR64i64_APX_DEFINED

#define XED_IFORM_ADCX_GPR64i64_GPR64i64_APX_DEFINED   1

◆ XED_IFORM_ADCX_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED

#define XED_IFORM_ADCX_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED   1

◆ XED_IFORM_ADCX_GPR64i64_GPR64i64_MEMi64_APX_DEFINED

#define XED_IFORM_ADCX_GPR64i64_GPR64i64_MEMi64_APX_DEFINED   1

◆ XED_IFORM_ADCX_GPR64i64_MEMi64_APX_DEFINED

#define XED_IFORM_ADCX_GPR64i64_MEMi64_APX_DEFINED   1

◆ XED_IFORM_ADCX_GPR64q_GPR64q_DEFINED

#define XED_IFORM_ADCX_GPR64q_GPR64q_DEFINED   1

◆ XED_IFORM_ADCX_GPR64q_MEMq_DEFINED

#define XED_IFORM_ADCX_GPR64q_MEMq_DEFINED   1

◆ XED_IFORM_ADD_AL_IMMb_DEFINED

#define XED_IFORM_ADD_AL_IMMb_DEFINED   1

◆ XED_IFORM_ADD_GPR8_GPR8_00_DEFINED

#define XED_IFORM_ADD_GPR8_GPR8_00_DEFINED   1

◆ XED_IFORM_ADD_GPR8_GPR8_02_DEFINED

#define XED_IFORM_ADD_GPR8_GPR8_02_DEFINED   1

◆ XED_IFORM_ADD_GPR8_IMMb_80r0_DEFINED

#define XED_IFORM_ADD_GPR8_IMMb_80r0_DEFINED   1

◆ XED_IFORM_ADD_GPR8_IMMb_82r0_DEFINED

#define XED_IFORM_ADD_GPR8_IMMb_82r0_DEFINED   1

◆ XED_IFORM_ADD_GPR8_MEMb_DEFINED

#define XED_IFORM_ADD_GPR8_MEMb_DEFINED   1

◆ XED_IFORM_ADD_GPR8i8_GPR8i8_APX_DEFINED

#define XED_IFORM_ADD_GPR8i8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_ADD_GPR8i8_GPR8i8_GPR8i8_APX_DEFINED

#define XED_IFORM_ADD_GPR8i8_GPR8i8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_ADD_GPR8i8_GPR8i8_IMM8_APX_DEFINED

#define XED_IFORM_ADD_GPR8i8_GPR8i8_IMM8_APX_DEFINED   1

◆ XED_IFORM_ADD_GPR8i8_GPR8i8_MEMi8_APX_DEFINED

#define XED_IFORM_ADD_GPR8i8_GPR8i8_MEMi8_APX_DEFINED   1

◆ XED_IFORM_ADD_GPR8i8_IMM8_APX_DEFINED

#define XED_IFORM_ADD_GPR8i8_IMM8_APX_DEFINED   1

◆ XED_IFORM_ADD_GPR8i8_MEMi8_APX_DEFINED

#define XED_IFORM_ADD_GPR8i8_MEMi8_APX_DEFINED   1

◆ XED_IFORM_ADD_GPR8i8_MEMi8_GPR8i8_APX_DEFINED

#define XED_IFORM_ADD_GPR8i8_MEMi8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_ADD_GPR8i8_MEMi8_IMM8_APX_DEFINED

#define XED_IFORM_ADD_GPR8i8_MEMi8_IMM8_APX_DEFINED   1

◆ XED_IFORM_ADD_GPRv_GPRv_01_DEFINED

#define XED_IFORM_ADD_GPRv_GPRv_01_DEFINED   1

◆ XED_IFORM_ADD_GPRv_GPRv_03_DEFINED

#define XED_IFORM_ADD_GPRv_GPRv_03_DEFINED   1

◆ XED_IFORM_ADD_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_ADD_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_ADD_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_ADD_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_ADD_GPRv_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_ADD_GPRv_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_ADD_GPRv_GPRv_IMMz_APX_DEFINED

#define XED_IFORM_ADD_GPRv_GPRv_IMMz_APX_DEFINED   1

◆ XED_IFORM_ADD_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_ADD_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_ADD_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_ADD_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_ADD_GPRv_IMMb_DEFINED

#define XED_IFORM_ADD_GPRv_IMMb_DEFINED   1

◆ XED_IFORM_ADD_GPRv_IMMz_APX_DEFINED

#define XED_IFORM_ADD_GPRv_IMMz_APX_DEFINED   1

◆ XED_IFORM_ADD_GPRv_IMMz_DEFINED

#define XED_IFORM_ADD_GPRv_IMMz_DEFINED   1

◆ XED_IFORM_ADD_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_ADD_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_ADD_GPRv_MEMv_DEFINED

#define XED_IFORM_ADD_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_ADD_GPRv_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_ADD_GPRv_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_ADD_GPRv_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_ADD_GPRv_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_ADD_GPRv_MEMv_IMMz_APX_DEFINED

#define XED_IFORM_ADD_GPRv_MEMv_IMMz_APX_DEFINED   1

◆ XED_IFORM_ADD_LOCK_MEMb_GPR8_DEFINED

#define XED_IFORM_ADD_LOCK_MEMb_GPR8_DEFINED   1

◆ XED_IFORM_ADD_LOCK_MEMb_IMMb_80r0_DEFINED

#define XED_IFORM_ADD_LOCK_MEMb_IMMb_80r0_DEFINED   1

◆ XED_IFORM_ADD_LOCK_MEMb_IMMb_82r0_DEFINED

#define XED_IFORM_ADD_LOCK_MEMb_IMMb_82r0_DEFINED   1

◆ XED_IFORM_ADD_LOCK_MEMv_GPRv_DEFINED

#define XED_IFORM_ADD_LOCK_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_ADD_LOCK_MEMv_IMMb_DEFINED

#define XED_IFORM_ADD_LOCK_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_ADD_LOCK_MEMv_IMMz_DEFINED

#define XED_IFORM_ADD_LOCK_MEMv_IMMz_DEFINED   1

◆ XED_IFORM_ADD_MEMb_GPR8_DEFINED

#define XED_IFORM_ADD_MEMb_GPR8_DEFINED   1

◆ XED_IFORM_ADD_MEMb_IMMb_80r0_DEFINED

#define XED_IFORM_ADD_MEMb_IMMb_80r0_DEFINED   1

◆ XED_IFORM_ADD_MEMb_IMMb_82r0_DEFINED

#define XED_IFORM_ADD_MEMb_IMMb_82r0_DEFINED   1

◆ XED_IFORM_ADD_MEMi8_GPR8i8_APX_DEFINED

#define XED_IFORM_ADD_MEMi8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_ADD_MEMi8_IMM8_APX_DEFINED

#define XED_IFORM_ADD_MEMi8_IMM8_APX_DEFINED   1

◆ XED_IFORM_ADD_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_ADD_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_ADD_MEMv_GPRv_DEFINED

#define XED_IFORM_ADD_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_ADD_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_ADD_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_ADD_MEMv_IMMb_DEFINED

#define XED_IFORM_ADD_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_ADD_MEMv_IMMz_APX_DEFINED

#define XED_IFORM_ADD_MEMv_IMMz_APX_DEFINED   1

◆ XED_IFORM_ADD_MEMv_IMMz_DEFINED

#define XED_IFORM_ADD_MEMv_IMMz_DEFINED   1

◆ XED_IFORM_ADD_OrAX_IMMz_DEFINED

#define XED_IFORM_ADD_OrAX_IMMz_DEFINED   1

◆ XED_IFORM_ADDPD_XMMpd_MEMpd_DEFINED

#define XED_IFORM_ADDPD_XMMpd_MEMpd_DEFINED   1

◆ XED_IFORM_ADDPD_XMMpd_XMMpd_DEFINED

#define XED_IFORM_ADDPD_XMMpd_XMMpd_DEFINED   1

◆ XED_IFORM_ADDPS_XMMps_MEMps_DEFINED

#define XED_IFORM_ADDPS_XMMps_MEMps_DEFINED   1

◆ XED_IFORM_ADDPS_XMMps_XMMps_DEFINED

#define XED_IFORM_ADDPS_XMMps_XMMps_DEFINED   1

◆ XED_IFORM_ADDSD_XMMsd_MEMsd_DEFINED

#define XED_IFORM_ADDSD_XMMsd_MEMsd_DEFINED   1

◆ XED_IFORM_ADDSD_XMMsd_XMMsd_DEFINED

#define XED_IFORM_ADDSD_XMMsd_XMMsd_DEFINED   1

◆ XED_IFORM_ADDSS_XMMss_MEMss_DEFINED

#define XED_IFORM_ADDSS_XMMss_MEMss_DEFINED   1

◆ XED_IFORM_ADDSS_XMMss_XMMss_DEFINED

#define XED_IFORM_ADDSS_XMMss_XMMss_DEFINED   1

◆ XED_IFORM_ADDSUBPD_XMMpd_MEMpd_DEFINED

#define XED_IFORM_ADDSUBPD_XMMpd_MEMpd_DEFINED   1

◆ XED_IFORM_ADDSUBPD_XMMpd_XMMpd_DEFINED

#define XED_IFORM_ADDSUBPD_XMMpd_XMMpd_DEFINED   1

◆ XED_IFORM_ADDSUBPS_XMMps_MEMps_DEFINED

#define XED_IFORM_ADDSUBPS_XMMps_MEMps_DEFINED   1

◆ XED_IFORM_ADDSUBPS_XMMps_XMMps_DEFINED

#define XED_IFORM_ADDSUBPS_XMMps_XMMps_DEFINED   1

◆ XED_IFORM_ADOX_GPR32d_GPR32d_DEFINED

#define XED_IFORM_ADOX_GPR32d_GPR32d_DEFINED   1

◆ XED_IFORM_ADOX_GPR32d_MEMd_DEFINED

#define XED_IFORM_ADOX_GPR32d_MEMd_DEFINED   1

◆ XED_IFORM_ADOX_GPR32i32_GPR32i32_APX_DEFINED

#define XED_IFORM_ADOX_GPR32i32_GPR32i32_APX_DEFINED   1

◆ XED_IFORM_ADOX_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED

#define XED_IFORM_ADOX_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED   1

◆ XED_IFORM_ADOX_GPR32i32_GPR32i32_MEMi32_APX_DEFINED

#define XED_IFORM_ADOX_GPR32i32_GPR32i32_MEMi32_APX_DEFINED   1

◆ XED_IFORM_ADOX_GPR32i32_MEMi32_APX_DEFINED

#define XED_IFORM_ADOX_GPR32i32_MEMi32_APX_DEFINED   1

◆ XED_IFORM_ADOX_GPR64i64_GPR64i64_APX_DEFINED

#define XED_IFORM_ADOX_GPR64i64_GPR64i64_APX_DEFINED   1

◆ XED_IFORM_ADOX_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED

#define XED_IFORM_ADOX_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED   1

◆ XED_IFORM_ADOX_GPR64i64_GPR64i64_MEMi64_APX_DEFINED

#define XED_IFORM_ADOX_GPR64i64_GPR64i64_MEMi64_APX_DEFINED   1

◆ XED_IFORM_ADOX_GPR64i64_MEMi64_APX_DEFINED

#define XED_IFORM_ADOX_GPR64i64_MEMi64_APX_DEFINED   1

◆ XED_IFORM_ADOX_GPR64q_GPR64q_DEFINED

#define XED_IFORM_ADOX_GPR64q_GPR64q_DEFINED   1

◆ XED_IFORM_ADOX_GPR64q_MEMq_DEFINED

#define XED_IFORM_ADOX_GPR64q_MEMq_DEFINED   1

◆ XED_IFORM_AESDEC128KL_XMMu8_MEMu8_DEFINED

#define XED_IFORM_AESDEC128KL_XMMu8_MEMu8_DEFINED   1

◆ XED_IFORM_AESDEC256KL_XMMu8_MEMu8_DEFINED

#define XED_IFORM_AESDEC256KL_XMMu8_MEMu8_DEFINED   1

◆ XED_IFORM_AESDEC_XMMdq_MEMdq_DEFINED

#define XED_IFORM_AESDEC_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_AESDEC_XMMdq_XMMdq_DEFINED

#define XED_IFORM_AESDEC_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_AESDECLAST_XMMdq_MEMdq_DEFINED

#define XED_IFORM_AESDECLAST_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_AESDECLAST_XMMdq_XMMdq_DEFINED

#define XED_IFORM_AESDECLAST_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_AESDECWIDE128KL_MEMu8_DEFINED

#define XED_IFORM_AESDECWIDE128KL_MEMu8_DEFINED   1

◆ XED_IFORM_AESDECWIDE256KL_MEMu8_DEFINED

#define XED_IFORM_AESDECWIDE256KL_MEMu8_DEFINED   1

◆ XED_IFORM_AESENC128KL_XMMu8_MEMu8_DEFINED

#define XED_IFORM_AESENC128KL_XMMu8_MEMu8_DEFINED   1

◆ XED_IFORM_AESENC256KL_XMMu8_MEMu8_DEFINED

#define XED_IFORM_AESENC256KL_XMMu8_MEMu8_DEFINED   1

◆ XED_IFORM_AESENC_XMMdq_MEMdq_DEFINED

#define XED_IFORM_AESENC_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_AESENC_XMMdq_XMMdq_DEFINED

#define XED_IFORM_AESENC_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_AESENCLAST_XMMdq_MEMdq_DEFINED

#define XED_IFORM_AESENCLAST_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_AESENCLAST_XMMdq_XMMdq_DEFINED

#define XED_IFORM_AESENCLAST_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_AESENCWIDE128KL_MEMu8_DEFINED

#define XED_IFORM_AESENCWIDE128KL_MEMu8_DEFINED   1

◆ XED_IFORM_AESENCWIDE256KL_MEMu8_DEFINED

#define XED_IFORM_AESENCWIDE256KL_MEMu8_DEFINED   1

◆ XED_IFORM_AESIMC_XMMdq_MEMdq_DEFINED

#define XED_IFORM_AESIMC_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_AESIMC_XMMdq_XMMdq_DEFINED

#define XED_IFORM_AESIMC_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_AESKEYGENASSIST_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_AESKEYGENASSIST_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_AESKEYGENASSIST_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_AESKEYGENASSIST_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_AND_AL_IMMb_DEFINED

#define XED_IFORM_AND_AL_IMMb_DEFINED   1

◆ XED_IFORM_AND_GPR8_GPR8_20_DEFINED

#define XED_IFORM_AND_GPR8_GPR8_20_DEFINED   1

◆ XED_IFORM_AND_GPR8_GPR8_22_DEFINED

#define XED_IFORM_AND_GPR8_GPR8_22_DEFINED   1

◆ XED_IFORM_AND_GPR8_IMMb_80r4_DEFINED

#define XED_IFORM_AND_GPR8_IMMb_80r4_DEFINED   1

◆ XED_IFORM_AND_GPR8_IMMb_82r4_DEFINED

#define XED_IFORM_AND_GPR8_IMMb_82r4_DEFINED   1

◆ XED_IFORM_AND_GPR8_MEMb_DEFINED

#define XED_IFORM_AND_GPR8_MEMb_DEFINED   1

◆ XED_IFORM_AND_GPR8i8_GPR8i8_APX_DEFINED

#define XED_IFORM_AND_GPR8i8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_AND_GPR8i8_GPR8i8_GPR8i8_APX_DEFINED

#define XED_IFORM_AND_GPR8i8_GPR8i8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_AND_GPR8i8_GPR8i8_IMM8_APX_DEFINED

#define XED_IFORM_AND_GPR8i8_GPR8i8_IMM8_APX_DEFINED   1

◆ XED_IFORM_AND_GPR8i8_GPR8i8_MEMi8_APX_DEFINED

#define XED_IFORM_AND_GPR8i8_GPR8i8_MEMi8_APX_DEFINED   1

◆ XED_IFORM_AND_GPR8i8_IMM8_APX_DEFINED

#define XED_IFORM_AND_GPR8i8_IMM8_APX_DEFINED   1

◆ XED_IFORM_AND_GPR8i8_MEMi8_APX_DEFINED

#define XED_IFORM_AND_GPR8i8_MEMi8_APX_DEFINED   1

◆ XED_IFORM_AND_GPR8i8_MEMi8_GPR8i8_APX_DEFINED

#define XED_IFORM_AND_GPR8i8_MEMi8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_AND_GPR8i8_MEMi8_IMM8_APX_DEFINED

#define XED_IFORM_AND_GPR8i8_MEMi8_IMM8_APX_DEFINED   1

◆ XED_IFORM_AND_GPRv_GPRv_21_DEFINED

#define XED_IFORM_AND_GPRv_GPRv_21_DEFINED   1

◆ XED_IFORM_AND_GPRv_GPRv_23_DEFINED

#define XED_IFORM_AND_GPRv_GPRv_23_DEFINED   1

◆ XED_IFORM_AND_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_AND_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_AND_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_AND_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_AND_GPRv_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_AND_GPRv_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_AND_GPRv_GPRv_IMMz_APX_DEFINED

#define XED_IFORM_AND_GPRv_GPRv_IMMz_APX_DEFINED   1

◆ XED_IFORM_AND_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_AND_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_AND_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_AND_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_AND_GPRv_IMMb_DEFINED

#define XED_IFORM_AND_GPRv_IMMb_DEFINED   1

◆ XED_IFORM_AND_GPRv_IMMz_APX_DEFINED

#define XED_IFORM_AND_GPRv_IMMz_APX_DEFINED   1

◆ XED_IFORM_AND_GPRv_IMMz_DEFINED

#define XED_IFORM_AND_GPRv_IMMz_DEFINED   1

◆ XED_IFORM_AND_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_AND_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_AND_GPRv_MEMv_DEFINED

#define XED_IFORM_AND_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_AND_GPRv_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_AND_GPRv_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_AND_GPRv_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_AND_GPRv_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_AND_GPRv_MEMv_IMMz_APX_DEFINED

#define XED_IFORM_AND_GPRv_MEMv_IMMz_APX_DEFINED   1

◆ XED_IFORM_AND_LOCK_MEMb_GPR8_DEFINED

#define XED_IFORM_AND_LOCK_MEMb_GPR8_DEFINED   1

◆ XED_IFORM_AND_LOCK_MEMb_IMMb_80r4_DEFINED

#define XED_IFORM_AND_LOCK_MEMb_IMMb_80r4_DEFINED   1

◆ XED_IFORM_AND_LOCK_MEMb_IMMb_82r4_DEFINED

#define XED_IFORM_AND_LOCK_MEMb_IMMb_82r4_DEFINED   1

◆ XED_IFORM_AND_LOCK_MEMv_GPRv_DEFINED

#define XED_IFORM_AND_LOCK_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_AND_LOCK_MEMv_IMMb_DEFINED

#define XED_IFORM_AND_LOCK_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_AND_LOCK_MEMv_IMMz_DEFINED

#define XED_IFORM_AND_LOCK_MEMv_IMMz_DEFINED   1

◆ XED_IFORM_AND_MEMb_GPR8_DEFINED

#define XED_IFORM_AND_MEMb_GPR8_DEFINED   1

◆ XED_IFORM_AND_MEMb_IMMb_80r4_DEFINED

#define XED_IFORM_AND_MEMb_IMMb_80r4_DEFINED   1

◆ XED_IFORM_AND_MEMb_IMMb_82r4_DEFINED

#define XED_IFORM_AND_MEMb_IMMb_82r4_DEFINED   1

◆ XED_IFORM_AND_MEMi8_GPR8i8_APX_DEFINED

#define XED_IFORM_AND_MEMi8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_AND_MEMi8_IMM8_APX_DEFINED

#define XED_IFORM_AND_MEMi8_IMM8_APX_DEFINED   1

◆ XED_IFORM_AND_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_AND_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_AND_MEMv_GPRv_DEFINED

#define XED_IFORM_AND_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_AND_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_AND_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_AND_MEMv_IMMb_DEFINED

#define XED_IFORM_AND_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_AND_MEMv_IMMz_APX_DEFINED

#define XED_IFORM_AND_MEMv_IMMz_APX_DEFINED   1

◆ XED_IFORM_AND_MEMv_IMMz_DEFINED

#define XED_IFORM_AND_MEMv_IMMz_DEFINED   1

◆ XED_IFORM_AND_OrAX_IMMz_DEFINED

#define XED_IFORM_AND_OrAX_IMMz_DEFINED   1

◆ XED_IFORM_ANDN_GPR32d_GPR32d_GPR32d_DEFINED

#define XED_IFORM_ANDN_GPR32d_GPR32d_GPR32d_DEFINED   1

◆ XED_IFORM_ANDN_GPR32d_GPR32d_MEMd_DEFINED

#define XED_IFORM_ANDN_GPR32d_GPR32d_MEMd_DEFINED   1

◆ XED_IFORM_ANDN_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED

#define XED_IFORM_ANDN_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED   1

◆ XED_IFORM_ANDN_GPR32i32_GPR32i32_MEMi32_APX_DEFINED

#define XED_IFORM_ANDN_GPR32i32_GPR32i32_MEMi32_APX_DEFINED   1

◆ XED_IFORM_ANDN_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED

#define XED_IFORM_ANDN_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED   1

◆ XED_IFORM_ANDN_GPR64i64_GPR64i64_MEMi64_APX_DEFINED

#define XED_IFORM_ANDN_GPR64i64_GPR64i64_MEMi64_APX_DEFINED   1

◆ XED_IFORM_ANDN_GPR64q_GPR64q_GPR64q_DEFINED

#define XED_IFORM_ANDN_GPR64q_GPR64q_GPR64q_DEFINED   1

◆ XED_IFORM_ANDN_GPR64q_GPR64q_MEMq_DEFINED

#define XED_IFORM_ANDN_GPR64q_GPR64q_MEMq_DEFINED   1

◆ XED_IFORM_ANDNPD_XMMxuq_MEMxuq_DEFINED

#define XED_IFORM_ANDNPD_XMMxuq_MEMxuq_DEFINED   1

◆ XED_IFORM_ANDNPD_XMMxuq_XMMxuq_DEFINED

#define XED_IFORM_ANDNPD_XMMxuq_XMMxuq_DEFINED   1

◆ XED_IFORM_ANDNPS_XMMxud_MEMxud_DEFINED

#define XED_IFORM_ANDNPS_XMMxud_MEMxud_DEFINED   1

◆ XED_IFORM_ANDNPS_XMMxud_XMMxud_DEFINED

#define XED_IFORM_ANDNPS_XMMxud_XMMxud_DEFINED   1

◆ XED_IFORM_ANDPD_XMMxuq_MEMxuq_DEFINED

#define XED_IFORM_ANDPD_XMMxuq_MEMxuq_DEFINED   1

◆ XED_IFORM_ANDPD_XMMxuq_XMMxuq_DEFINED

#define XED_IFORM_ANDPD_XMMxuq_XMMxuq_DEFINED   1

◆ XED_IFORM_ANDPS_XMMxud_MEMxud_DEFINED

#define XED_IFORM_ANDPS_XMMxud_MEMxud_DEFINED   1

◆ XED_IFORM_ANDPS_XMMxud_XMMxud_DEFINED

#define XED_IFORM_ANDPS_XMMxud_XMMxud_DEFINED   1

◆ XED_IFORM_AOR_MEM32_GPR32_DEFINED

#define XED_IFORM_AOR_MEM32_GPR32_DEFINED   1

◆ XED_IFORM_AOR_MEM64_GPR64_DEFINED

#define XED_IFORM_AOR_MEM64_GPR64_DEFINED   1

◆ XED_IFORM_AOR_MEMi32_GPR32i32_APX_DEFINED

#define XED_IFORM_AOR_MEMi32_GPR32i32_APX_DEFINED   1

◆ XED_IFORM_AOR_MEMi64_GPR64i64_APX_DEFINED

#define XED_IFORM_AOR_MEMi64_GPR64i64_APX_DEFINED   1

◆ XED_IFORM_ARPL_GPR16_GPR16_DEFINED

#define XED_IFORM_ARPL_GPR16_GPR16_DEFINED   1

◆ XED_IFORM_ARPL_MEMw_GPR16_DEFINED

#define XED_IFORM_ARPL_MEMw_GPR16_DEFINED   1

◆ XED_IFORM_AXOR_MEM32_GPR32_DEFINED

#define XED_IFORM_AXOR_MEM32_GPR32_DEFINED   1

◆ XED_IFORM_AXOR_MEM64_GPR64_DEFINED

#define XED_IFORM_AXOR_MEM64_GPR64_DEFINED   1

◆ XED_IFORM_AXOR_MEMi32_GPR32i32_APX_DEFINED

#define XED_IFORM_AXOR_MEMi32_GPR32i32_APX_DEFINED   1

◆ XED_IFORM_AXOR_MEMi64_GPR64i64_APX_DEFINED

#define XED_IFORM_AXOR_MEMi64_GPR64i64_APX_DEFINED   1

◆ XED_IFORM_BEXTR_GPR32d_GPR32d_GPR32d_DEFINED

#define XED_IFORM_BEXTR_GPR32d_GPR32d_GPR32d_DEFINED   1

◆ XED_IFORM_BEXTR_GPR32d_MEMd_GPR32d_DEFINED

#define XED_IFORM_BEXTR_GPR32d_MEMd_GPR32d_DEFINED   1

◆ XED_IFORM_BEXTR_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED

#define XED_IFORM_BEXTR_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED   1

◆ XED_IFORM_BEXTR_GPR32i32_MEMi32_GPR32i32_APX_DEFINED

#define XED_IFORM_BEXTR_GPR32i32_MEMi32_GPR32i32_APX_DEFINED   1

◆ XED_IFORM_BEXTR_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED

#define XED_IFORM_BEXTR_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED   1

◆ XED_IFORM_BEXTR_GPR64i64_MEMi64_GPR64i64_APX_DEFINED

#define XED_IFORM_BEXTR_GPR64i64_MEMi64_GPR64i64_APX_DEFINED   1

◆ XED_IFORM_BEXTR_GPR64q_GPR64q_GPR64q_DEFINED

#define XED_IFORM_BEXTR_GPR64q_GPR64q_GPR64q_DEFINED   1

◆ XED_IFORM_BEXTR_GPR64q_MEMq_GPR64q_DEFINED

#define XED_IFORM_BEXTR_GPR64q_MEMq_GPR64q_DEFINED   1

◆ XED_IFORM_BEXTR_XOP_GPR32d_GPR32d_IMMd_DEFINED

#define XED_IFORM_BEXTR_XOP_GPR32d_GPR32d_IMMd_DEFINED   1

◆ XED_IFORM_BEXTR_XOP_GPR32d_MEMd_IMMd_DEFINED

#define XED_IFORM_BEXTR_XOP_GPR32d_MEMd_IMMd_DEFINED   1

◆ XED_IFORM_BEXTR_XOP_GPRyy_GPRyy_IMMd_DEFINED

#define XED_IFORM_BEXTR_XOP_GPRyy_GPRyy_IMMd_DEFINED   1

◆ XED_IFORM_BEXTR_XOP_GPRyy_MEMy_IMMd_DEFINED

#define XED_IFORM_BEXTR_XOP_GPRyy_MEMy_IMMd_DEFINED   1

◆ XED_IFORM_BLCFILL_GPR32d_GPR32d_DEFINED

#define XED_IFORM_BLCFILL_GPR32d_GPR32d_DEFINED   1

◆ XED_IFORM_BLCFILL_GPR32d_MEMd_DEFINED

#define XED_IFORM_BLCFILL_GPR32d_MEMd_DEFINED   1

◆ XED_IFORM_BLCFILL_GPRyy_GPRyy_DEFINED

#define XED_IFORM_BLCFILL_GPRyy_GPRyy_DEFINED   1

◆ XED_IFORM_BLCFILL_GPRyy_MEMy_DEFINED

#define XED_IFORM_BLCFILL_GPRyy_MEMy_DEFINED   1

◆ XED_IFORM_BLCI_GPR32d_GPR32d_DEFINED

#define XED_IFORM_BLCI_GPR32d_GPR32d_DEFINED   1

◆ XED_IFORM_BLCI_GPR32d_MEMd_DEFINED

#define XED_IFORM_BLCI_GPR32d_MEMd_DEFINED   1

◆ XED_IFORM_BLCI_GPRyy_GPRyy_DEFINED

#define XED_IFORM_BLCI_GPRyy_GPRyy_DEFINED   1

◆ XED_IFORM_BLCI_GPRyy_MEMy_DEFINED

#define XED_IFORM_BLCI_GPRyy_MEMy_DEFINED   1

◆ XED_IFORM_BLCIC_GPR32d_GPR32d_DEFINED

#define XED_IFORM_BLCIC_GPR32d_GPR32d_DEFINED   1

◆ XED_IFORM_BLCIC_GPR32d_MEMd_DEFINED

#define XED_IFORM_BLCIC_GPR32d_MEMd_DEFINED   1

◆ XED_IFORM_BLCIC_GPRyy_GPRyy_DEFINED

#define XED_IFORM_BLCIC_GPRyy_GPRyy_DEFINED   1

◆ XED_IFORM_BLCIC_GPRyy_MEMy_DEFINED

#define XED_IFORM_BLCIC_GPRyy_MEMy_DEFINED   1

◆ XED_IFORM_BLCMSK_GPR32d_GPR32d_DEFINED

#define XED_IFORM_BLCMSK_GPR32d_GPR32d_DEFINED   1

◆ XED_IFORM_BLCMSK_GPR32d_MEMd_DEFINED

#define XED_IFORM_BLCMSK_GPR32d_MEMd_DEFINED   1

◆ XED_IFORM_BLCMSK_GPRyy_GPRyy_DEFINED

#define XED_IFORM_BLCMSK_GPRyy_GPRyy_DEFINED   1

◆ XED_IFORM_BLCMSK_GPRyy_MEMy_DEFINED

#define XED_IFORM_BLCMSK_GPRyy_MEMy_DEFINED   1

◆ XED_IFORM_BLCS_GPR32d_GPR32d_DEFINED

#define XED_IFORM_BLCS_GPR32d_GPR32d_DEFINED   1

◆ XED_IFORM_BLCS_GPR32d_MEMd_DEFINED

#define XED_IFORM_BLCS_GPR32d_MEMd_DEFINED   1

◆ XED_IFORM_BLCS_GPRyy_GPRyy_DEFINED

#define XED_IFORM_BLCS_GPRyy_GPRyy_DEFINED   1

◆ XED_IFORM_BLCS_GPRyy_MEMy_DEFINED

#define XED_IFORM_BLCS_GPRyy_MEMy_DEFINED   1

◆ XED_IFORM_BLENDPD_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_BLENDPD_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_BLENDPD_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_BLENDPD_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_BLENDPS_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_BLENDPS_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_BLENDPS_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_BLENDPS_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_BLENDVPD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_BLENDVPD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_BLENDVPD_XMMdq_XMMdq_DEFINED

#define XED_IFORM_BLENDVPD_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_BLENDVPS_XMMdq_MEMdq_DEFINED

#define XED_IFORM_BLENDVPS_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_BLENDVPS_XMMdq_XMMdq_DEFINED

#define XED_IFORM_BLENDVPS_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_BLSFILL_GPR32d_GPR32d_DEFINED

#define XED_IFORM_BLSFILL_GPR32d_GPR32d_DEFINED   1

◆ XED_IFORM_BLSFILL_GPR32d_MEMd_DEFINED

#define XED_IFORM_BLSFILL_GPR32d_MEMd_DEFINED   1

◆ XED_IFORM_BLSFILL_GPRyy_GPRyy_DEFINED

#define XED_IFORM_BLSFILL_GPRyy_GPRyy_DEFINED   1

◆ XED_IFORM_BLSFILL_GPRyy_MEMy_DEFINED

#define XED_IFORM_BLSFILL_GPRyy_MEMy_DEFINED   1

◆ XED_IFORM_BLSI_GPR32d_GPR32d_DEFINED

#define XED_IFORM_BLSI_GPR32d_GPR32d_DEFINED   1

◆ XED_IFORM_BLSI_GPR32d_MEMd_DEFINED

#define XED_IFORM_BLSI_GPR32d_MEMd_DEFINED   1

◆ XED_IFORM_BLSI_GPR32i32_GPR32i32_APX_DEFINED

#define XED_IFORM_BLSI_GPR32i32_GPR32i32_APX_DEFINED   1

◆ XED_IFORM_BLSI_GPR32i32_MEMi32_APX_DEFINED

#define XED_IFORM_BLSI_GPR32i32_MEMi32_APX_DEFINED   1

◆ XED_IFORM_BLSI_GPR64i64_GPR64i64_APX_DEFINED

#define XED_IFORM_BLSI_GPR64i64_GPR64i64_APX_DEFINED   1

◆ XED_IFORM_BLSI_GPR64i64_MEMi64_APX_DEFINED

#define XED_IFORM_BLSI_GPR64i64_MEMi64_APX_DEFINED   1

◆ XED_IFORM_BLSI_GPR64q_GPR64q_DEFINED

#define XED_IFORM_BLSI_GPR64q_GPR64q_DEFINED   1

◆ XED_IFORM_BLSI_GPR64q_MEMq_DEFINED

#define XED_IFORM_BLSI_GPR64q_MEMq_DEFINED   1

◆ XED_IFORM_BLSIC_GPR32d_GPR32d_DEFINED

#define XED_IFORM_BLSIC_GPR32d_GPR32d_DEFINED   1

◆ XED_IFORM_BLSIC_GPR32d_MEMd_DEFINED

#define XED_IFORM_BLSIC_GPR32d_MEMd_DEFINED   1

◆ XED_IFORM_BLSIC_GPRyy_GPRyy_DEFINED

#define XED_IFORM_BLSIC_GPRyy_GPRyy_DEFINED   1

◆ XED_IFORM_BLSIC_GPRyy_MEMy_DEFINED

#define XED_IFORM_BLSIC_GPRyy_MEMy_DEFINED   1

◆ XED_IFORM_BLSMSK_GPR32d_GPR32d_DEFINED

#define XED_IFORM_BLSMSK_GPR32d_GPR32d_DEFINED   1

◆ XED_IFORM_BLSMSK_GPR32d_MEMd_DEFINED

#define XED_IFORM_BLSMSK_GPR32d_MEMd_DEFINED   1

◆ XED_IFORM_BLSMSK_GPR32i32_GPR32i32_APX_DEFINED

#define XED_IFORM_BLSMSK_GPR32i32_GPR32i32_APX_DEFINED   1

◆ XED_IFORM_BLSMSK_GPR32i32_MEMi32_APX_DEFINED

#define XED_IFORM_BLSMSK_GPR32i32_MEMi32_APX_DEFINED   1

◆ XED_IFORM_BLSMSK_GPR64i64_GPR64i64_APX_DEFINED

#define XED_IFORM_BLSMSK_GPR64i64_GPR64i64_APX_DEFINED   1

◆ XED_IFORM_BLSMSK_GPR64i64_MEMi64_APX_DEFINED

#define XED_IFORM_BLSMSK_GPR64i64_MEMi64_APX_DEFINED   1

◆ XED_IFORM_BLSMSK_GPR64q_GPR64q_DEFINED

#define XED_IFORM_BLSMSK_GPR64q_GPR64q_DEFINED   1

◆ XED_IFORM_BLSMSK_GPR64q_MEMq_DEFINED

#define XED_IFORM_BLSMSK_GPR64q_MEMq_DEFINED   1

◆ XED_IFORM_BLSR_GPR32d_GPR32d_DEFINED

#define XED_IFORM_BLSR_GPR32d_GPR32d_DEFINED   1

◆ XED_IFORM_BLSR_GPR32d_MEMd_DEFINED

#define XED_IFORM_BLSR_GPR32d_MEMd_DEFINED   1

◆ XED_IFORM_BLSR_GPR32i32_GPR32i32_APX_DEFINED

#define XED_IFORM_BLSR_GPR32i32_GPR32i32_APX_DEFINED   1

◆ XED_IFORM_BLSR_GPR32i32_MEMi32_APX_DEFINED

#define XED_IFORM_BLSR_GPR32i32_MEMi32_APX_DEFINED   1

◆ XED_IFORM_BLSR_GPR64i64_GPR64i64_APX_DEFINED

#define XED_IFORM_BLSR_GPR64i64_GPR64i64_APX_DEFINED   1

◆ XED_IFORM_BLSR_GPR64i64_MEMi64_APX_DEFINED

#define XED_IFORM_BLSR_GPR64i64_MEMi64_APX_DEFINED   1

◆ XED_IFORM_BLSR_GPR64q_GPR64q_DEFINED

#define XED_IFORM_BLSR_GPR64q_GPR64q_DEFINED   1

◆ XED_IFORM_BLSR_GPR64q_MEMq_DEFINED

#define XED_IFORM_BLSR_GPR64q_MEMq_DEFINED   1

◆ XED_IFORM_BNDCL_BND_AGEN_DEFINED

#define XED_IFORM_BNDCL_BND_AGEN_DEFINED   1

◆ XED_IFORM_BNDCL_BND_GPR32_DEFINED

#define XED_IFORM_BNDCL_BND_GPR32_DEFINED   1

◆ XED_IFORM_BNDCL_BND_GPR64_DEFINED

#define XED_IFORM_BNDCL_BND_GPR64_DEFINED   1

◆ XED_IFORM_BNDCN_BND_AGEN_DEFINED

#define XED_IFORM_BNDCN_BND_AGEN_DEFINED   1

◆ XED_IFORM_BNDCN_BND_GPR32_DEFINED

#define XED_IFORM_BNDCN_BND_GPR32_DEFINED   1

◆ XED_IFORM_BNDCN_BND_GPR64_DEFINED

#define XED_IFORM_BNDCN_BND_GPR64_DEFINED   1

◆ XED_IFORM_BNDCU_BND_AGEN_DEFINED

#define XED_IFORM_BNDCU_BND_AGEN_DEFINED   1

◆ XED_IFORM_BNDCU_BND_GPR32_DEFINED

#define XED_IFORM_BNDCU_BND_GPR32_DEFINED   1

◆ XED_IFORM_BNDCU_BND_GPR64_DEFINED

#define XED_IFORM_BNDCU_BND_GPR64_DEFINED   1

◆ XED_IFORM_BNDLDX_BND_MEMbnd32_DEFINED

#define XED_IFORM_BNDLDX_BND_MEMbnd32_DEFINED   1

◆ XED_IFORM_BNDLDX_BND_MEMbnd64_DEFINED

#define XED_IFORM_BNDLDX_BND_MEMbnd64_DEFINED   1

◆ XED_IFORM_BNDMK_BND_AGEN_DEFINED

#define XED_IFORM_BNDMK_BND_AGEN_DEFINED   1

◆ XED_IFORM_BNDMOV_BND_BND_DEFINED

#define XED_IFORM_BNDMOV_BND_BND_DEFINED   1

◆ XED_IFORM_BNDMOV_BND_MEMdq_DEFINED

#define XED_IFORM_BNDMOV_BND_MEMdq_DEFINED   1

◆ XED_IFORM_BNDMOV_BND_MEMq_DEFINED

#define XED_IFORM_BNDMOV_BND_MEMq_DEFINED   1

◆ XED_IFORM_BNDMOV_MEMdq_BND_DEFINED

#define XED_IFORM_BNDMOV_MEMdq_BND_DEFINED   1

◆ XED_IFORM_BNDMOV_MEMq_BND_DEFINED

#define XED_IFORM_BNDMOV_MEMq_BND_DEFINED   1

◆ XED_IFORM_BNDSTX_MEMbnd32_BND_DEFINED

#define XED_IFORM_BNDSTX_MEMbnd32_BND_DEFINED   1

◆ XED_IFORM_BNDSTX_MEMbnd64_BND_DEFINED

#define XED_IFORM_BNDSTX_MEMbnd64_BND_DEFINED   1

◆ XED_IFORM_BOUND_GPR16_MEMa16_DEFINED

#define XED_IFORM_BOUND_GPR16_MEMa16_DEFINED   1

◆ XED_IFORM_BOUND_GPR32_MEMa32_DEFINED

#define XED_IFORM_BOUND_GPR32_MEMa32_DEFINED   1

◆ XED_IFORM_BSF_GPRv_GPRv_DEFINED

#define XED_IFORM_BSF_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_BSF_GPRv_MEMv_DEFINED

#define XED_IFORM_BSF_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_BSR_GPRv_GPRv_DEFINED

#define XED_IFORM_BSR_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_BSR_GPRv_MEMv_DEFINED

#define XED_IFORM_BSR_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_BSWAP_GPRv_DEFINED

#define XED_IFORM_BSWAP_GPRv_DEFINED   1

◆ XED_IFORM_BT_GPRv_GPRv_DEFINED

#define XED_IFORM_BT_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_BT_GPRv_IMMb_DEFINED

#define XED_IFORM_BT_GPRv_IMMb_DEFINED   1

◆ XED_IFORM_BT_MEMv_GPRv_DEFINED

#define XED_IFORM_BT_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_BT_MEMv_IMMb_DEFINED

#define XED_IFORM_BT_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_BTC_GPRv_GPRv_DEFINED

#define XED_IFORM_BTC_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_BTC_GPRv_IMMb_DEFINED

#define XED_IFORM_BTC_GPRv_IMMb_DEFINED   1

◆ XED_IFORM_BTC_LOCK_MEMv_GPRv_DEFINED

#define XED_IFORM_BTC_LOCK_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_BTC_LOCK_MEMv_IMMb_DEFINED

#define XED_IFORM_BTC_LOCK_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_BTC_MEMv_GPRv_DEFINED

#define XED_IFORM_BTC_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_BTC_MEMv_IMMb_DEFINED

#define XED_IFORM_BTC_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_BTR_GPRv_GPRv_DEFINED

#define XED_IFORM_BTR_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_BTR_GPRv_IMMb_DEFINED

#define XED_IFORM_BTR_GPRv_IMMb_DEFINED   1

◆ XED_IFORM_BTR_LOCK_MEMv_GPRv_DEFINED

#define XED_IFORM_BTR_LOCK_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_BTR_LOCK_MEMv_IMMb_DEFINED

#define XED_IFORM_BTR_LOCK_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_BTR_MEMv_GPRv_DEFINED

#define XED_IFORM_BTR_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_BTR_MEMv_IMMb_DEFINED

#define XED_IFORM_BTR_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_BTS_GPRv_GPRv_DEFINED

#define XED_IFORM_BTS_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_BTS_GPRv_IMMb_DEFINED

#define XED_IFORM_BTS_GPRv_IMMb_DEFINED   1

◆ XED_IFORM_BTS_LOCK_MEMv_GPRv_DEFINED

#define XED_IFORM_BTS_LOCK_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_BTS_LOCK_MEMv_IMMb_DEFINED

#define XED_IFORM_BTS_LOCK_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_BTS_MEMv_GPRv_DEFINED

#define XED_IFORM_BTS_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_BTS_MEMv_IMMb_DEFINED

#define XED_IFORM_BTS_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_BZHI_GPR32d_GPR32d_GPR32d_DEFINED

#define XED_IFORM_BZHI_GPR32d_GPR32d_GPR32d_DEFINED   1

◆ XED_IFORM_BZHI_GPR32d_MEMd_GPR32d_DEFINED

#define XED_IFORM_BZHI_GPR32d_MEMd_GPR32d_DEFINED   1

◆ XED_IFORM_BZHI_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED

#define XED_IFORM_BZHI_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED   1

◆ XED_IFORM_BZHI_GPR32i32_MEMi32_GPR32i32_APX_DEFINED

#define XED_IFORM_BZHI_GPR32i32_MEMi32_GPR32i32_APX_DEFINED   1

◆ XED_IFORM_BZHI_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED

#define XED_IFORM_BZHI_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED   1

◆ XED_IFORM_BZHI_GPR64i64_MEMi64_GPR64i64_APX_DEFINED

#define XED_IFORM_BZHI_GPR64i64_MEMi64_GPR64i64_APX_DEFINED   1

◆ XED_IFORM_BZHI_GPR64q_GPR64q_GPR64q_DEFINED

#define XED_IFORM_BZHI_GPR64q_GPR64q_GPR64q_DEFINED   1

◆ XED_IFORM_BZHI_GPR64q_MEMq_GPR64q_DEFINED

#define XED_IFORM_BZHI_GPR64q_MEMq_GPR64q_DEFINED   1

◆ XED_IFORM_CALL_FAR_MEMp2_DEFINED

#define XED_IFORM_CALL_FAR_MEMp2_DEFINED   1

◆ XED_IFORM_CALL_FAR_PTRp_IMMw_DEFINED

#define XED_IFORM_CALL_FAR_PTRp_IMMw_DEFINED   1

◆ XED_IFORM_CALL_NEAR_GPRv_DEFINED

#define XED_IFORM_CALL_NEAR_GPRv_DEFINED   1

◆ XED_IFORM_CALL_NEAR_MEMv_DEFINED

#define XED_IFORM_CALL_NEAR_MEMv_DEFINED   1

◆ XED_IFORM_CALL_NEAR_RELBRd_DEFINED

#define XED_IFORM_CALL_NEAR_RELBRd_DEFINED   1

◆ XED_IFORM_CALL_NEAR_RELBRz_DEFINED

#define XED_IFORM_CALL_NEAR_RELBRz_DEFINED   1

◆ XED_IFORM_CBW_DEFINED

#define XED_IFORM_CBW_DEFINED   1

◆ XED_IFORM_CCMPB_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPB_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPB_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPB_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPB_GPR8i8_MEMi8_DFV_APX_DEFINED

#define XED_IFORM_CCMPB_GPR8i8_MEMi8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPB_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPB_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPB_GPRv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPB_GPRv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPB_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPB_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPB_GPRv_MEMv_DFV_APX_DEFINED

#define XED_IFORM_CCMPB_GPRv_MEMv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPB_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPB_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPB_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPB_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPB_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPB_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPB_MEMv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPB_MEMv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPB_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPB_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPBE_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPBE_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPBE_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPBE_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPBE_GPR8i8_MEMi8_DFV_APX_DEFINED

#define XED_IFORM_CCMPBE_GPR8i8_MEMi8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPBE_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPBE_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPBE_GPRv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPBE_GPRv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPBE_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPBE_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPBE_GPRv_MEMv_DFV_APX_DEFINED

#define XED_IFORM_CCMPBE_GPRv_MEMv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPBE_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPBE_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPBE_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPBE_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPBE_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPBE_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPBE_MEMv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPBE_MEMv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPBE_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPBE_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPF_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPF_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPF_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPF_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPF_GPR8i8_MEMi8_DFV_APX_DEFINED

#define XED_IFORM_CCMPF_GPR8i8_MEMi8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPF_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPF_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPF_GPRv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPF_GPRv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPF_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPF_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPF_GPRv_MEMv_DFV_APX_DEFINED

#define XED_IFORM_CCMPF_GPRv_MEMv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPF_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPF_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPF_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPF_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPF_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPF_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPF_MEMv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPF_MEMv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPF_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPF_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPL_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPL_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPL_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPL_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPL_GPR8i8_MEMi8_DFV_APX_DEFINED

#define XED_IFORM_CCMPL_GPR8i8_MEMi8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPL_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPL_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPL_GPRv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPL_GPRv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPL_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPL_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPL_GPRv_MEMv_DFV_APX_DEFINED

#define XED_IFORM_CCMPL_GPRv_MEMv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPL_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPL_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPL_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPL_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPL_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPL_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPL_MEMv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPL_MEMv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPL_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPL_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPLE_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPLE_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPLE_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPLE_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPLE_GPR8i8_MEMi8_DFV_APX_DEFINED

#define XED_IFORM_CCMPLE_GPR8i8_MEMi8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPLE_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPLE_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPLE_GPRv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPLE_GPRv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPLE_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPLE_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPLE_GPRv_MEMv_DFV_APX_DEFINED

#define XED_IFORM_CCMPLE_GPRv_MEMv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPLE_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPLE_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPLE_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPLE_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPLE_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPLE_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPLE_MEMv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPLE_MEMv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPLE_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPLE_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNB_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNB_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNB_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNB_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNB_GPR8i8_MEMi8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNB_GPR8i8_MEMi8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNB_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPNB_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNB_GPRv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNB_GPRv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNB_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPNB_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNB_GPRv_MEMv_DFV_APX_DEFINED

#define XED_IFORM_CCMPNB_GPRv_MEMv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNB_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNB_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNB_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNB_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNB_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPNB_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNB_MEMv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNB_MEMv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNB_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPNB_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNBE_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNBE_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNBE_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNBE_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNBE_GPR8i8_MEMi8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNBE_GPR8i8_MEMi8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNBE_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPNBE_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNBE_GPRv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNBE_GPRv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNBE_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPNBE_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNBE_GPRv_MEMv_DFV_APX_DEFINED

#define XED_IFORM_CCMPNBE_GPRv_MEMv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNBE_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNBE_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNBE_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNBE_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNBE_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPNBE_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNBE_MEMv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNBE_MEMv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNBE_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPNBE_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNL_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNL_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNL_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNL_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNL_GPR8i8_MEMi8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNL_GPR8i8_MEMi8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNL_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPNL_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNL_GPRv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNL_GPRv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNL_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPNL_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNL_GPRv_MEMv_DFV_APX_DEFINED

#define XED_IFORM_CCMPNL_GPRv_MEMv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNL_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNL_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNL_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNL_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNL_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPNL_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNL_MEMv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNL_MEMv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNL_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPNL_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNLE_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNLE_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNLE_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNLE_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNLE_GPR8i8_MEMi8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNLE_GPR8i8_MEMi8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNLE_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPNLE_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNLE_GPRv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNLE_GPRv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNLE_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPNLE_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNLE_GPRv_MEMv_DFV_APX_DEFINED

#define XED_IFORM_CCMPNLE_GPRv_MEMv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNLE_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNLE_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNLE_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNLE_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNLE_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPNLE_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNLE_MEMv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNLE_MEMv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNLE_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPNLE_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNO_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNO_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNO_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNO_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNO_GPR8i8_MEMi8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNO_GPR8i8_MEMi8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNO_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPNO_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNO_GPRv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNO_GPRv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNO_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPNO_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNO_GPRv_MEMv_DFV_APX_DEFINED

#define XED_IFORM_CCMPNO_GPRv_MEMv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNO_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNO_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNO_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNO_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNO_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPNO_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNO_MEMv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNO_MEMv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNO_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPNO_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNS_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNS_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNS_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNS_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNS_GPR8i8_MEMi8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNS_GPR8i8_MEMi8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNS_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPNS_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNS_GPRv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNS_GPRv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNS_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPNS_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNS_GPRv_MEMv_DFV_APX_DEFINED

#define XED_IFORM_CCMPNS_GPRv_MEMv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNS_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNS_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNS_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNS_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNS_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPNS_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNS_MEMv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNS_MEMv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNS_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPNS_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNZ_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNZ_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNZ_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNZ_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNZ_GPR8i8_MEMi8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNZ_GPR8i8_MEMi8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNZ_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPNZ_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNZ_GPRv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNZ_GPRv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNZ_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPNZ_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNZ_GPRv_MEMv_DFV_APX_DEFINED

#define XED_IFORM_CCMPNZ_GPRv_MEMv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNZ_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNZ_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNZ_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNZ_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNZ_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPNZ_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNZ_MEMv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPNZ_MEMv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPNZ_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPNZ_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPO_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPO_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPO_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPO_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPO_GPR8i8_MEMi8_DFV_APX_DEFINED

#define XED_IFORM_CCMPO_GPR8i8_MEMi8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPO_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPO_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPO_GPRv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPO_GPRv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPO_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPO_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPO_GPRv_MEMv_DFV_APX_DEFINED

#define XED_IFORM_CCMPO_GPRv_MEMv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPO_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPO_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPO_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPO_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPO_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPO_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPO_MEMv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPO_MEMv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPO_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPO_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPS_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPS_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPS_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPS_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPS_GPR8i8_MEMi8_DFV_APX_DEFINED

#define XED_IFORM_CCMPS_GPR8i8_MEMi8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPS_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPS_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPS_GPRv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPS_GPRv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPS_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPS_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPS_GPRv_MEMv_DFV_APX_DEFINED

#define XED_IFORM_CCMPS_GPRv_MEMv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPS_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPS_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPS_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPS_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPS_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPS_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPS_MEMv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPS_MEMv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPS_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPS_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPT_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPT_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPT_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPT_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPT_GPR8i8_MEMi8_DFV_APX_DEFINED

#define XED_IFORM_CCMPT_GPR8i8_MEMi8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPT_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPT_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPT_GPRv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPT_GPRv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPT_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPT_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPT_GPRv_MEMv_DFV_APX_DEFINED

#define XED_IFORM_CCMPT_GPRv_MEMv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPT_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPT_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPT_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPT_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPT_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPT_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPT_MEMv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPT_MEMv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPT_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPT_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPZ_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPZ_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPZ_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPZ_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPZ_GPR8i8_MEMi8_DFV_APX_DEFINED

#define XED_IFORM_CCMPZ_GPR8i8_MEMi8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPZ_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPZ_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPZ_GPRv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPZ_GPRv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPZ_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPZ_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPZ_GPRv_MEMv_DFV_APX_DEFINED

#define XED_IFORM_CCMPZ_GPRv_MEMv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPZ_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CCMPZ_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPZ_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPZ_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPZ_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CCMPZ_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPZ_MEMv_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CCMPZ_MEMv_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CCMPZ_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CCMPZ_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CDQ_DEFINED

#define XED_IFORM_CDQ_DEFINED   1

◆ XED_IFORM_CDQE_DEFINED

#define XED_IFORM_CDQE_DEFINED   1

◆ XED_IFORM_CFCMOVB_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVB_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVB_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVB_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVB_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVB_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVB_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVB_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVB_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVB_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVBE_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVBE_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVBE_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVBE_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVBE_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVBE_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVBE_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVBE_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVBE_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVBE_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVL_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVL_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVL_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVL_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVL_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVL_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVL_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVL_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVL_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVL_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVLE_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVLE_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVLE_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVLE_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVLE_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVLE_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVLE_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVLE_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVLE_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVLE_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNB_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVNB_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNB_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVNB_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNB_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVNB_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNB_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVNB_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNB_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVNB_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNBE_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVNBE_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNBE_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVNBE_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNBE_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVNBE_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNBE_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVNBE_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNBE_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVNBE_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNL_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVNL_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNL_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVNL_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNL_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVNL_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNL_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVNL_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNL_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVNL_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNLE_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVNLE_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNLE_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVNLE_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNLE_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVNLE_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNLE_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVNLE_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNLE_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVNLE_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNO_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVNO_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNO_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVNO_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNO_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVNO_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNO_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVNO_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNO_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVNO_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNP_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVNP_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNP_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVNP_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNP_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVNP_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNP_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVNP_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNP_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVNP_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNS_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVNS_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNS_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVNS_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNS_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVNS_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNS_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVNS_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNS_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVNS_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNZ_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVNZ_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNZ_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVNZ_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNZ_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVNZ_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNZ_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVNZ_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVNZ_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVNZ_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVO_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVO_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVO_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVO_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVO_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVO_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVO_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVO_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVO_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVO_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVP_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVP_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVP_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVP_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVP_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVP_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVP_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVP_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVP_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVP_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVS_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVS_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVS_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVS_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVS_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVS_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVS_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVS_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVS_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVS_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVZ_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVZ_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVZ_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVZ_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVZ_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVZ_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVZ_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CFCMOVZ_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CFCMOVZ_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_CFCMOVZ_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CLAC_DEFINED

#define XED_IFORM_CLAC_DEFINED   1

◆ XED_IFORM_CLC_DEFINED

#define XED_IFORM_CLC_DEFINED   1

◆ XED_IFORM_CLD_DEFINED

#define XED_IFORM_CLD_DEFINED   1

◆ XED_IFORM_CLDEMOTE_MEMu8_DEFINED

#define XED_IFORM_CLDEMOTE_MEMu8_DEFINED   1

◆ XED_IFORM_CLFLUSH_MEMmprefetch_DEFINED

#define XED_IFORM_CLFLUSH_MEMmprefetch_DEFINED   1

◆ XED_IFORM_CLFLUSHOPT_MEMmprefetch_DEFINED

#define XED_IFORM_CLFLUSHOPT_MEMmprefetch_DEFINED   1

◆ XED_IFORM_CLGI_DEFINED

#define XED_IFORM_CLGI_DEFINED   1

◆ XED_IFORM_CLI_DEFINED

#define XED_IFORM_CLI_DEFINED   1

◆ XED_IFORM_CLRSSBSY_MEMu64_DEFINED

#define XED_IFORM_CLRSSBSY_MEMu64_DEFINED   1

◆ XED_IFORM_CLTS_DEFINED

#define XED_IFORM_CLTS_DEFINED   1

◆ XED_IFORM_CLUI_DEFINED

#define XED_IFORM_CLUI_DEFINED   1

◆ XED_IFORM_CLWB_MEMmprefetch_DEFINED

#define XED_IFORM_CLWB_MEMmprefetch_DEFINED   1

◆ XED_IFORM_CLZERO_DEFINED

#define XED_IFORM_CLZERO_DEFINED   1

◆ XED_IFORM_CMC_DEFINED

#define XED_IFORM_CMC_DEFINED   1

◆ XED_IFORM_CMOVB_GPRv_GPRv_DEFINED

#define XED_IFORM_CMOVB_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_CMOVB_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CMOVB_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CMOVB_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CMOVB_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CMOVB_GPRv_MEMv_DEFINED

#define XED_IFORM_CMOVB_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_CMOVBE_GPRv_GPRv_DEFINED

#define XED_IFORM_CMOVBE_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_CMOVBE_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CMOVBE_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CMOVBE_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CMOVBE_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CMOVBE_GPRv_MEMv_DEFINED

#define XED_IFORM_CMOVBE_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_CMOVL_GPRv_GPRv_DEFINED

#define XED_IFORM_CMOVL_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_CMOVL_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CMOVL_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CMOVL_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CMOVL_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CMOVL_GPRv_MEMv_DEFINED

#define XED_IFORM_CMOVL_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_CMOVLE_GPRv_GPRv_DEFINED

#define XED_IFORM_CMOVLE_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_CMOVLE_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CMOVLE_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CMOVLE_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CMOVLE_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CMOVLE_GPRv_MEMv_DEFINED

#define XED_IFORM_CMOVLE_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_CMOVNB_GPRv_GPRv_DEFINED

#define XED_IFORM_CMOVNB_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_CMOVNB_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CMOVNB_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CMOVNB_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CMOVNB_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CMOVNB_GPRv_MEMv_DEFINED

#define XED_IFORM_CMOVNB_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_CMOVNBE_GPRv_GPRv_DEFINED

#define XED_IFORM_CMOVNBE_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_CMOVNBE_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CMOVNBE_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CMOVNBE_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CMOVNBE_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CMOVNBE_GPRv_MEMv_DEFINED

#define XED_IFORM_CMOVNBE_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_CMOVNL_GPRv_GPRv_DEFINED

#define XED_IFORM_CMOVNL_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_CMOVNL_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CMOVNL_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CMOVNL_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CMOVNL_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CMOVNL_GPRv_MEMv_DEFINED

#define XED_IFORM_CMOVNL_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_CMOVNLE_GPRv_GPRv_DEFINED

#define XED_IFORM_CMOVNLE_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_CMOVNLE_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CMOVNLE_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CMOVNLE_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CMOVNLE_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CMOVNLE_GPRv_MEMv_DEFINED

#define XED_IFORM_CMOVNLE_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_CMOVNO_GPRv_GPRv_DEFINED

#define XED_IFORM_CMOVNO_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_CMOVNO_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CMOVNO_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CMOVNO_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CMOVNO_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CMOVNO_GPRv_MEMv_DEFINED

#define XED_IFORM_CMOVNO_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_CMOVNP_GPRv_GPRv_DEFINED

#define XED_IFORM_CMOVNP_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_CMOVNP_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CMOVNP_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CMOVNP_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CMOVNP_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CMOVNP_GPRv_MEMv_DEFINED

#define XED_IFORM_CMOVNP_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_CMOVNS_GPRv_GPRv_DEFINED

#define XED_IFORM_CMOVNS_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_CMOVNS_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CMOVNS_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CMOVNS_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CMOVNS_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CMOVNS_GPRv_MEMv_DEFINED

#define XED_IFORM_CMOVNS_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_CMOVNZ_GPRv_GPRv_DEFINED

#define XED_IFORM_CMOVNZ_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_CMOVNZ_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CMOVNZ_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CMOVNZ_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CMOVNZ_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CMOVNZ_GPRv_MEMv_DEFINED

#define XED_IFORM_CMOVNZ_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_CMOVO_GPRv_GPRv_DEFINED

#define XED_IFORM_CMOVO_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_CMOVO_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CMOVO_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CMOVO_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CMOVO_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CMOVO_GPRv_MEMv_DEFINED

#define XED_IFORM_CMOVO_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_CMOVP_GPRv_GPRv_DEFINED

#define XED_IFORM_CMOVP_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_CMOVP_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CMOVP_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CMOVP_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CMOVP_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CMOVP_GPRv_MEMv_DEFINED

#define XED_IFORM_CMOVP_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_CMOVS_GPRv_GPRv_DEFINED

#define XED_IFORM_CMOVS_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_CMOVS_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CMOVS_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CMOVS_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CMOVS_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CMOVS_GPRv_MEMv_DEFINED

#define XED_IFORM_CMOVS_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_CMOVZ_GPRv_GPRv_DEFINED

#define XED_IFORM_CMOVZ_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_CMOVZ_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_CMOVZ_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_CMOVZ_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_CMOVZ_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_CMOVZ_GPRv_MEMv_DEFINED

#define XED_IFORM_CMOVZ_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_CMP_AL_IMMb_DEFINED

#define XED_IFORM_CMP_AL_IMMb_DEFINED   1

◆ XED_IFORM_CMP_GPR8_GPR8_38_DEFINED

#define XED_IFORM_CMP_GPR8_GPR8_38_DEFINED   1

◆ XED_IFORM_CMP_GPR8_GPR8_3A_DEFINED

#define XED_IFORM_CMP_GPR8_GPR8_3A_DEFINED   1

◆ XED_IFORM_CMP_GPR8_IMMb_80r7_DEFINED

#define XED_IFORM_CMP_GPR8_IMMb_80r7_DEFINED   1

◆ XED_IFORM_CMP_GPR8_IMMb_82r7_DEFINED

#define XED_IFORM_CMP_GPR8_IMMb_82r7_DEFINED   1

◆ XED_IFORM_CMP_GPR8_MEMb_DEFINED

#define XED_IFORM_CMP_GPR8_MEMb_DEFINED   1

◆ XED_IFORM_CMP_GPRv_GPRv_39_DEFINED

#define XED_IFORM_CMP_GPRv_GPRv_39_DEFINED   1

◆ XED_IFORM_CMP_GPRv_GPRv_3B_DEFINED

#define XED_IFORM_CMP_GPRv_GPRv_3B_DEFINED   1

◆ XED_IFORM_CMP_GPRv_IMMb_DEFINED

#define XED_IFORM_CMP_GPRv_IMMb_DEFINED   1

◆ XED_IFORM_CMP_GPRv_IMMz_DEFINED

#define XED_IFORM_CMP_GPRv_IMMz_DEFINED   1

◆ XED_IFORM_CMP_GPRv_MEMv_DEFINED

#define XED_IFORM_CMP_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_CMP_MEMb_GPR8_DEFINED

#define XED_IFORM_CMP_MEMb_GPR8_DEFINED   1

◆ XED_IFORM_CMP_MEMb_IMMb_80r7_DEFINED

#define XED_IFORM_CMP_MEMb_IMMb_80r7_DEFINED   1

◆ XED_IFORM_CMP_MEMb_IMMb_82r7_DEFINED

#define XED_IFORM_CMP_MEMb_IMMb_82r7_DEFINED   1

◆ XED_IFORM_CMP_MEMv_GPRv_DEFINED

#define XED_IFORM_CMP_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_CMP_MEMv_IMMb_DEFINED

#define XED_IFORM_CMP_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_CMP_MEMv_IMMz_DEFINED

#define XED_IFORM_CMP_MEMv_IMMz_DEFINED   1

◆ XED_IFORM_CMP_OrAX_IMMz_DEFINED

#define XED_IFORM_CMP_OrAX_IMMz_DEFINED   1

◆ XED_IFORM_CMPBEXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED

#define XED_IFORM_CMPBEXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1

◆ XED_IFORM_CMPBEXADD_MEMu32_GPR32u32_GPR32u32_DEFINED

#define XED_IFORM_CMPBEXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1

◆ XED_IFORM_CMPBEXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED

#define XED_IFORM_CMPBEXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1

◆ XED_IFORM_CMPBEXADD_MEMu64_GPR64u64_GPR64u64_DEFINED

#define XED_IFORM_CMPBEXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1

◆ XED_IFORM_CMPBXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED

#define XED_IFORM_CMPBXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1

◆ XED_IFORM_CMPBXADD_MEMu32_GPR32u32_GPR32u32_DEFINED

#define XED_IFORM_CMPBXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1

◆ XED_IFORM_CMPBXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED

#define XED_IFORM_CMPBXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1

◆ XED_IFORM_CMPBXADD_MEMu64_GPR64u64_GPR64u64_DEFINED

#define XED_IFORM_CMPBXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1

◆ XED_IFORM_CMPLEXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED

#define XED_IFORM_CMPLEXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1

◆ XED_IFORM_CMPLEXADD_MEMu32_GPR32u32_GPR32u32_DEFINED

#define XED_IFORM_CMPLEXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1

◆ XED_IFORM_CMPLEXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED

#define XED_IFORM_CMPLEXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1

◆ XED_IFORM_CMPLEXADD_MEMu64_GPR64u64_GPR64u64_DEFINED

#define XED_IFORM_CMPLEXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1

◆ XED_IFORM_CMPLXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED

#define XED_IFORM_CMPLXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1

◆ XED_IFORM_CMPLXADD_MEMu32_GPR32u32_GPR32u32_DEFINED

#define XED_IFORM_CMPLXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1

◆ XED_IFORM_CMPLXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED

#define XED_IFORM_CMPLXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1

◆ XED_IFORM_CMPLXADD_MEMu64_GPR64u64_GPR64u64_DEFINED

#define XED_IFORM_CMPLXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1

◆ XED_IFORM_CMPNBEXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED

#define XED_IFORM_CMPNBEXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1

◆ XED_IFORM_CMPNBEXADD_MEMu32_GPR32u32_GPR32u32_DEFINED

#define XED_IFORM_CMPNBEXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1

◆ XED_IFORM_CMPNBEXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED

#define XED_IFORM_CMPNBEXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1

◆ XED_IFORM_CMPNBEXADD_MEMu64_GPR64u64_GPR64u64_DEFINED

#define XED_IFORM_CMPNBEXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1

◆ XED_IFORM_CMPNBXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED

#define XED_IFORM_CMPNBXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1

◆ XED_IFORM_CMPNBXADD_MEMu32_GPR32u32_GPR32u32_DEFINED

#define XED_IFORM_CMPNBXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1

◆ XED_IFORM_CMPNBXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED

#define XED_IFORM_CMPNBXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1

◆ XED_IFORM_CMPNBXADD_MEMu64_GPR64u64_GPR64u64_DEFINED

#define XED_IFORM_CMPNBXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1

◆ XED_IFORM_CMPNLEXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED

#define XED_IFORM_CMPNLEXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1

◆ XED_IFORM_CMPNLEXADD_MEMu32_GPR32u32_GPR32u32_DEFINED

#define XED_IFORM_CMPNLEXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1

◆ XED_IFORM_CMPNLEXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED

#define XED_IFORM_CMPNLEXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1

◆ XED_IFORM_CMPNLEXADD_MEMu64_GPR64u64_GPR64u64_DEFINED

#define XED_IFORM_CMPNLEXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1

◆ XED_IFORM_CMPNLXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED

#define XED_IFORM_CMPNLXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1

◆ XED_IFORM_CMPNLXADD_MEMu32_GPR32u32_GPR32u32_DEFINED

#define XED_IFORM_CMPNLXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1

◆ XED_IFORM_CMPNLXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED

#define XED_IFORM_CMPNLXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1

◆ XED_IFORM_CMPNLXADD_MEMu64_GPR64u64_GPR64u64_DEFINED

#define XED_IFORM_CMPNLXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1

◆ XED_IFORM_CMPNOXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED

#define XED_IFORM_CMPNOXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1

◆ XED_IFORM_CMPNOXADD_MEMu32_GPR32u32_GPR32u32_DEFINED

#define XED_IFORM_CMPNOXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1

◆ XED_IFORM_CMPNOXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED

#define XED_IFORM_CMPNOXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1

◆ XED_IFORM_CMPNOXADD_MEMu64_GPR64u64_GPR64u64_DEFINED

#define XED_IFORM_CMPNOXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1

◆ XED_IFORM_CMPNPXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED

#define XED_IFORM_CMPNPXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1

◆ XED_IFORM_CMPNPXADD_MEMu32_GPR32u32_GPR32u32_DEFINED

#define XED_IFORM_CMPNPXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1

◆ XED_IFORM_CMPNPXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED

#define XED_IFORM_CMPNPXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1

◆ XED_IFORM_CMPNPXADD_MEMu64_GPR64u64_GPR64u64_DEFINED

#define XED_IFORM_CMPNPXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1

◆ XED_IFORM_CMPNSXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED

#define XED_IFORM_CMPNSXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1

◆ XED_IFORM_CMPNSXADD_MEMu32_GPR32u32_GPR32u32_DEFINED

#define XED_IFORM_CMPNSXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1

◆ XED_IFORM_CMPNSXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED

#define XED_IFORM_CMPNSXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1

◆ XED_IFORM_CMPNSXADD_MEMu64_GPR64u64_GPR64u64_DEFINED

#define XED_IFORM_CMPNSXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1

◆ XED_IFORM_CMPNZXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED

#define XED_IFORM_CMPNZXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1

◆ XED_IFORM_CMPNZXADD_MEMu32_GPR32u32_GPR32u32_DEFINED

#define XED_IFORM_CMPNZXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1

◆ XED_IFORM_CMPNZXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED

#define XED_IFORM_CMPNZXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1

◆ XED_IFORM_CMPNZXADD_MEMu64_GPR64u64_GPR64u64_DEFINED

#define XED_IFORM_CMPNZXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1

◆ XED_IFORM_CMPOXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED

#define XED_IFORM_CMPOXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1

◆ XED_IFORM_CMPOXADD_MEMu32_GPR32u32_GPR32u32_DEFINED

#define XED_IFORM_CMPOXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1

◆ XED_IFORM_CMPOXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED

#define XED_IFORM_CMPOXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1

◆ XED_IFORM_CMPOXADD_MEMu64_GPR64u64_GPR64u64_DEFINED

#define XED_IFORM_CMPOXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1

◆ XED_IFORM_CMPPD_XMMpd_MEMpd_IMMb_DEFINED

#define XED_IFORM_CMPPD_XMMpd_MEMpd_IMMb_DEFINED   1

◆ XED_IFORM_CMPPD_XMMpd_XMMpd_IMMb_DEFINED

#define XED_IFORM_CMPPD_XMMpd_XMMpd_IMMb_DEFINED   1

◆ XED_IFORM_CMPPS_XMMps_MEMps_IMMb_DEFINED

#define XED_IFORM_CMPPS_XMMps_MEMps_IMMb_DEFINED   1

◆ XED_IFORM_CMPPS_XMMps_XMMps_IMMb_DEFINED

#define XED_IFORM_CMPPS_XMMps_XMMps_IMMb_DEFINED   1

◆ XED_IFORM_CMPPXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED

#define XED_IFORM_CMPPXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1

◆ XED_IFORM_CMPPXADD_MEMu32_GPR32u32_GPR32u32_DEFINED

#define XED_IFORM_CMPPXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1

◆ XED_IFORM_CMPPXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED

#define XED_IFORM_CMPPXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1

◆ XED_IFORM_CMPPXADD_MEMu64_GPR64u64_GPR64u64_DEFINED

#define XED_IFORM_CMPPXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1

◆ XED_IFORM_CMPSB_DEFINED

#define XED_IFORM_CMPSB_DEFINED   1

◆ XED_IFORM_CMPSD_DEFINED

#define XED_IFORM_CMPSD_DEFINED   1

◆ XED_IFORM_CMPSD_XMM_XMMsd_MEMsd_IMMb_DEFINED

#define XED_IFORM_CMPSD_XMM_XMMsd_MEMsd_IMMb_DEFINED   1

◆ XED_IFORM_CMPSD_XMM_XMMsd_XMMsd_IMMb_DEFINED

#define XED_IFORM_CMPSD_XMM_XMMsd_XMMsd_IMMb_DEFINED   1

◆ XED_IFORM_CMPSQ_DEFINED

#define XED_IFORM_CMPSQ_DEFINED   1

◆ XED_IFORM_CMPSS_XMMss_MEMss_IMMb_DEFINED

#define XED_IFORM_CMPSS_XMMss_MEMss_IMMb_DEFINED   1

◆ XED_IFORM_CMPSS_XMMss_XMMss_IMMb_DEFINED

#define XED_IFORM_CMPSS_XMMss_XMMss_IMMb_DEFINED   1

◆ XED_IFORM_CMPSW_DEFINED

#define XED_IFORM_CMPSW_DEFINED   1

◆ XED_IFORM_CMPSXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED

#define XED_IFORM_CMPSXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1

◆ XED_IFORM_CMPSXADD_MEMu32_GPR32u32_GPR32u32_DEFINED

#define XED_IFORM_CMPSXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1

◆ XED_IFORM_CMPSXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED

#define XED_IFORM_CMPSXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1

◆ XED_IFORM_CMPSXADD_MEMu64_GPR64u64_GPR64u64_DEFINED

#define XED_IFORM_CMPSXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1

◆ XED_IFORM_CMPXCHG16B_LOCK_MEMdq_DEFINED

#define XED_IFORM_CMPXCHG16B_LOCK_MEMdq_DEFINED   1

◆ XED_IFORM_CMPXCHG16B_MEMdq_DEFINED

#define XED_IFORM_CMPXCHG16B_MEMdq_DEFINED   1

◆ XED_IFORM_CMPXCHG8B_LOCK_MEMq_DEFINED

#define XED_IFORM_CMPXCHG8B_LOCK_MEMq_DEFINED   1

◆ XED_IFORM_CMPXCHG8B_MEMq_DEFINED

#define XED_IFORM_CMPXCHG8B_MEMq_DEFINED   1

◆ XED_IFORM_CMPXCHG_GPR8_GPR8_DEFINED

#define XED_IFORM_CMPXCHG_GPR8_GPR8_DEFINED   1

◆ XED_IFORM_CMPXCHG_GPRv_GPRv_DEFINED

#define XED_IFORM_CMPXCHG_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_CMPXCHG_LOCK_MEMb_GPR8_DEFINED

#define XED_IFORM_CMPXCHG_LOCK_MEMb_GPR8_DEFINED   1

◆ XED_IFORM_CMPXCHG_LOCK_MEMv_GPRv_DEFINED

#define XED_IFORM_CMPXCHG_LOCK_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_CMPXCHG_MEMb_GPR8_DEFINED

#define XED_IFORM_CMPXCHG_MEMb_GPR8_DEFINED   1

◆ XED_IFORM_CMPXCHG_MEMv_GPRv_DEFINED

#define XED_IFORM_CMPXCHG_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_CMPZXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED

#define XED_IFORM_CMPZXADD_MEMu32_GPR32u32_GPR32u32_APX_DEFINED   1

◆ XED_IFORM_CMPZXADD_MEMu32_GPR32u32_GPR32u32_DEFINED

#define XED_IFORM_CMPZXADD_MEMu32_GPR32u32_GPR32u32_DEFINED   1

◆ XED_IFORM_CMPZXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED

#define XED_IFORM_CMPZXADD_MEMu64_GPR64u64_GPR64u64_APX_DEFINED   1

◆ XED_IFORM_CMPZXADD_MEMu64_GPR64u64_GPR64u64_DEFINED

#define XED_IFORM_CMPZXADD_MEMu64_GPR64u64_GPR64u64_DEFINED   1

◆ XED_IFORM_COMISD_XMMsd_MEMsd_DEFINED

#define XED_IFORM_COMISD_XMMsd_MEMsd_DEFINED   1

◆ XED_IFORM_COMISD_XMMsd_XMMsd_DEFINED

#define XED_IFORM_COMISD_XMMsd_XMMsd_DEFINED   1

◆ XED_IFORM_COMISS_XMMss_MEMss_DEFINED

#define XED_IFORM_COMISS_XMMss_MEMss_DEFINED   1

◆ XED_IFORM_COMISS_XMMss_XMMss_DEFINED

#define XED_IFORM_COMISS_XMMss_XMMss_DEFINED   1

◆ XED_IFORM_CPUID_DEFINED

#define XED_IFORM_CPUID_DEFINED   1

◆ XED_IFORM_CQO_DEFINED

#define XED_IFORM_CQO_DEFINED   1

◆ XED_IFORM_CRC32_GPRy_GPR8i8_APX_DEFINED

#define XED_IFORM_CRC32_GPRy_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_CRC32_GPRy_GPRv_APX_DEFINED

#define XED_IFORM_CRC32_GPRy_GPRv_APX_DEFINED   1

◆ XED_IFORM_CRC32_GPRy_MEMi8_APX_DEFINED

#define XED_IFORM_CRC32_GPRy_MEMi8_APX_DEFINED   1

◆ XED_IFORM_CRC32_GPRy_MEMv_APX_DEFINED

#define XED_IFORM_CRC32_GPRy_MEMv_APX_DEFINED   1

◆ XED_IFORM_CRC32_GPRyy_GPR8b_DEFINED

#define XED_IFORM_CRC32_GPRyy_GPR8b_DEFINED   1

◆ XED_IFORM_CRC32_GPRyy_GPRv_DEFINED

#define XED_IFORM_CRC32_GPRyy_GPRv_DEFINED   1

◆ XED_IFORM_CRC32_GPRyy_MEMb_DEFINED

#define XED_IFORM_CRC32_GPRyy_MEMb_DEFINED   1

◆ XED_IFORM_CRC32_GPRyy_MEMv_DEFINED

#define XED_IFORM_CRC32_GPRyy_MEMv_DEFINED   1

◆ XED_IFORM_CTESTB_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTB_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTB_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTB_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTB_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTB_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTB_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTB_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTB_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTB_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTB_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTB_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTB_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTB_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTB_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTB_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTBE_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTBE_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTBE_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTBE_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTBE_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTBE_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTBE_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTBE_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTBE_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTBE_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTBE_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTBE_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTBE_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTBE_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTBE_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTBE_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTF_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTF_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTF_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTF_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTF_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTF_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTF_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTF_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTF_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTF_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTF_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTF_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTF_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTF_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTF_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTF_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTL_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTL_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTL_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTL_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTL_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTL_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTL_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTL_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTL_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTL_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTL_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTL_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTL_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTL_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTL_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTL_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTLE_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTLE_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTLE_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTLE_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTLE_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTLE_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTLE_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTLE_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTLE_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTLE_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTLE_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTLE_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTLE_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTLE_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTLE_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTLE_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNB_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTNB_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNB_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTNB_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNB_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTNB_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNB_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTNB_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNB_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTNB_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNB_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTNB_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNB_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTNB_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNB_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTNB_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNBE_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTNBE_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNBE_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTNBE_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNBE_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTNBE_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNBE_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTNBE_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNBE_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTNBE_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNBE_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTNBE_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNBE_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTNBE_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNBE_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTNBE_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNL_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTNL_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNL_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTNL_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNL_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTNL_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNL_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTNL_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNL_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTNL_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNL_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTNL_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNL_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTNL_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNL_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTNL_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNLE_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTNLE_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNLE_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTNLE_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNLE_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTNLE_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNLE_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTNLE_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNLE_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTNLE_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNLE_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTNLE_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNLE_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTNLE_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNLE_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTNLE_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNO_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTNO_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNO_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTNO_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNO_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTNO_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNO_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTNO_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNO_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTNO_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNO_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTNO_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNO_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTNO_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNO_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTNO_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNS_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTNS_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNS_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTNS_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNS_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTNS_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNS_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTNS_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNS_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTNS_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNS_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTNS_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNS_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTNS_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNS_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTNS_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNZ_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTNZ_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNZ_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTNZ_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNZ_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTNZ_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNZ_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTNZ_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNZ_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTNZ_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNZ_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTNZ_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNZ_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTNZ_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTNZ_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTNZ_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTO_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTO_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTO_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTO_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTO_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTO_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTO_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTO_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTO_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTO_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTO_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTO_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTO_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTO_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTO_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTO_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTS_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTS_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTS_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTS_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTS_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTS_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTS_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTS_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTS_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTS_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTS_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTS_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTS_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTS_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTS_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTS_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTT_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTT_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTT_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTT_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTT_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTT_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTT_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTT_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTT_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTT_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTT_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTT_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTT_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTT_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTT_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTT_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTZ_GPR8i8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTZ_GPR8i8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTZ_GPR8i8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTZ_GPR8i8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTZ_GPRv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTZ_GPRv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTZ_GPRv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTZ_GPRv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTZ_MEMi8_GPR8i8_DFV_APX_DEFINED

#define XED_IFORM_CTESTZ_MEMi8_GPR8i8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTZ_MEMi8_IMM8_DFV_APX_DEFINED

#define XED_IFORM_CTESTZ_MEMi8_IMM8_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTZ_MEMv_GPRv_DFV_APX_DEFINED

#define XED_IFORM_CTESTZ_MEMv_GPRv_DFV_APX_DEFINED   1

◆ XED_IFORM_CTESTZ_MEMv_IMMz_DFV_APX_DEFINED

#define XED_IFORM_CTESTZ_MEMv_IMMz_DFV_APX_DEFINED   1

◆ XED_IFORM_CVTDQ2PD_XMMpd_MEMq_DEFINED

#define XED_IFORM_CVTDQ2PD_XMMpd_MEMq_DEFINED   1

◆ XED_IFORM_CVTDQ2PD_XMMpd_XMMq_DEFINED

#define XED_IFORM_CVTDQ2PD_XMMpd_XMMq_DEFINED   1

◆ XED_IFORM_CVTDQ2PS_XMMps_MEMdq_DEFINED

#define XED_IFORM_CVTDQ2PS_XMMps_MEMdq_DEFINED   1

◆ XED_IFORM_CVTDQ2PS_XMMps_XMMdq_DEFINED

#define XED_IFORM_CVTDQ2PS_XMMps_XMMdq_DEFINED   1

◆ XED_IFORM_CVTPD2DQ_XMMdq_MEMpd_DEFINED

#define XED_IFORM_CVTPD2DQ_XMMdq_MEMpd_DEFINED   1

◆ XED_IFORM_CVTPD2DQ_XMMdq_XMMpd_DEFINED

#define XED_IFORM_CVTPD2DQ_XMMdq_XMMpd_DEFINED   1

◆ XED_IFORM_CVTPD2PI_MMXq_MEMpd_DEFINED

#define XED_IFORM_CVTPD2PI_MMXq_MEMpd_DEFINED   1

◆ XED_IFORM_CVTPD2PI_MMXq_XMMpd_DEFINED

#define XED_IFORM_CVTPD2PI_MMXq_XMMpd_DEFINED   1

◆ XED_IFORM_CVTPD2PS_XMMps_MEMpd_DEFINED

#define XED_IFORM_CVTPD2PS_XMMps_MEMpd_DEFINED   1

◆ XED_IFORM_CVTPD2PS_XMMps_XMMpd_DEFINED

#define XED_IFORM_CVTPD2PS_XMMps_XMMpd_DEFINED   1

◆ XED_IFORM_CVTPI2PD_XMMpd_MEMq_DEFINED

#define XED_IFORM_CVTPI2PD_XMMpd_MEMq_DEFINED   1

◆ XED_IFORM_CVTPI2PD_XMMpd_MMXq_DEFINED

#define XED_IFORM_CVTPI2PD_XMMpd_MMXq_DEFINED   1

◆ XED_IFORM_CVTPI2PS_XMMq_MEMq_DEFINED

#define XED_IFORM_CVTPI2PS_XMMq_MEMq_DEFINED   1

◆ XED_IFORM_CVTPI2PS_XMMq_MMXq_DEFINED

#define XED_IFORM_CVTPI2PS_XMMq_MMXq_DEFINED   1

◆ XED_IFORM_CVTPS2DQ_XMMdq_MEMps_DEFINED

#define XED_IFORM_CVTPS2DQ_XMMdq_MEMps_DEFINED   1

◆ XED_IFORM_CVTPS2DQ_XMMdq_XMMps_DEFINED

#define XED_IFORM_CVTPS2DQ_XMMdq_XMMps_DEFINED   1

◆ XED_IFORM_CVTPS2PD_XMMpd_MEMq_DEFINED

#define XED_IFORM_CVTPS2PD_XMMpd_MEMq_DEFINED   1

◆ XED_IFORM_CVTPS2PD_XMMpd_XMMq_DEFINED

#define XED_IFORM_CVTPS2PD_XMMpd_XMMq_DEFINED   1

◆ XED_IFORM_CVTPS2PI_MMXq_MEMq_DEFINED

#define XED_IFORM_CVTPS2PI_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_CVTPS2PI_MMXq_XMMq_DEFINED

#define XED_IFORM_CVTPS2PI_MMXq_XMMq_DEFINED   1

◆ XED_IFORM_CVTSD2SI_GPR32d_MEMsd_DEFINED

#define XED_IFORM_CVTSD2SI_GPR32d_MEMsd_DEFINED   1

◆ XED_IFORM_CVTSD2SI_GPR32d_XMMsd_DEFINED

#define XED_IFORM_CVTSD2SI_GPR32d_XMMsd_DEFINED   1

◆ XED_IFORM_CVTSD2SI_GPR64q_MEMsd_DEFINED

#define XED_IFORM_CVTSD2SI_GPR64q_MEMsd_DEFINED   1

◆ XED_IFORM_CVTSD2SI_GPR64q_XMMsd_DEFINED

#define XED_IFORM_CVTSD2SI_GPR64q_XMMsd_DEFINED   1

◆ XED_IFORM_CVTSD2SS_XMMss_MEMsd_DEFINED

#define XED_IFORM_CVTSD2SS_XMMss_MEMsd_DEFINED   1

◆ XED_IFORM_CVTSD2SS_XMMss_XMMsd_DEFINED

#define XED_IFORM_CVTSD2SS_XMMss_XMMsd_DEFINED   1

◆ XED_IFORM_CVTSI2SD_XMMsd_GPR32d_DEFINED

#define XED_IFORM_CVTSI2SD_XMMsd_GPR32d_DEFINED   1

◆ XED_IFORM_CVTSI2SD_XMMsd_GPR64q_DEFINED

#define XED_IFORM_CVTSI2SD_XMMsd_GPR64q_DEFINED   1

◆ XED_IFORM_CVTSI2SD_XMMsd_MEMd_DEFINED

#define XED_IFORM_CVTSI2SD_XMMsd_MEMd_DEFINED   1

◆ XED_IFORM_CVTSI2SD_XMMsd_MEMq_DEFINED

#define XED_IFORM_CVTSI2SD_XMMsd_MEMq_DEFINED   1

◆ XED_IFORM_CVTSI2SS_XMMss_GPR32d_DEFINED

#define XED_IFORM_CVTSI2SS_XMMss_GPR32d_DEFINED   1

◆ XED_IFORM_CVTSI2SS_XMMss_GPR64q_DEFINED

#define XED_IFORM_CVTSI2SS_XMMss_GPR64q_DEFINED   1

◆ XED_IFORM_CVTSI2SS_XMMss_MEMd_DEFINED

#define XED_IFORM_CVTSI2SS_XMMss_MEMd_DEFINED   1

◆ XED_IFORM_CVTSI2SS_XMMss_MEMq_DEFINED

#define XED_IFORM_CVTSI2SS_XMMss_MEMq_DEFINED   1

◆ XED_IFORM_CVTSS2SD_XMMsd_MEMss_DEFINED

#define XED_IFORM_CVTSS2SD_XMMsd_MEMss_DEFINED   1

◆ XED_IFORM_CVTSS2SD_XMMsd_XMMss_DEFINED

#define XED_IFORM_CVTSS2SD_XMMsd_XMMss_DEFINED   1

◆ XED_IFORM_CVTSS2SI_GPR32d_MEMss_DEFINED

#define XED_IFORM_CVTSS2SI_GPR32d_MEMss_DEFINED   1

◆ XED_IFORM_CVTSS2SI_GPR32d_XMMss_DEFINED

#define XED_IFORM_CVTSS2SI_GPR32d_XMMss_DEFINED   1

◆ XED_IFORM_CVTSS2SI_GPR64q_MEMss_DEFINED

#define XED_IFORM_CVTSS2SI_GPR64q_MEMss_DEFINED   1

◆ XED_IFORM_CVTSS2SI_GPR64q_XMMss_DEFINED

#define XED_IFORM_CVTSS2SI_GPR64q_XMMss_DEFINED   1

◆ XED_IFORM_CVTTPD2DQ_XMMdq_MEMpd_DEFINED

#define XED_IFORM_CVTTPD2DQ_XMMdq_MEMpd_DEFINED   1

◆ XED_IFORM_CVTTPD2DQ_XMMdq_XMMpd_DEFINED

#define XED_IFORM_CVTTPD2DQ_XMMdq_XMMpd_DEFINED   1

◆ XED_IFORM_CVTTPD2PI_MMXq_MEMpd_DEFINED

#define XED_IFORM_CVTTPD2PI_MMXq_MEMpd_DEFINED   1

◆ XED_IFORM_CVTTPD2PI_MMXq_XMMpd_DEFINED

#define XED_IFORM_CVTTPD2PI_MMXq_XMMpd_DEFINED   1

◆ XED_IFORM_CVTTPS2DQ_XMMdq_MEMps_DEFINED

#define XED_IFORM_CVTTPS2DQ_XMMdq_MEMps_DEFINED   1

◆ XED_IFORM_CVTTPS2DQ_XMMdq_XMMps_DEFINED

#define XED_IFORM_CVTTPS2DQ_XMMdq_XMMps_DEFINED   1

◆ XED_IFORM_CVTTPS2PI_MMXq_MEMq_DEFINED

#define XED_IFORM_CVTTPS2PI_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_CVTTPS2PI_MMXq_XMMq_DEFINED

#define XED_IFORM_CVTTPS2PI_MMXq_XMMq_DEFINED   1

◆ XED_IFORM_CVTTSD2SI_GPR32d_MEMsd_DEFINED

#define XED_IFORM_CVTTSD2SI_GPR32d_MEMsd_DEFINED   1

◆ XED_IFORM_CVTTSD2SI_GPR32d_XMMsd_DEFINED

#define XED_IFORM_CVTTSD2SI_GPR32d_XMMsd_DEFINED   1

◆ XED_IFORM_CVTTSD2SI_GPR64q_MEMsd_DEFINED

#define XED_IFORM_CVTTSD2SI_GPR64q_MEMsd_DEFINED   1

◆ XED_IFORM_CVTTSD2SI_GPR64q_XMMsd_DEFINED

#define XED_IFORM_CVTTSD2SI_GPR64q_XMMsd_DEFINED   1

◆ XED_IFORM_CVTTSS2SI_GPR32d_MEMss_DEFINED

#define XED_IFORM_CVTTSS2SI_GPR32d_MEMss_DEFINED   1

◆ XED_IFORM_CVTTSS2SI_GPR32d_XMMss_DEFINED

#define XED_IFORM_CVTTSS2SI_GPR32d_XMMss_DEFINED   1

◆ XED_IFORM_CVTTSS2SI_GPR64q_MEMss_DEFINED

#define XED_IFORM_CVTTSS2SI_GPR64q_MEMss_DEFINED   1

◆ XED_IFORM_CVTTSS2SI_GPR64q_XMMss_DEFINED

#define XED_IFORM_CVTTSS2SI_GPR64q_XMMss_DEFINED   1

◆ XED_IFORM_CWD_DEFINED

#define XED_IFORM_CWD_DEFINED   1

◆ XED_IFORM_CWDE_DEFINED

#define XED_IFORM_CWDE_DEFINED   1

◆ XED_IFORM_DAA_DEFINED

#define XED_IFORM_DAA_DEFINED   1

◆ XED_IFORM_DAS_DEFINED

#define XED_IFORM_DAS_DEFINED   1

◆ XED_IFORM_DEC_GPR8_DEFINED

#define XED_IFORM_DEC_GPR8_DEFINED   1

◆ XED_IFORM_DEC_GPR8i8_APX_DEFINED

#define XED_IFORM_DEC_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_DEC_GPR8i8_GPR8i8_APX_DEFINED

#define XED_IFORM_DEC_GPR8i8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_DEC_GPR8i8_MEMi8_APX_DEFINED

#define XED_IFORM_DEC_GPR8i8_MEMi8_APX_DEFINED   1

◆ XED_IFORM_DEC_GPRv_48_DEFINED

#define XED_IFORM_DEC_GPRv_48_DEFINED   1

◆ XED_IFORM_DEC_GPRv_APX_DEFINED

#define XED_IFORM_DEC_GPRv_APX_DEFINED   1

◆ XED_IFORM_DEC_GPRv_FFr1_DEFINED

#define XED_IFORM_DEC_GPRv_FFr1_DEFINED   1

◆ XED_IFORM_DEC_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_DEC_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_DEC_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_DEC_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_DEC_LOCK_MEMb_DEFINED

#define XED_IFORM_DEC_LOCK_MEMb_DEFINED   1

◆ XED_IFORM_DEC_LOCK_MEMv_DEFINED

#define XED_IFORM_DEC_LOCK_MEMv_DEFINED   1

◆ XED_IFORM_DEC_MEMb_DEFINED

#define XED_IFORM_DEC_MEMb_DEFINED   1

◆ XED_IFORM_DEC_MEMi8_APX_DEFINED

#define XED_IFORM_DEC_MEMi8_APX_DEFINED   1

◆ XED_IFORM_DEC_MEMv_APX_DEFINED

#define XED_IFORM_DEC_MEMv_APX_DEFINED   1

◆ XED_IFORM_DEC_MEMv_DEFINED

#define XED_IFORM_DEC_MEMv_DEFINED   1

◆ XED_IFORM_DIV_GPR8_DEFINED

#define XED_IFORM_DIV_GPR8_DEFINED   1

◆ XED_IFORM_DIV_GPR8i8_APX_DEFINED

#define XED_IFORM_DIV_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_DIV_GPRv_APX_DEFINED

#define XED_IFORM_DIV_GPRv_APX_DEFINED   1

◆ XED_IFORM_DIV_GPRv_DEFINED

#define XED_IFORM_DIV_GPRv_DEFINED   1

◆ XED_IFORM_DIV_MEMb_DEFINED

#define XED_IFORM_DIV_MEMb_DEFINED   1

◆ XED_IFORM_DIV_MEMi8_APX_DEFINED

#define XED_IFORM_DIV_MEMi8_APX_DEFINED   1

◆ XED_IFORM_DIV_MEMv_APX_DEFINED

#define XED_IFORM_DIV_MEMv_APX_DEFINED   1

◆ XED_IFORM_DIV_MEMv_DEFINED

#define XED_IFORM_DIV_MEMv_DEFINED   1

◆ XED_IFORM_DIVPD_XMMpd_MEMpd_DEFINED

#define XED_IFORM_DIVPD_XMMpd_MEMpd_DEFINED   1

◆ XED_IFORM_DIVPD_XMMpd_XMMpd_DEFINED

#define XED_IFORM_DIVPD_XMMpd_XMMpd_DEFINED   1

◆ XED_IFORM_DIVPS_XMMps_MEMps_DEFINED

#define XED_IFORM_DIVPS_XMMps_MEMps_DEFINED   1

◆ XED_IFORM_DIVPS_XMMps_XMMps_DEFINED

#define XED_IFORM_DIVPS_XMMps_XMMps_DEFINED   1

◆ XED_IFORM_DIVSD_XMMsd_MEMsd_DEFINED

#define XED_IFORM_DIVSD_XMMsd_MEMsd_DEFINED   1

◆ XED_IFORM_DIVSD_XMMsd_XMMsd_DEFINED

#define XED_IFORM_DIVSD_XMMsd_XMMsd_DEFINED   1

◆ XED_IFORM_DIVSS_XMMss_MEMss_DEFINED

#define XED_IFORM_DIVSS_XMMss_MEMss_DEFINED   1

◆ XED_IFORM_DIVSS_XMMss_XMMss_DEFINED

#define XED_IFORM_DIVSS_XMMss_XMMss_DEFINED   1

◆ XED_IFORM_DPPD_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_DPPD_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_DPPD_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_DPPD_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_DPPS_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_DPPS_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_DPPS_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_DPPS_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_EMMS_DEFINED

#define XED_IFORM_EMMS_DEFINED   1

◆ XED_IFORM_ENCLS_DEFINED

#define XED_IFORM_ENCLS_DEFINED   1

◆ XED_IFORM_ENCLU_DEFINED

#define XED_IFORM_ENCLU_DEFINED   1

◆ XED_IFORM_ENCLV_DEFINED

#define XED_IFORM_ENCLV_DEFINED   1

◆ XED_IFORM_ENCODEKEY128_GPR32u8_GPR32u8_DEFINED

#define XED_IFORM_ENCODEKEY128_GPR32u8_GPR32u8_DEFINED   1

◆ XED_IFORM_ENCODEKEY256_GPR32u8_GPR32u8_DEFINED

#define XED_IFORM_ENCODEKEY256_GPR32u8_GPR32u8_DEFINED   1

◆ XED_IFORM_ENDBR32_DEFINED

#define XED_IFORM_ENDBR32_DEFINED   1

◆ XED_IFORM_ENDBR64_DEFINED

#define XED_IFORM_ENDBR64_DEFINED   1

◆ XED_IFORM_ENQCMD_GPRa_MEMu32_DEFINED

#define XED_IFORM_ENQCMD_GPRa_MEMu32_DEFINED   1

◆ XED_IFORM_ENQCMD_GPRav_MEMu32_APX_DEFINED

#define XED_IFORM_ENQCMD_GPRav_MEMu32_APX_DEFINED   1

◆ XED_IFORM_ENQCMDS_GPRa_MEMu32_DEFINED

#define XED_IFORM_ENQCMDS_GPRa_MEMu32_DEFINED   1

◆ XED_IFORM_ENQCMDS_GPRav_MEMu32_APX_DEFINED

#define XED_IFORM_ENQCMDS_GPRav_MEMu32_APX_DEFINED   1

◆ XED_IFORM_ENTER_IMMw_IMMb_DEFINED

#define XED_IFORM_ENTER_IMMw_IMMb_DEFINED   1

◆ XED_IFORM_ERETS_DEFINED

#define XED_IFORM_ERETS_DEFINED   1

◆ XED_IFORM_ERETU_DEFINED

#define XED_IFORM_ERETU_DEFINED   1

◆ XED_IFORM_EXTRACTPS_GPR32d_XMMdq_IMMb_DEFINED

#define XED_IFORM_EXTRACTPS_GPR32d_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_EXTRACTPS_MEMd_XMMps_IMMb_DEFINED

#define XED_IFORM_EXTRACTPS_MEMd_XMMps_IMMb_DEFINED   1

◆ XED_IFORM_EXTRQ_XMMq_IMMb_IMMb_DEFINED

#define XED_IFORM_EXTRQ_XMMq_IMMb_IMMb_DEFINED   1

◆ XED_IFORM_EXTRQ_XMMq_XMMdq_DEFINED

#define XED_IFORM_EXTRQ_XMMq_XMMdq_DEFINED   1

◆ XED_IFORM_F2XM1_DEFINED

#define XED_IFORM_F2XM1_DEFINED   1

◆ XED_IFORM_FABS_DEFINED

#define XED_IFORM_FABS_DEFINED   1

◆ XED_IFORM_FADD_MEMm64real_DEFINED

#define XED_IFORM_FADD_MEMm64real_DEFINED   1

◆ XED_IFORM_FADD_MEMmem32real_DEFINED

#define XED_IFORM_FADD_MEMmem32real_DEFINED   1

◆ XED_IFORM_FADD_ST0_X87_DEFINED

#define XED_IFORM_FADD_ST0_X87_DEFINED   1

◆ XED_IFORM_FADD_X87_ST0_DEFINED

#define XED_IFORM_FADD_X87_ST0_DEFINED   1

◆ XED_IFORM_FADDP_X87_ST0_DEFINED

#define XED_IFORM_FADDP_X87_ST0_DEFINED   1

◆ XED_IFORM_FBLD_ST0_MEMmem80dec_DEFINED

#define XED_IFORM_FBLD_ST0_MEMmem80dec_DEFINED   1

◆ XED_IFORM_FBSTP_MEMmem80dec_ST0_DEFINED

#define XED_IFORM_FBSTP_MEMmem80dec_ST0_DEFINED   1

◆ XED_IFORM_FCHS_DEFINED

#define XED_IFORM_FCHS_DEFINED   1

◆ XED_IFORM_FCMOVB_ST0_X87_DEFINED

#define XED_IFORM_FCMOVB_ST0_X87_DEFINED   1

◆ XED_IFORM_FCMOVBE_ST0_X87_DEFINED

#define XED_IFORM_FCMOVBE_ST0_X87_DEFINED   1

◆ XED_IFORM_FCMOVE_ST0_X87_DEFINED

#define XED_IFORM_FCMOVE_ST0_X87_DEFINED   1

◆ XED_IFORM_FCMOVNB_ST0_X87_DEFINED

#define XED_IFORM_FCMOVNB_ST0_X87_DEFINED   1

◆ XED_IFORM_FCMOVNBE_ST0_X87_DEFINED

#define XED_IFORM_FCMOVNBE_ST0_X87_DEFINED   1

◆ XED_IFORM_FCMOVNE_ST0_X87_DEFINED

#define XED_IFORM_FCMOVNE_ST0_X87_DEFINED   1

◆ XED_IFORM_FCMOVNU_ST0_X87_DEFINED

#define XED_IFORM_FCMOVNU_ST0_X87_DEFINED   1

◆ XED_IFORM_FCMOVU_ST0_X87_DEFINED

#define XED_IFORM_FCMOVU_ST0_X87_DEFINED   1

◆ XED_IFORM_FCOM_ST0_MEMm64real_DEFINED

#define XED_IFORM_FCOM_ST0_MEMm64real_DEFINED   1

◆ XED_IFORM_FCOM_ST0_MEMmem32real_DEFINED

#define XED_IFORM_FCOM_ST0_MEMmem32real_DEFINED   1

◆ XED_IFORM_FCOM_ST0_X87_DCD0_DEFINED

#define XED_IFORM_FCOM_ST0_X87_DCD0_DEFINED   1

◆ XED_IFORM_FCOM_ST0_X87_DEFINED

#define XED_IFORM_FCOM_ST0_X87_DEFINED   1

◆ XED_IFORM_FCOMI_ST0_X87_DEFINED

#define XED_IFORM_FCOMI_ST0_X87_DEFINED   1

◆ XED_IFORM_FCOMIP_ST0_X87_DEFINED

#define XED_IFORM_FCOMIP_ST0_X87_DEFINED   1

◆ XED_IFORM_FCOMP_ST0_MEMm64real_DEFINED

#define XED_IFORM_FCOMP_ST0_MEMm64real_DEFINED   1

◆ XED_IFORM_FCOMP_ST0_MEMmem32real_DEFINED

#define XED_IFORM_FCOMP_ST0_MEMmem32real_DEFINED   1

◆ XED_IFORM_FCOMP_ST0_X87_DCD1_DEFINED

#define XED_IFORM_FCOMP_ST0_X87_DCD1_DEFINED   1

◆ XED_IFORM_FCOMP_ST0_X87_DED0_DEFINED

#define XED_IFORM_FCOMP_ST0_X87_DED0_DEFINED   1

◆ XED_IFORM_FCOMP_ST0_X87_DEFINED

#define XED_IFORM_FCOMP_ST0_X87_DEFINED   1

◆ XED_IFORM_FCOMPP_DEFINED

#define XED_IFORM_FCOMPP_DEFINED   1

◆ XED_IFORM_FCOS_DEFINED

#define XED_IFORM_FCOS_DEFINED   1

◆ XED_IFORM_FDECSTP_DEFINED

#define XED_IFORM_FDECSTP_DEFINED   1

◆ XED_IFORM_FDISI8087_NOP_DEFINED

#define XED_IFORM_FDISI8087_NOP_DEFINED   1

◆ XED_IFORM_FDIV_ST0_MEMm64real_DEFINED

#define XED_IFORM_FDIV_ST0_MEMm64real_DEFINED   1

◆ XED_IFORM_FDIV_ST0_MEMmem32real_DEFINED

#define XED_IFORM_FDIV_ST0_MEMmem32real_DEFINED   1

◆ XED_IFORM_FDIV_ST0_X87_DEFINED

#define XED_IFORM_FDIV_ST0_X87_DEFINED   1

◆ XED_IFORM_FDIV_X87_ST0_DEFINED

#define XED_IFORM_FDIV_X87_ST0_DEFINED   1

◆ XED_IFORM_FDIVP_X87_ST0_DEFINED

#define XED_IFORM_FDIVP_X87_ST0_DEFINED   1

◆ XED_IFORM_FDIVR_ST0_MEMm64real_DEFINED

#define XED_IFORM_FDIVR_ST0_MEMm64real_DEFINED   1

◆ XED_IFORM_FDIVR_ST0_MEMmem32real_DEFINED

#define XED_IFORM_FDIVR_ST0_MEMmem32real_DEFINED   1

◆ XED_IFORM_FDIVR_ST0_X87_DEFINED

#define XED_IFORM_FDIVR_ST0_X87_DEFINED   1

◆ XED_IFORM_FDIVR_X87_ST0_DEFINED

#define XED_IFORM_FDIVR_X87_ST0_DEFINED   1

◆ XED_IFORM_FDIVRP_X87_ST0_DEFINED

#define XED_IFORM_FDIVRP_X87_ST0_DEFINED   1

◆ XED_IFORM_FEMMS_DEFINED

#define XED_IFORM_FEMMS_DEFINED   1

◆ XED_IFORM_FENI8087_NOP_DEFINED

#define XED_IFORM_FENI8087_NOP_DEFINED   1

◆ XED_IFORM_FFREE_X87_DEFINED

#define XED_IFORM_FFREE_X87_DEFINED   1

◆ XED_IFORM_FFREEP_X87_DEFINED

#define XED_IFORM_FFREEP_X87_DEFINED   1

◆ XED_IFORM_FIADD_ST0_MEMmem16int_DEFINED

#define XED_IFORM_FIADD_ST0_MEMmem16int_DEFINED   1

◆ XED_IFORM_FIADD_ST0_MEMmem32int_DEFINED

#define XED_IFORM_FIADD_ST0_MEMmem32int_DEFINED   1

◆ XED_IFORM_FICOM_ST0_MEMmem16int_DEFINED

#define XED_IFORM_FICOM_ST0_MEMmem16int_DEFINED   1

◆ XED_IFORM_FICOM_ST0_MEMmem32int_DEFINED

#define XED_IFORM_FICOM_ST0_MEMmem32int_DEFINED   1

◆ XED_IFORM_FICOMP_ST0_MEMmem16int_DEFINED

#define XED_IFORM_FICOMP_ST0_MEMmem16int_DEFINED   1

◆ XED_IFORM_FICOMP_ST0_MEMmem32int_DEFINED

#define XED_IFORM_FICOMP_ST0_MEMmem32int_DEFINED   1

◆ XED_IFORM_FIDIV_ST0_MEMmem16int_DEFINED

#define XED_IFORM_FIDIV_ST0_MEMmem16int_DEFINED   1

◆ XED_IFORM_FIDIV_ST0_MEMmem32int_DEFINED

#define XED_IFORM_FIDIV_ST0_MEMmem32int_DEFINED   1

◆ XED_IFORM_FIDIVR_ST0_MEMmem16int_DEFINED

#define XED_IFORM_FIDIVR_ST0_MEMmem16int_DEFINED   1

◆ XED_IFORM_FIDIVR_ST0_MEMmem32int_DEFINED

#define XED_IFORM_FIDIVR_ST0_MEMmem32int_DEFINED   1

◆ XED_IFORM_FILD_ST0_MEMm64int_DEFINED

#define XED_IFORM_FILD_ST0_MEMm64int_DEFINED   1

◆ XED_IFORM_FILD_ST0_MEMmem16int_DEFINED

#define XED_IFORM_FILD_ST0_MEMmem16int_DEFINED   1

◆ XED_IFORM_FILD_ST0_MEMmem32int_DEFINED

#define XED_IFORM_FILD_ST0_MEMmem32int_DEFINED   1

◆ XED_IFORM_FIMUL_ST0_MEMmem16int_DEFINED

#define XED_IFORM_FIMUL_ST0_MEMmem16int_DEFINED   1

◆ XED_IFORM_FIMUL_ST0_MEMmem32int_DEFINED

#define XED_IFORM_FIMUL_ST0_MEMmem32int_DEFINED   1

◆ XED_IFORM_FINCSTP_DEFINED

#define XED_IFORM_FINCSTP_DEFINED   1

◆ XED_IFORM_FIST_MEMmem16int_ST0_DEFINED

#define XED_IFORM_FIST_MEMmem16int_ST0_DEFINED   1

◆ XED_IFORM_FIST_MEMmem32int_ST0_DEFINED

#define XED_IFORM_FIST_MEMmem32int_ST0_DEFINED   1

◆ XED_IFORM_FISTP_MEMm64int_ST0_DEFINED

#define XED_IFORM_FISTP_MEMm64int_ST0_DEFINED   1

◆ XED_IFORM_FISTP_MEMmem16int_ST0_DEFINED

#define XED_IFORM_FISTP_MEMmem16int_ST0_DEFINED   1

◆ XED_IFORM_FISTP_MEMmem32int_ST0_DEFINED

#define XED_IFORM_FISTP_MEMmem32int_ST0_DEFINED   1

◆ XED_IFORM_FISTTP_MEMm64int_ST0_DEFINED

#define XED_IFORM_FISTTP_MEMm64int_ST0_DEFINED   1

◆ XED_IFORM_FISTTP_MEMmem16int_ST0_DEFINED

#define XED_IFORM_FISTTP_MEMmem16int_ST0_DEFINED   1

◆ XED_IFORM_FISTTP_MEMmem32int_ST0_DEFINED

#define XED_IFORM_FISTTP_MEMmem32int_ST0_DEFINED   1

◆ XED_IFORM_FISUB_ST0_MEMmem16int_DEFINED

#define XED_IFORM_FISUB_ST0_MEMmem16int_DEFINED   1

◆ XED_IFORM_FISUB_ST0_MEMmem32int_DEFINED

#define XED_IFORM_FISUB_ST0_MEMmem32int_DEFINED   1

◆ XED_IFORM_FISUBR_ST0_MEMmem16int_DEFINED

#define XED_IFORM_FISUBR_ST0_MEMmem16int_DEFINED   1

◆ XED_IFORM_FISUBR_ST0_MEMmem32int_DEFINED

#define XED_IFORM_FISUBR_ST0_MEMmem32int_DEFINED   1

◆ XED_IFORM_FLD1_DEFINED

#define XED_IFORM_FLD1_DEFINED   1

◆ XED_IFORM_FLD_ST0_MEMm64real_DEFINED

#define XED_IFORM_FLD_ST0_MEMm64real_DEFINED   1

◆ XED_IFORM_FLD_ST0_MEMmem32real_DEFINED

#define XED_IFORM_FLD_ST0_MEMmem32real_DEFINED   1

◆ XED_IFORM_FLD_ST0_MEMmem80real_DEFINED

#define XED_IFORM_FLD_ST0_MEMmem80real_DEFINED   1

◆ XED_IFORM_FLD_ST0_X87_DEFINED

#define XED_IFORM_FLD_ST0_X87_DEFINED   1

◆ XED_IFORM_FLDCW_MEMmem16_DEFINED

#define XED_IFORM_FLDCW_MEMmem16_DEFINED   1

◆ XED_IFORM_FLDENV_MEMmem14_DEFINED

#define XED_IFORM_FLDENV_MEMmem14_DEFINED   1

◆ XED_IFORM_FLDENV_MEMmem28_DEFINED

#define XED_IFORM_FLDENV_MEMmem28_DEFINED   1

◆ XED_IFORM_FLDL2E_DEFINED

#define XED_IFORM_FLDL2E_DEFINED   1

◆ XED_IFORM_FLDL2T_DEFINED

#define XED_IFORM_FLDL2T_DEFINED   1

◆ XED_IFORM_FLDLG2_DEFINED

#define XED_IFORM_FLDLG2_DEFINED   1

◆ XED_IFORM_FLDLN2_DEFINED

#define XED_IFORM_FLDLN2_DEFINED   1

◆ XED_IFORM_FLDPI_DEFINED

#define XED_IFORM_FLDPI_DEFINED   1

◆ XED_IFORM_FLDZ_DEFINED

#define XED_IFORM_FLDZ_DEFINED   1

◆ XED_IFORM_FMUL_ST0_MEMm64real_DEFINED

#define XED_IFORM_FMUL_ST0_MEMm64real_DEFINED   1

◆ XED_IFORM_FMUL_ST0_MEMmem32real_DEFINED

#define XED_IFORM_FMUL_ST0_MEMmem32real_DEFINED   1

◆ XED_IFORM_FMUL_ST0_X87_DEFINED

#define XED_IFORM_FMUL_ST0_X87_DEFINED   1

◆ XED_IFORM_FMUL_X87_ST0_DEFINED

#define XED_IFORM_FMUL_X87_ST0_DEFINED   1

◆ XED_IFORM_FMULP_X87_ST0_DEFINED

#define XED_IFORM_FMULP_X87_ST0_DEFINED   1

◆ XED_IFORM_FNCLEX_DEFINED

#define XED_IFORM_FNCLEX_DEFINED   1

◆ XED_IFORM_FNINIT_DEFINED

#define XED_IFORM_FNINIT_DEFINED   1

◆ XED_IFORM_FNOP_DEFINED

#define XED_IFORM_FNOP_DEFINED   1

◆ XED_IFORM_FNSAVE_MEMmem108_DEFINED

#define XED_IFORM_FNSAVE_MEMmem108_DEFINED   1

◆ XED_IFORM_FNSAVE_MEMmem94_DEFINED

#define XED_IFORM_FNSAVE_MEMmem94_DEFINED   1

◆ XED_IFORM_FNSTCW_MEMmem16_DEFINED

#define XED_IFORM_FNSTCW_MEMmem16_DEFINED   1

◆ XED_IFORM_FNSTENV_MEMmem14_DEFINED

#define XED_IFORM_FNSTENV_MEMmem14_DEFINED   1

◆ XED_IFORM_FNSTENV_MEMmem28_DEFINED

#define XED_IFORM_FNSTENV_MEMmem28_DEFINED   1

◆ XED_IFORM_FNSTSW_AX_DEFINED

#define XED_IFORM_FNSTSW_AX_DEFINED   1

◆ XED_IFORM_FNSTSW_MEMmem16_DEFINED

#define XED_IFORM_FNSTSW_MEMmem16_DEFINED   1

◆ XED_IFORM_FPATAN_DEFINED

#define XED_IFORM_FPATAN_DEFINED   1

◆ XED_IFORM_FPREM1_DEFINED

#define XED_IFORM_FPREM1_DEFINED   1

◆ XED_IFORM_FPREM_DEFINED

#define XED_IFORM_FPREM_DEFINED   1

◆ XED_IFORM_FPTAN_DEFINED

#define XED_IFORM_FPTAN_DEFINED   1

◆ XED_IFORM_FRNDINT_DEFINED

#define XED_IFORM_FRNDINT_DEFINED   1

◆ XED_IFORM_FRSTOR_MEMmem108_DEFINED

#define XED_IFORM_FRSTOR_MEMmem108_DEFINED   1

◆ XED_IFORM_FRSTOR_MEMmem94_DEFINED

#define XED_IFORM_FRSTOR_MEMmem94_DEFINED   1

◆ XED_IFORM_FSCALE_DEFINED

#define XED_IFORM_FSCALE_DEFINED   1

◆ XED_IFORM_FSETPM287_NOP_DEFINED

#define XED_IFORM_FSETPM287_NOP_DEFINED   1

◆ XED_IFORM_FSIN_DEFINED

#define XED_IFORM_FSIN_DEFINED   1

◆ XED_IFORM_FSINCOS_DEFINED

#define XED_IFORM_FSINCOS_DEFINED   1

◆ XED_IFORM_FSQRT_DEFINED

#define XED_IFORM_FSQRT_DEFINED   1

◆ XED_IFORM_FST_MEMm64real_ST0_DEFINED

#define XED_IFORM_FST_MEMm64real_ST0_DEFINED   1

◆ XED_IFORM_FST_MEMmem32real_ST0_DEFINED

#define XED_IFORM_FST_MEMmem32real_ST0_DEFINED   1

◆ XED_IFORM_FST_X87_ST0_DEFINED

#define XED_IFORM_FST_X87_ST0_DEFINED   1

◆ XED_IFORM_FSTP_MEMm64real_ST0_DEFINED

#define XED_IFORM_FSTP_MEMm64real_ST0_DEFINED   1

◆ XED_IFORM_FSTP_MEMmem32real_ST0_DEFINED

#define XED_IFORM_FSTP_MEMmem32real_ST0_DEFINED   1

◆ XED_IFORM_FSTP_MEMmem80real_ST0_DEFINED

#define XED_IFORM_FSTP_MEMmem80real_ST0_DEFINED   1

◆ XED_IFORM_FSTP_X87_ST0_DEFINED

#define XED_IFORM_FSTP_X87_ST0_DEFINED   1

◆ XED_IFORM_FSTP_X87_ST0_DFD0_DEFINED

#define XED_IFORM_FSTP_X87_ST0_DFD0_DEFINED   1

◆ XED_IFORM_FSTP_X87_ST0_DFD1_DEFINED

#define XED_IFORM_FSTP_X87_ST0_DFD1_DEFINED   1

◆ XED_IFORM_FSTPNCE_X87_ST0_DEFINED

#define XED_IFORM_FSTPNCE_X87_ST0_DEFINED   1

◆ XED_IFORM_FSUB_ST0_MEMm64real_DEFINED

#define XED_IFORM_FSUB_ST0_MEMm64real_DEFINED   1

◆ XED_IFORM_FSUB_ST0_MEMmem32real_DEFINED

#define XED_IFORM_FSUB_ST0_MEMmem32real_DEFINED   1

◆ XED_IFORM_FSUB_ST0_X87_DEFINED

#define XED_IFORM_FSUB_ST0_X87_DEFINED   1

◆ XED_IFORM_FSUB_X87_ST0_DEFINED

#define XED_IFORM_FSUB_X87_ST0_DEFINED   1

◆ XED_IFORM_FSUBP_X87_ST0_DEFINED

#define XED_IFORM_FSUBP_X87_ST0_DEFINED   1

◆ XED_IFORM_FSUBR_ST0_MEMm64real_DEFINED

#define XED_IFORM_FSUBR_ST0_MEMm64real_DEFINED   1

◆ XED_IFORM_FSUBR_ST0_MEMmem32real_DEFINED

#define XED_IFORM_FSUBR_ST0_MEMmem32real_DEFINED   1

◆ XED_IFORM_FSUBR_ST0_X87_DEFINED

#define XED_IFORM_FSUBR_ST0_X87_DEFINED   1

◆ XED_IFORM_FSUBR_X87_ST0_DEFINED

#define XED_IFORM_FSUBR_X87_ST0_DEFINED   1

◆ XED_IFORM_FSUBRP_X87_ST0_DEFINED

#define XED_IFORM_FSUBRP_X87_ST0_DEFINED   1

◆ XED_IFORM_FTST_DEFINED

#define XED_IFORM_FTST_DEFINED   1

◆ XED_IFORM_FUCOM_ST0_X87_DEFINED

#define XED_IFORM_FUCOM_ST0_X87_DEFINED   1

◆ XED_IFORM_FUCOMI_ST0_X87_DEFINED

#define XED_IFORM_FUCOMI_ST0_X87_DEFINED   1

◆ XED_IFORM_FUCOMIP_ST0_X87_DEFINED

#define XED_IFORM_FUCOMIP_ST0_X87_DEFINED   1

◆ XED_IFORM_FUCOMP_ST0_X87_DEFINED

#define XED_IFORM_FUCOMP_ST0_X87_DEFINED   1

◆ XED_IFORM_FUCOMPP_DEFINED

#define XED_IFORM_FUCOMPP_DEFINED   1

◆ XED_IFORM_FWAIT_DEFINED

#define XED_IFORM_FWAIT_DEFINED   1

◆ XED_IFORM_FXAM_DEFINED

#define XED_IFORM_FXAM_DEFINED   1

◆ XED_IFORM_FXCH_ST0_X87_DDC1_DEFINED

#define XED_IFORM_FXCH_ST0_X87_DDC1_DEFINED   1

◆ XED_IFORM_FXCH_ST0_X87_DEFINED

#define XED_IFORM_FXCH_ST0_X87_DEFINED   1

◆ XED_IFORM_FXCH_ST0_X87_DFC1_DEFINED

#define XED_IFORM_FXCH_ST0_X87_DFC1_DEFINED   1

◆ XED_IFORM_FXRSTOR64_MEMmfpxenv_DEFINED

#define XED_IFORM_FXRSTOR64_MEMmfpxenv_DEFINED   1

◆ XED_IFORM_FXRSTOR_MEMmfpxenv_DEFINED

#define XED_IFORM_FXRSTOR_MEMmfpxenv_DEFINED   1

◆ XED_IFORM_FXSAVE64_MEMmfpxenv_DEFINED

#define XED_IFORM_FXSAVE64_MEMmfpxenv_DEFINED   1

◆ XED_IFORM_FXSAVE_MEMmfpxenv_DEFINED

#define XED_IFORM_FXSAVE_MEMmfpxenv_DEFINED   1

◆ XED_IFORM_FXTRACT_DEFINED

#define XED_IFORM_FXTRACT_DEFINED   1

◆ XED_IFORM_FYL2X_DEFINED

#define XED_IFORM_FYL2X_DEFINED   1

◆ XED_IFORM_FYL2XP1_DEFINED

#define XED_IFORM_FYL2XP1_DEFINED   1

◆ XED_IFORM_GETSEC_DEFINED

#define XED_IFORM_GETSEC_DEFINED   1

◆ XED_IFORM_GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8_DEFINED

#define XED_IFORM_GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8_DEFINED   1

◆ XED_IFORM_GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8_DEFINED

#define XED_IFORM_GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8_DEFINED   1

◆ XED_IFORM_GF2P8AFFINEQB_XMMu8_MEMu64_IMM8_DEFINED

#define XED_IFORM_GF2P8AFFINEQB_XMMu8_MEMu64_IMM8_DEFINED   1

◆ XED_IFORM_GF2P8AFFINEQB_XMMu8_XMMu64_IMM8_DEFINED

#define XED_IFORM_GF2P8AFFINEQB_XMMu8_XMMu64_IMM8_DEFINED   1

◆ XED_IFORM_GF2P8MULB_XMMu8_MEMu8_DEFINED

#define XED_IFORM_GF2P8MULB_XMMu8_MEMu8_DEFINED   1

◆ XED_IFORM_GF2P8MULB_XMMu8_XMMu8_DEFINED

#define XED_IFORM_GF2P8MULB_XMMu8_XMMu8_DEFINED   1

◆ XED_IFORM_HADDPD_XMMpd_MEMpd_DEFINED

#define XED_IFORM_HADDPD_XMMpd_MEMpd_DEFINED   1

◆ XED_IFORM_HADDPD_XMMpd_XMMpd_DEFINED

#define XED_IFORM_HADDPD_XMMpd_XMMpd_DEFINED   1

◆ XED_IFORM_HADDPS_XMMps_MEMps_DEFINED

#define XED_IFORM_HADDPS_XMMps_MEMps_DEFINED   1

◆ XED_IFORM_HADDPS_XMMps_XMMps_DEFINED

#define XED_IFORM_HADDPS_XMMps_XMMps_DEFINED   1

◆ XED_IFORM_HLT_DEFINED

#define XED_IFORM_HLT_DEFINED   1

◆ XED_IFORM_HRESET_IMM8_DEFINED

#define XED_IFORM_HRESET_IMM8_DEFINED   1

◆ XED_IFORM_HSUBPD_XMMpd_MEMpd_DEFINED

#define XED_IFORM_HSUBPD_XMMpd_MEMpd_DEFINED   1

◆ XED_IFORM_HSUBPD_XMMpd_XMMpd_DEFINED

#define XED_IFORM_HSUBPD_XMMpd_XMMpd_DEFINED   1

◆ XED_IFORM_HSUBPS_XMMps_MEMps_DEFINED

#define XED_IFORM_HSUBPS_XMMps_MEMps_DEFINED   1

◆ XED_IFORM_HSUBPS_XMMps_XMMps_DEFINED

#define XED_IFORM_HSUBPS_XMMps_XMMps_DEFINED   1

◆ XED_IFORM_IDIV_GPR8_DEFINED

#define XED_IFORM_IDIV_GPR8_DEFINED   1

◆ XED_IFORM_IDIV_GPR8i8_APX_DEFINED

#define XED_IFORM_IDIV_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_IDIV_GPRv_APX_DEFINED

#define XED_IFORM_IDIV_GPRv_APX_DEFINED   1

◆ XED_IFORM_IDIV_GPRv_DEFINED

#define XED_IFORM_IDIV_GPRv_DEFINED   1

◆ XED_IFORM_IDIV_MEMb_DEFINED

#define XED_IFORM_IDIV_MEMb_DEFINED   1

◆ XED_IFORM_IDIV_MEMi8_APX_DEFINED

#define XED_IFORM_IDIV_MEMi8_APX_DEFINED   1

◆ XED_IFORM_IDIV_MEMv_APX_DEFINED

#define XED_IFORM_IDIV_MEMv_APX_DEFINED   1

◆ XED_IFORM_IDIV_MEMv_DEFINED

#define XED_IFORM_IDIV_MEMv_DEFINED   1

◆ XED_IFORM_IMUL_GPR8_DEFINED

#define XED_IFORM_IMUL_GPR8_DEFINED   1

◆ XED_IFORM_IMUL_GPR8i8_APX_DEFINED

#define XED_IFORM_IMUL_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_IMUL_GPRv_APX_DEFINED

#define XED_IFORM_IMUL_GPRv_APX_DEFINED   1

◆ XED_IFORM_IMUL_GPRv_DEFINED

#define XED_IFORM_IMUL_GPRv_DEFINED   1

◆ XED_IFORM_IMUL_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_IMUL_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_IMUL_GPRv_GPRv_DEFINED

#define XED_IFORM_IMUL_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_IMUL_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_IMUL_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_IMUL_GPRv_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_IMUL_GPRv_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_IMUL_GPRv_GPRv_IMM8_APX_ZU_DEFINED

#define XED_IFORM_IMUL_GPRv_GPRv_IMM8_APX_ZU_DEFINED   1

◆ XED_IFORM_IMUL_GPRv_GPRv_IMMb_DEFINED

#define XED_IFORM_IMUL_GPRv_GPRv_IMMb_DEFINED   1

◆ XED_IFORM_IMUL_GPRv_GPRv_IMMz_APX_DEFINED

#define XED_IFORM_IMUL_GPRv_GPRv_IMMz_APX_DEFINED   1

◆ XED_IFORM_IMUL_GPRv_GPRv_IMMz_APX_ZU_DEFINED

#define XED_IFORM_IMUL_GPRv_GPRv_IMMz_APX_ZU_DEFINED   1

◆ XED_IFORM_IMUL_GPRv_GPRv_IMMz_DEFINED

#define XED_IFORM_IMUL_GPRv_GPRv_IMMz_DEFINED   1

◆ XED_IFORM_IMUL_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_IMUL_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_IMUL_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_IMUL_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_IMUL_GPRv_MEMv_DEFINED

#define XED_IFORM_IMUL_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_IMUL_GPRv_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_IMUL_GPRv_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_IMUL_GPRv_MEMv_IMM8_APX_ZU_DEFINED

#define XED_IFORM_IMUL_GPRv_MEMv_IMM8_APX_ZU_DEFINED   1

◆ XED_IFORM_IMUL_GPRv_MEMv_IMMb_DEFINED

#define XED_IFORM_IMUL_GPRv_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_IMUL_GPRv_MEMv_IMMz_APX_DEFINED

#define XED_IFORM_IMUL_GPRv_MEMv_IMMz_APX_DEFINED   1

◆ XED_IFORM_IMUL_GPRv_MEMv_IMMz_APX_ZU_DEFINED

#define XED_IFORM_IMUL_GPRv_MEMv_IMMz_APX_ZU_DEFINED   1

◆ XED_IFORM_IMUL_GPRv_MEMv_IMMz_DEFINED

#define XED_IFORM_IMUL_GPRv_MEMv_IMMz_DEFINED   1

◆ XED_IFORM_IMUL_MEMb_DEFINED

#define XED_IFORM_IMUL_MEMb_DEFINED   1

◆ XED_IFORM_IMUL_MEMi8_APX_DEFINED

#define XED_IFORM_IMUL_MEMi8_APX_DEFINED   1

◆ XED_IFORM_IMUL_MEMv_APX_DEFINED

#define XED_IFORM_IMUL_MEMv_APX_DEFINED   1

◆ XED_IFORM_IMUL_MEMv_DEFINED

#define XED_IFORM_IMUL_MEMv_DEFINED   1

◆ XED_IFORM_IN_AL_DX_DEFINED

#define XED_IFORM_IN_AL_DX_DEFINED   1

◆ XED_IFORM_IN_AL_IMMb_DEFINED

#define XED_IFORM_IN_AL_IMMb_DEFINED   1

◆ XED_IFORM_IN_OeAX_DX_DEFINED

#define XED_IFORM_IN_OeAX_DX_DEFINED   1

◆ XED_IFORM_IN_OeAX_IMMb_DEFINED

#define XED_IFORM_IN_OeAX_IMMb_DEFINED   1

◆ XED_IFORM_INC_GPR8_DEFINED

#define XED_IFORM_INC_GPR8_DEFINED   1

◆ XED_IFORM_INC_GPR8i8_APX_DEFINED

#define XED_IFORM_INC_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_INC_GPR8i8_GPR8i8_APX_DEFINED

#define XED_IFORM_INC_GPR8i8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_INC_GPR8i8_MEMi8_APX_DEFINED

#define XED_IFORM_INC_GPR8i8_MEMi8_APX_DEFINED   1

◆ XED_IFORM_INC_GPRv_40_DEFINED

#define XED_IFORM_INC_GPRv_40_DEFINED   1

◆ XED_IFORM_INC_GPRv_APX_DEFINED

#define XED_IFORM_INC_GPRv_APX_DEFINED   1

◆ XED_IFORM_INC_GPRv_FFr0_DEFINED

#define XED_IFORM_INC_GPRv_FFr0_DEFINED   1

◆ XED_IFORM_INC_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_INC_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_INC_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_INC_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_INC_LOCK_MEMb_DEFINED

#define XED_IFORM_INC_LOCK_MEMb_DEFINED   1

◆ XED_IFORM_INC_LOCK_MEMv_DEFINED

#define XED_IFORM_INC_LOCK_MEMv_DEFINED   1

◆ XED_IFORM_INC_MEMb_DEFINED

#define XED_IFORM_INC_MEMb_DEFINED   1

◆ XED_IFORM_INC_MEMi8_APX_DEFINED

#define XED_IFORM_INC_MEMi8_APX_DEFINED   1

◆ XED_IFORM_INC_MEMv_APX_DEFINED

#define XED_IFORM_INC_MEMv_APX_DEFINED   1

◆ XED_IFORM_INC_MEMv_DEFINED

#define XED_IFORM_INC_MEMv_DEFINED   1

◆ XED_IFORM_INCSSPD_GPR32u8_DEFINED

#define XED_IFORM_INCSSPD_GPR32u8_DEFINED   1

◆ XED_IFORM_INCSSPQ_GPR64u8_DEFINED

#define XED_IFORM_INCSSPQ_GPR64u8_DEFINED   1

◆ XED_IFORM_INSB_DEFINED

#define XED_IFORM_INSB_DEFINED   1

◆ XED_IFORM_INSD_DEFINED

#define XED_IFORM_INSD_DEFINED   1

◆ XED_IFORM_INSERTPS_XMMps_MEMd_IMMb_DEFINED

#define XED_IFORM_INSERTPS_XMMps_MEMd_IMMb_DEFINED   1

◆ XED_IFORM_INSERTPS_XMMps_XMMps_IMMb_DEFINED

#define XED_IFORM_INSERTPS_XMMps_XMMps_IMMb_DEFINED   1

◆ XED_IFORM_INSERTQ_XMMq_XMMdq_DEFINED

#define XED_IFORM_INSERTQ_XMMq_XMMdq_DEFINED   1

◆ XED_IFORM_INSERTQ_XMMq_XMMq_IMMb_IMMb_DEFINED

#define XED_IFORM_INSERTQ_XMMq_XMMq_IMMb_IMMb_DEFINED   1

◆ XED_IFORM_INSW_DEFINED

#define XED_IFORM_INSW_DEFINED   1

◆ XED_IFORM_INT1_DEFINED

#define XED_IFORM_INT1_DEFINED   1

◆ XED_IFORM_INT3_DEFINED

#define XED_IFORM_INT3_DEFINED   1

◆ XED_IFORM_INT_IMMb_DEFINED

#define XED_IFORM_INT_IMMb_DEFINED   1

◆ XED_IFORM_INTO_DEFINED

#define XED_IFORM_INTO_DEFINED   1

◆ XED_IFORM_INVALID_DEFINED

#define XED_IFORM_INVALID_DEFINED   1

◆ XED_IFORM_INVD_DEFINED

#define XED_IFORM_INVD_DEFINED   1

◆ XED_IFORM_INVEPT_GPR32_MEMdq_DEFINED

#define XED_IFORM_INVEPT_GPR32_MEMdq_DEFINED   1

◆ XED_IFORM_INVEPT_GPR64_MEMdq_DEFINED

#define XED_IFORM_INVEPT_GPR64_MEMdq_DEFINED   1

◆ XED_IFORM_INVEPT_GPR64i64_MEMi128_APX_DEFINED

#define XED_IFORM_INVEPT_GPR64i64_MEMi128_APX_DEFINED   1

◆ XED_IFORM_INVLPG_MEMb_DEFINED

#define XED_IFORM_INVLPG_MEMb_DEFINED   1

◆ XED_IFORM_INVLPGA_ArAX_ECX_DEFINED

#define XED_IFORM_INVLPGA_ArAX_ECX_DEFINED   1

◆ XED_IFORM_INVLPGB_DEFINED

#define XED_IFORM_INVLPGB_DEFINED   1

◆ XED_IFORM_INVPCID_GPR32_MEMdq_DEFINED

#define XED_IFORM_INVPCID_GPR32_MEMdq_DEFINED   1

◆ XED_IFORM_INVPCID_GPR64_MEMdq_DEFINED

#define XED_IFORM_INVPCID_GPR64_MEMdq_DEFINED   1

◆ XED_IFORM_INVPCID_GPR64i64_MEMi128_APX_DEFINED

#define XED_IFORM_INVPCID_GPR64i64_MEMi128_APX_DEFINED   1

◆ XED_IFORM_INVVPID_GPR32_MEMdq_DEFINED

#define XED_IFORM_INVVPID_GPR32_MEMdq_DEFINED   1

◆ XED_IFORM_INVVPID_GPR64_MEMdq_DEFINED

#define XED_IFORM_INVVPID_GPR64_MEMdq_DEFINED   1

◆ XED_IFORM_INVVPID_GPR64i64_MEMi128_APX_DEFINED

#define XED_IFORM_INVVPID_GPR64i64_MEMi128_APX_DEFINED   1

◆ XED_IFORM_IRET_DEFINED

#define XED_IFORM_IRET_DEFINED   1

◆ XED_IFORM_IRETD_DEFINED

#define XED_IFORM_IRETD_DEFINED   1

◆ XED_IFORM_IRETQ_DEFINED

#define XED_IFORM_IRETQ_DEFINED   1

◆ XED_IFORM_JB_RELBRb_DEFINED

#define XED_IFORM_JB_RELBRb_DEFINED   1

◆ XED_IFORM_JB_RELBRd_DEFINED

#define XED_IFORM_JB_RELBRd_DEFINED   1

◆ XED_IFORM_JB_RELBRz_DEFINED

#define XED_IFORM_JB_RELBRz_DEFINED   1

◆ XED_IFORM_JBE_RELBRb_DEFINED

#define XED_IFORM_JBE_RELBRb_DEFINED   1

◆ XED_IFORM_JBE_RELBRd_DEFINED

#define XED_IFORM_JBE_RELBRd_DEFINED   1

◆ XED_IFORM_JBE_RELBRz_DEFINED

#define XED_IFORM_JBE_RELBRz_DEFINED   1

◆ XED_IFORM_JCXZ_RELBRb_DEFINED

#define XED_IFORM_JCXZ_RELBRb_DEFINED   1

◆ XED_IFORM_JECXZ_RELBRb_DEFINED

#define XED_IFORM_JECXZ_RELBRb_DEFINED   1

◆ XED_IFORM_JL_RELBRb_DEFINED

#define XED_IFORM_JL_RELBRb_DEFINED   1

◆ XED_IFORM_JL_RELBRd_DEFINED

#define XED_IFORM_JL_RELBRd_DEFINED   1

◆ XED_IFORM_JL_RELBRz_DEFINED

#define XED_IFORM_JL_RELBRz_DEFINED   1

◆ XED_IFORM_JLE_RELBRb_DEFINED

#define XED_IFORM_JLE_RELBRb_DEFINED   1

◆ XED_IFORM_JLE_RELBRd_DEFINED

#define XED_IFORM_JLE_RELBRd_DEFINED   1

◆ XED_IFORM_JLE_RELBRz_DEFINED

#define XED_IFORM_JLE_RELBRz_DEFINED   1

◆ XED_IFORM_JMP_FAR_MEMp2_DEFINED

#define XED_IFORM_JMP_FAR_MEMp2_DEFINED   1

◆ XED_IFORM_JMP_FAR_PTRp_IMMw_DEFINED

#define XED_IFORM_JMP_FAR_PTRp_IMMw_DEFINED   1

◆ XED_IFORM_JMP_GPRv_DEFINED

#define XED_IFORM_JMP_GPRv_DEFINED   1

◆ XED_IFORM_JMP_MEMv_DEFINED

#define XED_IFORM_JMP_MEMv_DEFINED   1

◆ XED_IFORM_JMP_RELBRb_DEFINED

#define XED_IFORM_JMP_RELBRb_DEFINED   1

◆ XED_IFORM_JMP_RELBRd_DEFINED

#define XED_IFORM_JMP_RELBRd_DEFINED   1

◆ XED_IFORM_JMP_RELBRz_DEFINED

#define XED_IFORM_JMP_RELBRz_DEFINED   1

◆ XED_IFORM_JMPABS_ABSBRu64_APX_DEFINED

#define XED_IFORM_JMPABS_ABSBRu64_APX_DEFINED   1

◆ XED_IFORM_JNB_RELBRb_DEFINED

#define XED_IFORM_JNB_RELBRb_DEFINED   1

◆ XED_IFORM_JNB_RELBRd_DEFINED

#define XED_IFORM_JNB_RELBRd_DEFINED   1

◆ XED_IFORM_JNB_RELBRz_DEFINED

#define XED_IFORM_JNB_RELBRz_DEFINED   1

◆ XED_IFORM_JNBE_RELBRb_DEFINED

#define XED_IFORM_JNBE_RELBRb_DEFINED   1

◆ XED_IFORM_JNBE_RELBRd_DEFINED

#define XED_IFORM_JNBE_RELBRd_DEFINED   1

◆ XED_IFORM_JNBE_RELBRz_DEFINED

#define XED_IFORM_JNBE_RELBRz_DEFINED   1

◆ XED_IFORM_JNL_RELBRb_DEFINED

#define XED_IFORM_JNL_RELBRb_DEFINED   1

◆ XED_IFORM_JNL_RELBRd_DEFINED

#define XED_IFORM_JNL_RELBRd_DEFINED   1

◆ XED_IFORM_JNL_RELBRz_DEFINED

#define XED_IFORM_JNL_RELBRz_DEFINED   1

◆ XED_IFORM_JNLE_RELBRb_DEFINED

#define XED_IFORM_JNLE_RELBRb_DEFINED   1

◆ XED_IFORM_JNLE_RELBRd_DEFINED

#define XED_IFORM_JNLE_RELBRd_DEFINED   1

◆ XED_IFORM_JNLE_RELBRz_DEFINED

#define XED_IFORM_JNLE_RELBRz_DEFINED   1

◆ XED_IFORM_JNO_RELBRb_DEFINED

#define XED_IFORM_JNO_RELBRb_DEFINED   1

◆ XED_IFORM_JNO_RELBRd_DEFINED

#define XED_IFORM_JNO_RELBRd_DEFINED   1

◆ XED_IFORM_JNO_RELBRz_DEFINED

#define XED_IFORM_JNO_RELBRz_DEFINED   1

◆ XED_IFORM_JNP_RELBRb_DEFINED

#define XED_IFORM_JNP_RELBRb_DEFINED   1

◆ XED_IFORM_JNP_RELBRd_DEFINED

#define XED_IFORM_JNP_RELBRd_DEFINED   1

◆ XED_IFORM_JNP_RELBRz_DEFINED

#define XED_IFORM_JNP_RELBRz_DEFINED   1

◆ XED_IFORM_JNS_RELBRb_DEFINED

#define XED_IFORM_JNS_RELBRb_DEFINED   1

◆ XED_IFORM_JNS_RELBRd_DEFINED

#define XED_IFORM_JNS_RELBRd_DEFINED   1

◆ XED_IFORM_JNS_RELBRz_DEFINED

#define XED_IFORM_JNS_RELBRz_DEFINED   1

◆ XED_IFORM_JNZ_RELBRb_DEFINED

#define XED_IFORM_JNZ_RELBRb_DEFINED   1

◆ XED_IFORM_JNZ_RELBRd_DEFINED

#define XED_IFORM_JNZ_RELBRd_DEFINED   1

◆ XED_IFORM_JNZ_RELBRz_DEFINED

#define XED_IFORM_JNZ_RELBRz_DEFINED   1

◆ XED_IFORM_JO_RELBRb_DEFINED

#define XED_IFORM_JO_RELBRb_DEFINED   1

◆ XED_IFORM_JO_RELBRd_DEFINED

#define XED_IFORM_JO_RELBRd_DEFINED   1

◆ XED_IFORM_JO_RELBRz_DEFINED

#define XED_IFORM_JO_RELBRz_DEFINED   1

◆ XED_IFORM_JP_RELBRb_DEFINED

#define XED_IFORM_JP_RELBRb_DEFINED   1

◆ XED_IFORM_JP_RELBRd_DEFINED

#define XED_IFORM_JP_RELBRd_DEFINED   1

◆ XED_IFORM_JP_RELBRz_DEFINED

#define XED_IFORM_JP_RELBRz_DEFINED   1

◆ XED_IFORM_JRCXZ_RELBRb_DEFINED

#define XED_IFORM_JRCXZ_RELBRb_DEFINED   1

◆ XED_IFORM_JS_RELBRb_DEFINED

#define XED_IFORM_JS_RELBRb_DEFINED   1

◆ XED_IFORM_JS_RELBRd_DEFINED

#define XED_IFORM_JS_RELBRd_DEFINED   1

◆ XED_IFORM_JS_RELBRz_DEFINED

#define XED_IFORM_JS_RELBRz_DEFINED   1

◆ XED_IFORM_JZ_RELBRb_DEFINED

#define XED_IFORM_JZ_RELBRb_DEFINED   1

◆ XED_IFORM_JZ_RELBRd_DEFINED

#define XED_IFORM_JZ_RELBRd_DEFINED   1

◆ XED_IFORM_JZ_RELBRz_DEFINED

#define XED_IFORM_JZ_RELBRz_DEFINED   1

◆ XED_IFORM_KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KMOVB_GPR32u32_MASKmskw_APX_DEFINED

#define XED_IFORM_KMOVB_GPR32u32_MASKmskw_APX_DEFINED   1

◆ XED_IFORM_KMOVB_GPR32u32_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KMOVB_GPR32u32_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KMOVB_MASKmskw_GPR32u32_APX_DEFINED

#define XED_IFORM_KMOVB_MASKmskw_GPR32u32_APX_DEFINED   1

◆ XED_IFORM_KMOVB_MASKmskw_GPR32u32_AVX512_DEFINED

#define XED_IFORM_KMOVB_MASKmskw_GPR32u32_AVX512_DEFINED   1

◆ XED_IFORM_KMOVB_MASKmskw_MASKu8_APX_DEFINED

#define XED_IFORM_KMOVB_MASKmskw_MASKu8_APX_DEFINED   1

◆ XED_IFORM_KMOVB_MASKmskw_MASKu8_AVX512_DEFINED

#define XED_IFORM_KMOVB_MASKmskw_MASKu8_AVX512_DEFINED   1

◆ XED_IFORM_KMOVB_MASKmskw_MEMu8_APX_DEFINED

#define XED_IFORM_KMOVB_MASKmskw_MEMu8_APX_DEFINED   1

◆ XED_IFORM_KMOVB_MASKmskw_MEMu8_AVX512_DEFINED

#define XED_IFORM_KMOVB_MASKmskw_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_KMOVB_MEMu8_MASKmskw_APX_DEFINED

#define XED_IFORM_KMOVB_MEMu8_MASKmskw_APX_DEFINED   1

◆ XED_IFORM_KMOVB_MEMu8_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KMOVB_MEMu8_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KMOVD_GPR32u32_MASKmskw_APX_DEFINED

#define XED_IFORM_KMOVD_GPR32u32_MASKmskw_APX_DEFINED   1

◆ XED_IFORM_KMOVD_GPR32u32_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KMOVD_GPR32u32_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KMOVD_MASKmskw_GPR32u32_APX_DEFINED

#define XED_IFORM_KMOVD_MASKmskw_GPR32u32_APX_DEFINED   1

◆ XED_IFORM_KMOVD_MASKmskw_GPR32u32_AVX512_DEFINED

#define XED_IFORM_KMOVD_MASKmskw_GPR32u32_AVX512_DEFINED   1

◆ XED_IFORM_KMOVD_MASKmskw_MASKu32_APX_DEFINED

#define XED_IFORM_KMOVD_MASKmskw_MASKu32_APX_DEFINED   1

◆ XED_IFORM_KMOVD_MASKmskw_MASKu32_AVX512_DEFINED

#define XED_IFORM_KMOVD_MASKmskw_MASKu32_AVX512_DEFINED   1

◆ XED_IFORM_KMOVD_MASKmskw_MEMu32_APX_DEFINED

#define XED_IFORM_KMOVD_MASKmskw_MEMu32_APX_DEFINED   1

◆ XED_IFORM_KMOVD_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_KMOVD_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_KMOVD_MEMu32_MASKmskw_APX_DEFINED

#define XED_IFORM_KMOVD_MEMu32_MASKmskw_APX_DEFINED   1

◆ XED_IFORM_KMOVD_MEMu32_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KMOVD_MEMu32_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KMOVQ_GPR64u64_MASKmskw_APX_DEFINED

#define XED_IFORM_KMOVQ_GPR64u64_MASKmskw_APX_DEFINED   1

◆ XED_IFORM_KMOVQ_GPR64u64_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KMOVQ_GPR64u64_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KMOVQ_MASKmskw_GPR64u64_APX_DEFINED

#define XED_IFORM_KMOVQ_MASKmskw_GPR64u64_APX_DEFINED   1

◆ XED_IFORM_KMOVQ_MASKmskw_GPR64u64_AVX512_DEFINED

#define XED_IFORM_KMOVQ_MASKmskw_GPR64u64_AVX512_DEFINED   1

◆ XED_IFORM_KMOVQ_MASKmskw_MASKu64_APX_DEFINED

#define XED_IFORM_KMOVQ_MASKmskw_MASKu64_APX_DEFINED   1

◆ XED_IFORM_KMOVQ_MASKmskw_MASKu64_AVX512_DEFINED

#define XED_IFORM_KMOVQ_MASKmskw_MASKu64_AVX512_DEFINED   1

◆ XED_IFORM_KMOVQ_MASKmskw_MEMu64_APX_DEFINED

#define XED_IFORM_KMOVQ_MASKmskw_MEMu64_APX_DEFINED   1

◆ XED_IFORM_KMOVQ_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_KMOVQ_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_KMOVQ_MEMu64_MASKmskw_APX_DEFINED

#define XED_IFORM_KMOVQ_MEMu64_MASKmskw_APX_DEFINED   1

◆ XED_IFORM_KMOVQ_MEMu64_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KMOVQ_MEMu64_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KMOVW_GPR32u32_MASKmskw_APX_DEFINED

#define XED_IFORM_KMOVW_GPR32u32_MASKmskw_APX_DEFINED   1

◆ XED_IFORM_KMOVW_GPR32u32_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KMOVW_GPR32u32_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KMOVW_MASKmskw_GPR32u32_APX_DEFINED

#define XED_IFORM_KMOVW_MASKmskw_GPR32u32_APX_DEFINED   1

◆ XED_IFORM_KMOVW_MASKmskw_GPR32u32_AVX512_DEFINED

#define XED_IFORM_KMOVW_MASKmskw_GPR32u32_AVX512_DEFINED   1

◆ XED_IFORM_KMOVW_MASKmskw_MASKu16_APX_DEFINED

#define XED_IFORM_KMOVW_MASKmskw_MASKu16_APX_DEFINED   1

◆ XED_IFORM_KMOVW_MASKmskw_MASKu16_AVX512_DEFINED

#define XED_IFORM_KMOVW_MASKmskw_MASKu16_AVX512_DEFINED   1

◆ XED_IFORM_KMOVW_MASKmskw_MEMu16_APX_DEFINED

#define XED_IFORM_KMOVW_MASKmskw_MEMu16_APX_DEFINED   1

◆ XED_IFORM_KMOVW_MASKmskw_MEMu16_AVX512_DEFINED

#define XED_IFORM_KMOVW_MASKmskw_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_KMOVW_MEMu16_MASKmskw_APX_DEFINED

#define XED_IFORM_KMOVW_MEMu16_MASKmskw_APX_DEFINED   1

◆ XED_IFORM_KMOVW_MEMu16_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KMOVW_MEMu16_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KNOTB_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KNOTB_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KNOTD_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KNOTD_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KNOTQ_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KNOTQ_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KNOTW_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KNOTW_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KORB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KORB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KORD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KORD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KORTESTB_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KORTESTB_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KORTESTD_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KORTESTD_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KORTESTQ_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KORTESTQ_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KORTESTW_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KORTESTW_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KORW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KORW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED

#define XED_IFORM_KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED

#define XED_IFORM_KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED

#define XED_IFORM_KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED

#define XED_IFORM_KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED

#define XED_IFORM_KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED

#define XED_IFORM_KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED

#define XED_IFORM_KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED

#define XED_IFORM_KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_KTESTB_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KTESTB_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KTESTD_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KTESTD_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KTESTQ_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KTESTQ_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KTESTW_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KTESTW_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED

#define XED_IFORM_KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_LAHF_DEFINED

#define XED_IFORM_LAHF_DEFINED   1

◆ XED_IFORM_LAR_GPRv_GPRv_DEFINED

#define XED_IFORM_LAR_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_LAR_GPRv_MEMw_DEFINED

#define XED_IFORM_LAR_GPRv_MEMw_DEFINED   1

◆ XED_IFORM_LAST_DEFINED

#define XED_IFORM_LAST_DEFINED   1

◆ XED_IFORM_LDDQU_XMMpd_MEMdq_DEFINED

#define XED_IFORM_LDDQU_XMMpd_MEMdq_DEFINED   1

◆ XED_IFORM_LDMXCSR_MEMd_DEFINED

#define XED_IFORM_LDMXCSR_MEMd_DEFINED   1

◆ XED_IFORM_LDS_GPRz_MEMp_DEFINED

#define XED_IFORM_LDS_GPRz_MEMp_DEFINED   1

◆ XED_IFORM_LDTILECFG_MEM_APX_DEFINED

#define XED_IFORM_LDTILECFG_MEM_APX_DEFINED   1

◆ XED_IFORM_LDTILECFG_MEM_DEFINED

#define XED_IFORM_LDTILECFG_MEM_DEFINED   1

◆ XED_IFORM_LEA_GPRv_AGEN_DEFINED

#define XED_IFORM_LEA_GPRv_AGEN_DEFINED   1

◆ XED_IFORM_LEAVE_DEFINED

#define XED_IFORM_LEAVE_DEFINED   1

◆ XED_IFORM_LES_GPRz_MEMp_DEFINED

#define XED_IFORM_LES_GPRz_MEMp_DEFINED   1

◆ XED_IFORM_LFENCE_DEFINED

#define XED_IFORM_LFENCE_DEFINED   1

◆ XED_IFORM_LFS_GPRv_MEMp2_DEFINED

#define XED_IFORM_LFS_GPRv_MEMp2_DEFINED   1

◆ XED_IFORM_LGDT_MEMs64_DEFINED

#define XED_IFORM_LGDT_MEMs64_DEFINED   1

◆ XED_IFORM_LGDT_MEMs_DEFINED

#define XED_IFORM_LGDT_MEMs_DEFINED   1

◆ XED_IFORM_LGS_GPRv_MEMp2_DEFINED

#define XED_IFORM_LGS_GPRv_MEMp2_DEFINED   1

◆ XED_IFORM_LIDT_MEMs64_DEFINED

#define XED_IFORM_LIDT_MEMs64_DEFINED   1

◆ XED_IFORM_LIDT_MEMs_DEFINED

#define XED_IFORM_LIDT_MEMs_DEFINED   1

◆ XED_IFORM_LKGS_GPR16u16_DEFINED

#define XED_IFORM_LKGS_GPR16u16_DEFINED   1

◆ XED_IFORM_LKGS_MEMu16_DEFINED

#define XED_IFORM_LKGS_MEMu16_DEFINED   1

◆ XED_IFORM_LLDT_GPR16_DEFINED

#define XED_IFORM_LLDT_GPR16_DEFINED   1

◆ XED_IFORM_LLDT_MEMw_DEFINED

#define XED_IFORM_LLDT_MEMw_DEFINED   1

◆ XED_IFORM_LLWPCB_GPRyy_DEFINED

#define XED_IFORM_LLWPCB_GPRyy_DEFINED   1

◆ XED_IFORM_LMSW_GPR16_DEFINED

#define XED_IFORM_LMSW_GPR16_DEFINED   1

◆ XED_IFORM_LMSW_MEMw_DEFINED

#define XED_IFORM_LMSW_MEMw_DEFINED   1

◆ XED_IFORM_LOADIWKEY_XMMu8_XMMu8_DEFINED

#define XED_IFORM_LOADIWKEY_XMMu8_XMMu8_DEFINED   1

◆ XED_IFORM_LODSB_DEFINED

#define XED_IFORM_LODSB_DEFINED   1

◆ XED_IFORM_LODSD_DEFINED

#define XED_IFORM_LODSD_DEFINED   1

◆ XED_IFORM_LODSQ_DEFINED

#define XED_IFORM_LODSQ_DEFINED   1

◆ XED_IFORM_LODSW_DEFINED

#define XED_IFORM_LODSW_DEFINED   1

◆ XED_IFORM_LOOP_RELBRb_DEFINED

#define XED_IFORM_LOOP_RELBRb_DEFINED   1

◆ XED_IFORM_LOOPE_RELBRb_DEFINED

#define XED_IFORM_LOOPE_RELBRb_DEFINED   1

◆ XED_IFORM_LOOPNE_RELBRb_DEFINED

#define XED_IFORM_LOOPNE_RELBRb_DEFINED   1

◆ XED_IFORM_LSL_GPRv_GPRz_DEFINED

#define XED_IFORM_LSL_GPRv_GPRz_DEFINED   1

◆ XED_IFORM_LSL_GPRv_MEMw_DEFINED

#define XED_IFORM_LSL_GPRv_MEMw_DEFINED   1

◆ XED_IFORM_LSS_GPRv_MEMp2_DEFINED

#define XED_IFORM_LSS_GPRv_MEMp2_DEFINED   1

◆ XED_IFORM_LTR_GPR16_DEFINED

#define XED_IFORM_LTR_GPR16_DEFINED   1

◆ XED_IFORM_LTR_MEMw_DEFINED

#define XED_IFORM_LTR_MEMw_DEFINED   1

◆ XED_IFORM_LWPINS_GPRyy_GPR32d_IMMd_DEFINED

#define XED_IFORM_LWPINS_GPRyy_GPR32d_IMMd_DEFINED   1

◆ XED_IFORM_LWPINS_GPRyy_MEMd_IMMd_DEFINED

#define XED_IFORM_LWPINS_GPRyy_MEMd_IMMd_DEFINED   1

◆ XED_IFORM_LWPVAL_GPRyy_GPR32d_IMMd_DEFINED

#define XED_IFORM_LWPVAL_GPRyy_GPR32d_IMMd_DEFINED   1

◆ XED_IFORM_LWPVAL_GPRyy_MEMd_IMMd_DEFINED

#define XED_IFORM_LWPVAL_GPRyy_MEMd_IMMd_DEFINED   1

◆ XED_IFORM_LZCNT_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_LZCNT_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_LZCNT_GPRv_GPRv_DEFINED

#define XED_IFORM_LZCNT_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_LZCNT_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_LZCNT_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_LZCNT_GPRv_MEMv_DEFINED

#define XED_IFORM_LZCNT_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_MASKMOVDQU_XMMxub_XMMxub_DEFINED

#define XED_IFORM_MASKMOVDQU_XMMxub_XMMxub_DEFINED   1

◆ XED_IFORM_MASKMOVQ_MMXq_MMXq_DEFINED

#define XED_IFORM_MASKMOVQ_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_MAXPD_XMMpd_MEMpd_DEFINED

#define XED_IFORM_MAXPD_XMMpd_MEMpd_DEFINED   1

◆ XED_IFORM_MAXPD_XMMpd_XMMpd_DEFINED

#define XED_IFORM_MAXPD_XMMpd_XMMpd_DEFINED   1

◆ XED_IFORM_MAXPS_XMMps_MEMps_DEFINED

#define XED_IFORM_MAXPS_XMMps_MEMps_DEFINED   1

◆ XED_IFORM_MAXPS_XMMps_XMMps_DEFINED

#define XED_IFORM_MAXPS_XMMps_XMMps_DEFINED   1

◆ XED_IFORM_MAXSD_XMMsd_MEMsd_DEFINED

#define XED_IFORM_MAXSD_XMMsd_MEMsd_DEFINED   1

◆ XED_IFORM_MAXSD_XMMsd_XMMsd_DEFINED

#define XED_IFORM_MAXSD_XMMsd_XMMsd_DEFINED   1

◆ XED_IFORM_MAXSS_XMMss_MEMss_DEFINED

#define XED_IFORM_MAXSS_XMMss_MEMss_DEFINED   1

◆ XED_IFORM_MAXSS_XMMss_XMMss_DEFINED

#define XED_IFORM_MAXSS_XMMss_XMMss_DEFINED   1

◆ XED_IFORM_MCOMMIT_DEFINED

#define XED_IFORM_MCOMMIT_DEFINED   1

◆ XED_IFORM_MFENCE_DEFINED

#define XED_IFORM_MFENCE_DEFINED   1

◆ XED_IFORM_MINPD_XMMpd_MEMpd_DEFINED

#define XED_IFORM_MINPD_XMMpd_MEMpd_DEFINED   1

◆ XED_IFORM_MINPD_XMMpd_XMMpd_DEFINED

#define XED_IFORM_MINPD_XMMpd_XMMpd_DEFINED   1

◆ XED_IFORM_MINPS_XMMps_MEMps_DEFINED

#define XED_IFORM_MINPS_XMMps_MEMps_DEFINED   1

◆ XED_IFORM_MINPS_XMMps_XMMps_DEFINED

#define XED_IFORM_MINPS_XMMps_XMMps_DEFINED   1

◆ XED_IFORM_MINSD_XMMsd_MEMsd_DEFINED

#define XED_IFORM_MINSD_XMMsd_MEMsd_DEFINED   1

◆ XED_IFORM_MINSD_XMMsd_XMMsd_DEFINED

#define XED_IFORM_MINSD_XMMsd_XMMsd_DEFINED   1

◆ XED_IFORM_MINSS_XMMss_MEMss_DEFINED

#define XED_IFORM_MINSS_XMMss_MEMss_DEFINED   1

◆ XED_IFORM_MINSS_XMMss_XMMss_DEFINED

#define XED_IFORM_MINSS_XMMss_XMMss_DEFINED   1

◆ XED_IFORM_MONITOR_DEFINED

#define XED_IFORM_MONITOR_DEFINED   1

◆ XED_IFORM_MONITORX_DEFINED

#define XED_IFORM_MONITORX_DEFINED   1

◆ XED_IFORM_MOV_AL_MEMb_DEFINED

#define XED_IFORM_MOV_AL_MEMb_DEFINED   1

◆ XED_IFORM_MOV_CR_CR_GPR32_DEFINED

#define XED_IFORM_MOV_CR_CR_GPR32_DEFINED   1

◆ XED_IFORM_MOV_CR_CR_GPR64_DEFINED

#define XED_IFORM_MOV_CR_CR_GPR64_DEFINED   1

◆ XED_IFORM_MOV_CR_GPR32_CR_DEFINED

#define XED_IFORM_MOV_CR_GPR32_CR_DEFINED   1

◆ XED_IFORM_MOV_CR_GPR64_CR_DEFINED

#define XED_IFORM_MOV_CR_GPR64_CR_DEFINED   1

◆ XED_IFORM_MOV_DR_DR_GPR32_DEFINED

#define XED_IFORM_MOV_DR_DR_GPR32_DEFINED   1

◆ XED_IFORM_MOV_DR_DR_GPR64_DEFINED

#define XED_IFORM_MOV_DR_DR_GPR64_DEFINED   1

◆ XED_IFORM_MOV_DR_GPR32_DR_DEFINED

#define XED_IFORM_MOV_DR_GPR32_DR_DEFINED   1

◆ XED_IFORM_MOV_DR_GPR64_DR_DEFINED

#define XED_IFORM_MOV_DR_GPR64_DR_DEFINED   1

◆ XED_IFORM_MOV_GPR8_GPR8_88_DEFINED

#define XED_IFORM_MOV_GPR8_GPR8_88_DEFINED   1

◆ XED_IFORM_MOV_GPR8_GPR8_8A_DEFINED

#define XED_IFORM_MOV_GPR8_GPR8_8A_DEFINED   1

◆ XED_IFORM_MOV_GPR8_IMMb_B0_DEFINED

#define XED_IFORM_MOV_GPR8_IMMb_B0_DEFINED   1

◆ XED_IFORM_MOV_GPR8_IMMb_C6r0_DEFINED

#define XED_IFORM_MOV_GPR8_IMMb_C6r0_DEFINED   1

◆ XED_IFORM_MOV_GPR8_MEMb_DEFINED

#define XED_IFORM_MOV_GPR8_MEMb_DEFINED   1

◆ XED_IFORM_MOV_GPRv_GPRv_89_DEFINED

#define XED_IFORM_MOV_GPRv_GPRv_89_DEFINED   1

◆ XED_IFORM_MOV_GPRv_GPRv_8B_DEFINED

#define XED_IFORM_MOV_GPRv_GPRv_8B_DEFINED   1

◆ XED_IFORM_MOV_GPRv_IMMv_DEFINED

#define XED_IFORM_MOV_GPRv_IMMv_DEFINED   1

◆ XED_IFORM_MOV_GPRv_IMMz_DEFINED

#define XED_IFORM_MOV_GPRv_IMMz_DEFINED   1

◆ XED_IFORM_MOV_GPRv_MEMv_DEFINED

#define XED_IFORM_MOV_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_MOV_GPRv_SEG_DEFINED

#define XED_IFORM_MOV_GPRv_SEG_DEFINED   1

◆ XED_IFORM_MOV_MEMb_AL_DEFINED

#define XED_IFORM_MOV_MEMb_AL_DEFINED   1

◆ XED_IFORM_MOV_MEMb_GPR8_DEFINED

#define XED_IFORM_MOV_MEMb_GPR8_DEFINED   1

◆ XED_IFORM_MOV_MEMb_IMMb_DEFINED

#define XED_IFORM_MOV_MEMb_IMMb_DEFINED   1

◆ XED_IFORM_MOV_MEMv_GPRv_DEFINED

#define XED_IFORM_MOV_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_MOV_MEMv_IMMz_DEFINED

#define XED_IFORM_MOV_MEMv_IMMz_DEFINED   1

◆ XED_IFORM_MOV_MEMv_OrAX_DEFINED

#define XED_IFORM_MOV_MEMv_OrAX_DEFINED   1

◆ XED_IFORM_MOV_MEMw_SEG_DEFINED

#define XED_IFORM_MOV_MEMw_SEG_DEFINED   1

◆ XED_IFORM_MOV_OrAX_MEMv_DEFINED

#define XED_IFORM_MOV_OrAX_MEMv_DEFINED   1

◆ XED_IFORM_MOV_SEG_GPR16_DEFINED

#define XED_IFORM_MOV_SEG_GPR16_DEFINED   1

◆ XED_IFORM_MOV_SEG_MEMw_DEFINED

#define XED_IFORM_MOV_SEG_MEMw_DEFINED   1

◆ XED_IFORM_MOVAPD_MEMpd_XMMpd_DEFINED

#define XED_IFORM_MOVAPD_MEMpd_XMMpd_DEFINED   1

◆ XED_IFORM_MOVAPD_XMMpd_MEMpd_DEFINED

#define XED_IFORM_MOVAPD_XMMpd_MEMpd_DEFINED   1

◆ XED_IFORM_MOVAPD_XMMpd_XMMpd_0F28_DEFINED

#define XED_IFORM_MOVAPD_XMMpd_XMMpd_0F28_DEFINED   1

◆ XED_IFORM_MOVAPD_XMMpd_XMMpd_0F29_DEFINED

#define XED_IFORM_MOVAPD_XMMpd_XMMpd_0F29_DEFINED   1

◆ XED_IFORM_MOVAPS_MEMps_XMMps_DEFINED

#define XED_IFORM_MOVAPS_MEMps_XMMps_DEFINED   1

◆ XED_IFORM_MOVAPS_XMMps_MEMps_DEFINED

#define XED_IFORM_MOVAPS_XMMps_MEMps_DEFINED   1

◆ XED_IFORM_MOVAPS_XMMps_XMMps_0F28_DEFINED

#define XED_IFORM_MOVAPS_XMMps_XMMps_0F28_DEFINED   1

◆ XED_IFORM_MOVAPS_XMMps_XMMps_0F29_DEFINED

#define XED_IFORM_MOVAPS_XMMps_XMMps_0F29_DEFINED   1

◆ XED_IFORM_MOVBE_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_MOVBE_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_MOVBE_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_MOVBE_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_MOVBE_GPRv_MEMv_DEFINED

#define XED_IFORM_MOVBE_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_MOVBE_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_MOVBE_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_MOVBE_MEMv_GPRv_DEFINED

#define XED_IFORM_MOVBE_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_MOVD_GPR32_MMXd_DEFINED

#define XED_IFORM_MOVD_GPR32_MMXd_DEFINED   1

◆ XED_IFORM_MOVD_GPR32_XMMd_DEFINED

#define XED_IFORM_MOVD_GPR32_XMMd_DEFINED   1

◆ XED_IFORM_MOVD_MEMd_MMXd_DEFINED

#define XED_IFORM_MOVD_MEMd_MMXd_DEFINED   1

◆ XED_IFORM_MOVD_MEMd_XMMd_DEFINED

#define XED_IFORM_MOVD_MEMd_XMMd_DEFINED   1

◆ XED_IFORM_MOVD_MMXq_GPR32_DEFINED

#define XED_IFORM_MOVD_MMXq_GPR32_DEFINED   1

◆ XED_IFORM_MOVD_MMXq_MEMd_DEFINED

#define XED_IFORM_MOVD_MMXq_MEMd_DEFINED   1

◆ XED_IFORM_MOVD_XMMdq_GPR32_DEFINED

#define XED_IFORM_MOVD_XMMdq_GPR32_DEFINED   1

◆ XED_IFORM_MOVD_XMMdq_MEMd_DEFINED

#define XED_IFORM_MOVD_XMMdq_MEMd_DEFINED   1

◆ XED_IFORM_MOVDDUP_XMMdq_MEMq_DEFINED

#define XED_IFORM_MOVDDUP_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_MOVDDUP_XMMdq_XMMq_DEFINED

#define XED_IFORM_MOVDDUP_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_MOVDIR64B_GPRa_MEM_DEFINED

#define XED_IFORM_MOVDIR64B_GPRa_MEM_DEFINED   1

◆ XED_IFORM_MOVDIR64B_GPRav_MEMu32_APX_DEFINED

#define XED_IFORM_MOVDIR64B_GPRav_MEMu32_APX_DEFINED   1

◆ XED_IFORM_MOVDIRI_MEMu32_GPR32u32_DEFINED

#define XED_IFORM_MOVDIRI_MEMu32_GPR32u32_DEFINED   1

◆ XED_IFORM_MOVDIRI_MEMu64_GPR64u64_DEFINED

#define XED_IFORM_MOVDIRI_MEMu64_GPR64u64_DEFINED   1

◆ XED_IFORM_MOVDIRI_MEMyu_GPRyu_APX_DEFINED

#define XED_IFORM_MOVDIRI_MEMyu_GPRyu_APX_DEFINED   1

◆ XED_IFORM_MOVDQ2Q_MMXq_XMMq_DEFINED

#define XED_IFORM_MOVDQ2Q_MMXq_XMMq_DEFINED   1

◆ XED_IFORM_MOVDQA_MEMdq_XMMdq_DEFINED

#define XED_IFORM_MOVDQA_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_MOVDQA_XMMdq_MEMdq_DEFINED

#define XED_IFORM_MOVDQA_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_MOVDQA_XMMdq_XMMdq_0F6F_DEFINED

#define XED_IFORM_MOVDQA_XMMdq_XMMdq_0F6F_DEFINED   1

◆ XED_IFORM_MOVDQA_XMMdq_XMMdq_0F7F_DEFINED

#define XED_IFORM_MOVDQA_XMMdq_XMMdq_0F7F_DEFINED   1

◆ XED_IFORM_MOVDQU_MEMdq_XMMdq_DEFINED

#define XED_IFORM_MOVDQU_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_MOVDQU_XMMdq_MEMdq_DEFINED

#define XED_IFORM_MOVDQU_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_MOVDQU_XMMdq_XMMdq_0F6F_DEFINED

#define XED_IFORM_MOVDQU_XMMdq_XMMdq_0F6F_DEFINED   1

◆ XED_IFORM_MOVDQU_XMMdq_XMMdq_0F7F_DEFINED

#define XED_IFORM_MOVDQU_XMMdq_XMMdq_0F7F_DEFINED   1

◆ XED_IFORM_MOVHLPS_XMMq_XMMq_DEFINED

#define XED_IFORM_MOVHLPS_XMMq_XMMq_DEFINED   1

◆ XED_IFORM_MOVHPD_MEMq_XMMsd_DEFINED

#define XED_IFORM_MOVHPD_MEMq_XMMsd_DEFINED   1

◆ XED_IFORM_MOVHPD_XMMsd_MEMq_DEFINED

#define XED_IFORM_MOVHPD_XMMsd_MEMq_DEFINED   1

◆ XED_IFORM_MOVHPS_MEMq_XMMps_DEFINED

#define XED_IFORM_MOVHPS_MEMq_XMMps_DEFINED   1

◆ XED_IFORM_MOVHPS_XMMq_MEMq_DEFINED

#define XED_IFORM_MOVHPS_XMMq_MEMq_DEFINED   1

◆ XED_IFORM_MOVLHPS_XMMq_XMMq_DEFINED

#define XED_IFORM_MOVLHPS_XMMq_XMMq_DEFINED   1

◆ XED_IFORM_MOVLPD_MEMq_XMMsd_DEFINED

#define XED_IFORM_MOVLPD_MEMq_XMMsd_DEFINED   1

◆ XED_IFORM_MOVLPD_XMMsd_MEMq_DEFINED

#define XED_IFORM_MOVLPD_XMMsd_MEMq_DEFINED   1

◆ XED_IFORM_MOVLPS_MEMq_XMMq_DEFINED

#define XED_IFORM_MOVLPS_MEMq_XMMq_DEFINED   1

◆ XED_IFORM_MOVLPS_XMMq_MEMq_DEFINED

#define XED_IFORM_MOVLPS_XMMq_MEMq_DEFINED   1

◆ XED_IFORM_MOVMSKPD_GPR32_XMMpd_DEFINED

#define XED_IFORM_MOVMSKPD_GPR32_XMMpd_DEFINED   1

◆ XED_IFORM_MOVMSKPS_GPR32_XMMps_DEFINED

#define XED_IFORM_MOVMSKPS_GPR32_XMMps_DEFINED   1

◆ XED_IFORM_MOVNTDQ_MEMdq_XMMdq_DEFINED

#define XED_IFORM_MOVNTDQ_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_MOVNTDQA_XMMdq_MEMdq_DEFINED

#define XED_IFORM_MOVNTDQA_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_MOVNTI_MEMd_GPR32_DEFINED

#define XED_IFORM_MOVNTI_MEMd_GPR32_DEFINED   1

◆ XED_IFORM_MOVNTI_MEMq_GPR64_DEFINED

#define XED_IFORM_MOVNTI_MEMq_GPR64_DEFINED   1

◆ XED_IFORM_MOVNTPD_MEMdq_XMMpd_DEFINED

#define XED_IFORM_MOVNTPD_MEMdq_XMMpd_DEFINED   1

◆ XED_IFORM_MOVNTPS_MEMdq_XMMps_DEFINED

#define XED_IFORM_MOVNTPS_MEMdq_XMMps_DEFINED   1

◆ XED_IFORM_MOVNTQ_MEMq_MMXq_DEFINED

#define XED_IFORM_MOVNTQ_MEMq_MMXq_DEFINED   1

◆ XED_IFORM_MOVNTSD_MEMq_XMMq_DEFINED

#define XED_IFORM_MOVNTSD_MEMq_XMMq_DEFINED   1

◆ XED_IFORM_MOVNTSS_MEMd_XMMd_DEFINED

#define XED_IFORM_MOVNTSS_MEMd_XMMd_DEFINED   1

◆ XED_IFORM_MOVQ2DQ_XMMdq_MMXq_DEFINED

#define XED_IFORM_MOVQ2DQ_XMMdq_MMXq_DEFINED   1

◆ XED_IFORM_MOVQ_GPR64_MMXq_DEFINED

#define XED_IFORM_MOVQ_GPR64_MMXq_DEFINED   1

◆ XED_IFORM_MOVQ_GPR64_XMMq_DEFINED

#define XED_IFORM_MOVQ_GPR64_XMMq_DEFINED   1

◆ XED_IFORM_MOVQ_MEMq_MMXq_0F7E_DEFINED

#define XED_IFORM_MOVQ_MEMq_MMXq_0F7E_DEFINED   1

◆ XED_IFORM_MOVQ_MEMq_MMXq_0F7F_DEFINED

#define XED_IFORM_MOVQ_MEMq_MMXq_0F7F_DEFINED   1

◆ XED_IFORM_MOVQ_MEMq_XMMq_0F7E_DEFINED

#define XED_IFORM_MOVQ_MEMq_XMMq_0F7E_DEFINED   1

◆ XED_IFORM_MOVQ_MEMq_XMMq_0FD6_DEFINED

#define XED_IFORM_MOVQ_MEMq_XMMq_0FD6_DEFINED   1

◆ XED_IFORM_MOVQ_MMXq_GPR64_DEFINED

#define XED_IFORM_MOVQ_MMXq_GPR64_DEFINED   1

◆ XED_IFORM_MOVQ_MMXq_MEMq_0F6E_DEFINED

#define XED_IFORM_MOVQ_MMXq_MEMq_0F6E_DEFINED   1

◆ XED_IFORM_MOVQ_MMXq_MEMq_0F6F_DEFINED

#define XED_IFORM_MOVQ_MMXq_MEMq_0F6F_DEFINED   1

◆ XED_IFORM_MOVQ_MMXq_MMXq_0F6F_DEFINED

#define XED_IFORM_MOVQ_MMXq_MMXq_0F6F_DEFINED   1

◆ XED_IFORM_MOVQ_MMXq_MMXq_0F7F_DEFINED

#define XED_IFORM_MOVQ_MMXq_MMXq_0F7F_DEFINED   1

◆ XED_IFORM_MOVQ_XMMdq_GPR64_DEFINED

#define XED_IFORM_MOVQ_XMMdq_GPR64_DEFINED   1

◆ XED_IFORM_MOVQ_XMMdq_MEMq_0F6E_DEFINED

#define XED_IFORM_MOVQ_XMMdq_MEMq_0F6E_DEFINED   1

◆ XED_IFORM_MOVQ_XMMdq_MEMq_0F7E_DEFINED

#define XED_IFORM_MOVQ_XMMdq_MEMq_0F7E_DEFINED   1

◆ XED_IFORM_MOVQ_XMMdq_XMMq_0F7E_DEFINED

#define XED_IFORM_MOVQ_XMMdq_XMMq_0F7E_DEFINED   1

◆ XED_IFORM_MOVQ_XMMdq_XMMq_0FD6_DEFINED

#define XED_IFORM_MOVQ_XMMdq_XMMq_0FD6_DEFINED   1

◆ XED_IFORM_MOVRS_GPR8i8_MEMi8_APX_DEFINED

#define XED_IFORM_MOVRS_GPR8i8_MEMi8_APX_DEFINED   1

◆ XED_IFORM_MOVRS_GPR8i8_MEMi8_DEFINED

#define XED_IFORM_MOVRS_GPR8i8_MEMi8_DEFINED   1

◆ XED_IFORM_MOVRS_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_MOVRS_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_MOVRS_GPRv_MEMv_DEFINED

#define XED_IFORM_MOVRS_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_MOVSB_DEFINED

#define XED_IFORM_MOVSB_DEFINED   1

◆ XED_IFORM_MOVSD_DEFINED

#define XED_IFORM_MOVSD_DEFINED   1

◆ XED_IFORM_MOVSD_XMM_MEMsd_XMMsd_DEFINED

#define XED_IFORM_MOVSD_XMM_MEMsd_XMMsd_DEFINED   1

◆ XED_IFORM_MOVSD_XMM_XMMdq_MEMsd_DEFINED

#define XED_IFORM_MOVSD_XMM_XMMdq_MEMsd_DEFINED   1

◆ XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F10_DEFINED

#define XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F10_DEFINED   1

◆ XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F11_DEFINED

#define XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F11_DEFINED   1

◆ XED_IFORM_MOVSHDUP_XMMps_MEMps_DEFINED

#define XED_IFORM_MOVSHDUP_XMMps_MEMps_DEFINED   1

◆ XED_IFORM_MOVSHDUP_XMMps_XMMps_DEFINED

#define XED_IFORM_MOVSHDUP_XMMps_XMMps_DEFINED   1

◆ XED_IFORM_MOVSLDUP_XMMps_MEMps_DEFINED

#define XED_IFORM_MOVSLDUP_XMMps_MEMps_DEFINED   1

◆ XED_IFORM_MOVSLDUP_XMMps_XMMps_DEFINED

#define XED_IFORM_MOVSLDUP_XMMps_XMMps_DEFINED   1

◆ XED_IFORM_MOVSQ_DEFINED

#define XED_IFORM_MOVSQ_DEFINED   1

◆ XED_IFORM_MOVSS_MEMss_XMMss_DEFINED

#define XED_IFORM_MOVSS_MEMss_XMMss_DEFINED   1

◆ XED_IFORM_MOVSS_XMMdq_MEMss_DEFINED

#define XED_IFORM_MOVSS_XMMdq_MEMss_DEFINED   1

◆ XED_IFORM_MOVSS_XMMss_XMMss_0F10_DEFINED

#define XED_IFORM_MOVSS_XMMss_XMMss_0F10_DEFINED   1

◆ XED_IFORM_MOVSS_XMMss_XMMss_0F11_DEFINED

#define XED_IFORM_MOVSS_XMMss_XMMss_0F11_DEFINED   1

◆ XED_IFORM_MOVSW_DEFINED

#define XED_IFORM_MOVSW_DEFINED   1

◆ XED_IFORM_MOVSX_GPR16_MEMw_DEFINED

#define XED_IFORM_MOVSX_GPR16_MEMw_DEFINED   1

◆ XED_IFORM_MOVSX_GPR32_MEMw_DEFINED

#define XED_IFORM_MOVSX_GPR32_MEMw_DEFINED   1

◆ XED_IFORM_MOVSX_GPR64_MEMw_DEFINED

#define XED_IFORM_MOVSX_GPR64_MEMw_DEFINED   1

◆ XED_IFORM_MOVSX_GPRv_GPR16_DEFINED

#define XED_IFORM_MOVSX_GPRv_GPR16_DEFINED   1

◆ XED_IFORM_MOVSX_GPRv_GPR8_DEFINED

#define XED_IFORM_MOVSX_GPRv_GPR8_DEFINED   1

◆ XED_IFORM_MOVSX_GPRv_MEMb_DEFINED

#define XED_IFORM_MOVSX_GPRv_MEMb_DEFINED   1

◆ XED_IFORM_MOVSX_GPRv_MEMw_DEFINED

#define XED_IFORM_MOVSX_GPRv_MEMw_DEFINED   1

◆ XED_IFORM_MOVSXD_GPR64_MEMd_DEFINED

#define XED_IFORM_MOVSXD_GPR64_MEMd_DEFINED   1

◆ XED_IFORM_MOVSXD_GPRv_GPRz_DEFINED

#define XED_IFORM_MOVSXD_GPRv_GPRz_DEFINED   1

◆ XED_IFORM_MOVSXD_GPRz_MEMz_DEFINED

#define XED_IFORM_MOVSXD_GPRz_MEMz_DEFINED   1

◆ XED_IFORM_MOVUPD_MEMpd_XMMpd_DEFINED

#define XED_IFORM_MOVUPD_MEMpd_XMMpd_DEFINED   1

◆ XED_IFORM_MOVUPD_XMMpd_MEMpd_DEFINED

#define XED_IFORM_MOVUPD_XMMpd_MEMpd_DEFINED   1

◆ XED_IFORM_MOVUPD_XMMpd_XMMpd_0F10_DEFINED

#define XED_IFORM_MOVUPD_XMMpd_XMMpd_0F10_DEFINED   1

◆ XED_IFORM_MOVUPD_XMMpd_XMMpd_0F11_DEFINED

#define XED_IFORM_MOVUPD_XMMpd_XMMpd_0F11_DEFINED   1

◆ XED_IFORM_MOVUPS_MEMps_XMMps_DEFINED

#define XED_IFORM_MOVUPS_MEMps_XMMps_DEFINED   1

◆ XED_IFORM_MOVUPS_XMMps_MEMps_DEFINED

#define XED_IFORM_MOVUPS_XMMps_MEMps_DEFINED   1

◆ XED_IFORM_MOVUPS_XMMps_XMMps_0F10_DEFINED

#define XED_IFORM_MOVUPS_XMMps_XMMps_0F10_DEFINED   1

◆ XED_IFORM_MOVUPS_XMMps_XMMps_0F11_DEFINED

#define XED_IFORM_MOVUPS_XMMps_XMMps_0F11_DEFINED   1

◆ XED_IFORM_MOVZX_GPR16_MEMw_DEFINED

#define XED_IFORM_MOVZX_GPR16_MEMw_DEFINED   1

◆ XED_IFORM_MOVZX_GPR32_MEMw_DEFINED

#define XED_IFORM_MOVZX_GPR32_MEMw_DEFINED   1

◆ XED_IFORM_MOVZX_GPR64_MEMw_DEFINED

#define XED_IFORM_MOVZX_GPR64_MEMw_DEFINED   1

◆ XED_IFORM_MOVZX_GPRv_GPR16_DEFINED

#define XED_IFORM_MOVZX_GPRv_GPR16_DEFINED   1

◆ XED_IFORM_MOVZX_GPRv_GPR8_DEFINED

#define XED_IFORM_MOVZX_GPRv_GPR8_DEFINED   1

◆ XED_IFORM_MOVZX_GPRv_MEMb_DEFINED

#define XED_IFORM_MOVZX_GPRv_MEMb_DEFINED   1

◆ XED_IFORM_MOVZX_GPRv_MEMw_DEFINED

#define XED_IFORM_MOVZX_GPRv_MEMw_DEFINED   1

◆ XED_IFORM_MPSADBW_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_MPSADBW_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_MUL_GPR8_DEFINED

#define XED_IFORM_MUL_GPR8_DEFINED   1

◆ XED_IFORM_MUL_GPR8i8_APX_DEFINED

#define XED_IFORM_MUL_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_MUL_GPRv_APX_DEFINED

#define XED_IFORM_MUL_GPRv_APX_DEFINED   1

◆ XED_IFORM_MUL_GPRv_DEFINED

#define XED_IFORM_MUL_GPRv_DEFINED   1

◆ XED_IFORM_MUL_MEMb_DEFINED

#define XED_IFORM_MUL_MEMb_DEFINED   1

◆ XED_IFORM_MUL_MEMi8_APX_DEFINED

#define XED_IFORM_MUL_MEMi8_APX_DEFINED   1

◆ XED_IFORM_MUL_MEMv_APX_DEFINED

#define XED_IFORM_MUL_MEMv_APX_DEFINED   1

◆ XED_IFORM_MUL_MEMv_DEFINED

#define XED_IFORM_MUL_MEMv_DEFINED   1

◆ XED_IFORM_MULPD_XMMpd_MEMpd_DEFINED

#define XED_IFORM_MULPD_XMMpd_MEMpd_DEFINED   1

◆ XED_IFORM_MULPD_XMMpd_XMMpd_DEFINED

#define XED_IFORM_MULPD_XMMpd_XMMpd_DEFINED   1

◆ XED_IFORM_MULPS_XMMps_MEMps_DEFINED

#define XED_IFORM_MULPS_XMMps_MEMps_DEFINED   1

◆ XED_IFORM_MULPS_XMMps_XMMps_DEFINED

#define XED_IFORM_MULPS_XMMps_XMMps_DEFINED   1

◆ XED_IFORM_MULSD_XMMsd_MEMsd_DEFINED

#define XED_IFORM_MULSD_XMMsd_MEMsd_DEFINED   1

◆ XED_IFORM_MULSD_XMMsd_XMMsd_DEFINED

#define XED_IFORM_MULSD_XMMsd_XMMsd_DEFINED   1

◆ XED_IFORM_MULSS_XMMss_MEMss_DEFINED

#define XED_IFORM_MULSS_XMMss_MEMss_DEFINED   1

◆ XED_IFORM_MULSS_XMMss_XMMss_DEFINED

#define XED_IFORM_MULSS_XMMss_XMMss_DEFINED   1

◆ XED_IFORM_MULX_GPR32d_GPR32d_GPR32d_DEFINED

#define XED_IFORM_MULX_GPR32d_GPR32d_GPR32d_DEFINED   1

◆ XED_IFORM_MULX_GPR32d_GPR32d_MEMd_DEFINED

#define XED_IFORM_MULX_GPR32d_GPR32d_MEMd_DEFINED   1

◆ XED_IFORM_MULX_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED

#define XED_IFORM_MULX_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED   1

◆ XED_IFORM_MULX_GPR32i32_GPR32i32_MEMi32_APX_DEFINED

#define XED_IFORM_MULX_GPR32i32_GPR32i32_MEMi32_APX_DEFINED   1

◆ XED_IFORM_MULX_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED

#define XED_IFORM_MULX_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED   1

◆ XED_IFORM_MULX_GPR64i64_GPR64i64_MEMi64_APX_DEFINED

#define XED_IFORM_MULX_GPR64i64_GPR64i64_MEMi64_APX_DEFINED   1

◆ XED_IFORM_MULX_GPR64q_GPR64q_GPR64q_DEFINED

#define XED_IFORM_MULX_GPR64q_GPR64q_GPR64q_DEFINED   1

◆ XED_IFORM_MULX_GPR64q_GPR64q_MEMq_DEFINED

#define XED_IFORM_MULX_GPR64q_GPR64q_MEMq_DEFINED   1

◆ XED_IFORM_MWAIT_DEFINED

#define XED_IFORM_MWAIT_DEFINED   1

◆ XED_IFORM_MWAITX_DEFINED

#define XED_IFORM_MWAITX_DEFINED   1

◆ XED_IFORM_NEG_GPR8_DEFINED

#define XED_IFORM_NEG_GPR8_DEFINED   1

◆ XED_IFORM_NEG_GPR8i8_APX_DEFINED

#define XED_IFORM_NEG_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_NEG_GPR8i8_GPR8i8_APX_DEFINED

#define XED_IFORM_NEG_GPR8i8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_NEG_GPR8i8_MEMi8_APX_DEFINED

#define XED_IFORM_NEG_GPR8i8_MEMi8_APX_DEFINED   1

◆ XED_IFORM_NEG_GPRv_APX_DEFINED

#define XED_IFORM_NEG_GPRv_APX_DEFINED   1

◆ XED_IFORM_NEG_GPRv_DEFINED

#define XED_IFORM_NEG_GPRv_DEFINED   1

◆ XED_IFORM_NEG_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_NEG_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_NEG_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_NEG_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_NEG_LOCK_MEMb_DEFINED

#define XED_IFORM_NEG_LOCK_MEMb_DEFINED   1

◆ XED_IFORM_NEG_LOCK_MEMv_DEFINED

#define XED_IFORM_NEG_LOCK_MEMv_DEFINED   1

◆ XED_IFORM_NEG_MEMb_DEFINED

#define XED_IFORM_NEG_MEMb_DEFINED   1

◆ XED_IFORM_NEG_MEMi8_APX_DEFINED

#define XED_IFORM_NEG_MEMi8_APX_DEFINED   1

◆ XED_IFORM_NEG_MEMv_APX_DEFINED

#define XED_IFORM_NEG_MEMv_APX_DEFINED   1

◆ XED_IFORM_NEG_MEMv_DEFINED

#define XED_IFORM_NEG_MEMv_DEFINED   1

◆ XED_IFORM_NOP_90_DEFINED

#define XED_IFORM_NOP_90_DEFINED   1

◆ XED_IFORM_NOP_GPRv_0F18r0_DEFINED

#define XED_IFORM_NOP_GPRv_0F18r0_DEFINED   1

◆ XED_IFORM_NOP_GPRv_0F18r1_DEFINED

#define XED_IFORM_NOP_GPRv_0F18r1_DEFINED   1

◆ XED_IFORM_NOP_GPRv_0F18r2_DEFINED

#define XED_IFORM_NOP_GPRv_0F18r2_DEFINED   1

◆ XED_IFORM_NOP_GPRv_0F18r3_DEFINED

#define XED_IFORM_NOP_GPRv_0F18r3_DEFINED   1

◆ XED_IFORM_NOP_GPRv_0F18r4_DEFINED

#define XED_IFORM_NOP_GPRv_0F18r4_DEFINED   1

◆ XED_IFORM_NOP_GPRv_0F18r5_DEFINED

#define XED_IFORM_NOP_GPRv_0F18r5_DEFINED   1

◆ XED_IFORM_NOP_GPRv_0F18r6_DEFINED

#define XED_IFORM_NOP_GPRv_0F18r6_DEFINED   1

◆ XED_IFORM_NOP_GPRv_0F18r7_DEFINED

#define XED_IFORM_NOP_GPRv_0F18r7_DEFINED   1

◆ XED_IFORM_NOP_GPRv_0F1F_DEFINED

#define XED_IFORM_NOP_GPRv_0F1F_DEFINED   1

◆ XED_IFORM_NOP_GPRv_GPRv_0F0D_DEFINED

#define XED_IFORM_NOP_GPRv_GPRv_0F0D_DEFINED   1

◆ XED_IFORM_NOP_GPRv_GPRv_0F19_DEFINED

#define XED_IFORM_NOP_GPRv_GPRv_0F19_DEFINED   1

◆ XED_IFORM_NOP_GPRv_GPRv_0F1A_DEFINED

#define XED_IFORM_NOP_GPRv_GPRv_0F1A_DEFINED   1

◆ XED_IFORM_NOP_GPRv_GPRv_0F1B_DEFINED

#define XED_IFORM_NOP_GPRv_GPRv_0F1B_DEFINED   1

◆ XED_IFORM_NOP_GPRv_GPRv_0F1C_DEFINED

#define XED_IFORM_NOP_GPRv_GPRv_0F1C_DEFINED   1

◆ XED_IFORM_NOP_GPRv_GPRv_0F1D_DEFINED

#define XED_IFORM_NOP_GPRv_GPRv_0F1D_DEFINED   1

◆ XED_IFORM_NOP_GPRv_GPRv_0F1E_DEFINED

#define XED_IFORM_NOP_GPRv_GPRv_0F1E_DEFINED   1

◆ XED_IFORM_NOP_GPRv_MEM_0F1B_DEFINED

#define XED_IFORM_NOP_GPRv_MEM_0F1B_DEFINED   1

◆ XED_IFORM_NOP_GPRv_MEMv_0F1A_DEFINED

#define XED_IFORM_NOP_GPRv_MEMv_0F1A_DEFINED   1

◆ XED_IFORM_NOP_MEMv_0F18r4_DEFINED

#define XED_IFORM_NOP_MEMv_0F18r4_DEFINED   1

◆ XED_IFORM_NOP_MEMv_0F18r5_DEFINED

#define XED_IFORM_NOP_MEMv_0F18r5_DEFINED   1

◆ XED_IFORM_NOP_MEMv_0F18r6_DEFINED

#define XED_IFORM_NOP_MEMv_0F18r6_DEFINED   1

◆ XED_IFORM_NOP_MEMv_0F18r7_DEFINED

#define XED_IFORM_NOP_MEMv_0F18r7_DEFINED   1

◆ XED_IFORM_NOP_MEMv_0F1F_DEFINED

#define XED_IFORM_NOP_MEMv_0F1F_DEFINED   1

◆ XED_IFORM_NOP_MEMv_GPRv_0F19_DEFINED

#define XED_IFORM_NOP_MEMv_GPRv_0F19_DEFINED   1

◆ XED_IFORM_NOP_MEMv_GPRv_0F1C_DEFINED

#define XED_IFORM_NOP_MEMv_GPRv_0F1C_DEFINED   1

◆ XED_IFORM_NOP_MEMv_GPRv_0F1D_DEFINED

#define XED_IFORM_NOP_MEMv_GPRv_0F1D_DEFINED   1

◆ XED_IFORM_NOP_MEMv_GPRv_0F1E_DEFINED

#define XED_IFORM_NOP_MEMv_GPRv_0F1E_DEFINED   1

◆ XED_IFORM_NOT_GPR8_DEFINED

#define XED_IFORM_NOT_GPR8_DEFINED   1

◆ XED_IFORM_NOT_GPR8i8_APX_DEFINED

#define XED_IFORM_NOT_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_NOT_GPR8i8_GPR8i8_APX_DEFINED

#define XED_IFORM_NOT_GPR8i8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_NOT_GPR8i8_MEMi8_APX_DEFINED

#define XED_IFORM_NOT_GPR8i8_MEMi8_APX_DEFINED   1

◆ XED_IFORM_NOT_GPRv_APX_DEFINED

#define XED_IFORM_NOT_GPRv_APX_DEFINED   1

◆ XED_IFORM_NOT_GPRv_DEFINED

#define XED_IFORM_NOT_GPRv_DEFINED   1

◆ XED_IFORM_NOT_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_NOT_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_NOT_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_NOT_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_NOT_LOCK_MEMb_DEFINED

#define XED_IFORM_NOT_LOCK_MEMb_DEFINED   1

◆ XED_IFORM_NOT_LOCK_MEMv_DEFINED

#define XED_IFORM_NOT_LOCK_MEMv_DEFINED   1

◆ XED_IFORM_NOT_MEMb_DEFINED

#define XED_IFORM_NOT_MEMb_DEFINED   1

◆ XED_IFORM_NOT_MEMi8_APX_DEFINED

#define XED_IFORM_NOT_MEMi8_APX_DEFINED   1

◆ XED_IFORM_NOT_MEMv_APX_DEFINED

#define XED_IFORM_NOT_MEMv_APX_DEFINED   1

◆ XED_IFORM_NOT_MEMv_DEFINED

#define XED_IFORM_NOT_MEMv_DEFINED   1

◆ XED_IFORM_OR_AL_IMMb_DEFINED

#define XED_IFORM_OR_AL_IMMb_DEFINED   1

◆ XED_IFORM_OR_GPR8_GPR8_08_DEFINED

#define XED_IFORM_OR_GPR8_GPR8_08_DEFINED   1

◆ XED_IFORM_OR_GPR8_GPR8_0A_DEFINED

#define XED_IFORM_OR_GPR8_GPR8_0A_DEFINED   1

◆ XED_IFORM_OR_GPR8_IMMb_80r1_DEFINED

#define XED_IFORM_OR_GPR8_IMMb_80r1_DEFINED   1

◆ XED_IFORM_OR_GPR8_IMMb_82r1_DEFINED

#define XED_IFORM_OR_GPR8_IMMb_82r1_DEFINED   1

◆ XED_IFORM_OR_GPR8_MEMb_DEFINED

#define XED_IFORM_OR_GPR8_MEMb_DEFINED   1

◆ XED_IFORM_OR_GPR8i8_GPR8i8_APX_DEFINED

#define XED_IFORM_OR_GPR8i8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_OR_GPR8i8_GPR8i8_GPR8i8_APX_DEFINED

#define XED_IFORM_OR_GPR8i8_GPR8i8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_OR_GPR8i8_GPR8i8_IMM8_APX_DEFINED

#define XED_IFORM_OR_GPR8i8_GPR8i8_IMM8_APX_DEFINED   1

◆ XED_IFORM_OR_GPR8i8_GPR8i8_MEMi8_APX_DEFINED

#define XED_IFORM_OR_GPR8i8_GPR8i8_MEMi8_APX_DEFINED   1

◆ XED_IFORM_OR_GPR8i8_IMM8_APX_DEFINED

#define XED_IFORM_OR_GPR8i8_IMM8_APX_DEFINED   1

◆ XED_IFORM_OR_GPR8i8_MEMi8_APX_DEFINED

#define XED_IFORM_OR_GPR8i8_MEMi8_APX_DEFINED   1

◆ XED_IFORM_OR_GPR8i8_MEMi8_GPR8i8_APX_DEFINED

#define XED_IFORM_OR_GPR8i8_MEMi8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_OR_GPR8i8_MEMi8_IMM8_APX_DEFINED

#define XED_IFORM_OR_GPR8i8_MEMi8_IMM8_APX_DEFINED   1

◆ XED_IFORM_OR_GPRv_GPRv_09_DEFINED

#define XED_IFORM_OR_GPRv_GPRv_09_DEFINED   1

◆ XED_IFORM_OR_GPRv_GPRv_0B_DEFINED

#define XED_IFORM_OR_GPRv_GPRv_0B_DEFINED   1

◆ XED_IFORM_OR_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_OR_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_OR_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_OR_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_OR_GPRv_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_OR_GPRv_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_OR_GPRv_GPRv_IMMz_APX_DEFINED

#define XED_IFORM_OR_GPRv_GPRv_IMMz_APX_DEFINED   1

◆ XED_IFORM_OR_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_OR_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_OR_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_OR_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_OR_GPRv_IMMb_DEFINED

#define XED_IFORM_OR_GPRv_IMMb_DEFINED   1

◆ XED_IFORM_OR_GPRv_IMMz_APX_DEFINED

#define XED_IFORM_OR_GPRv_IMMz_APX_DEFINED   1

◆ XED_IFORM_OR_GPRv_IMMz_DEFINED

#define XED_IFORM_OR_GPRv_IMMz_DEFINED   1

◆ XED_IFORM_OR_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_OR_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_OR_GPRv_MEMv_DEFINED

#define XED_IFORM_OR_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_OR_GPRv_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_OR_GPRv_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_OR_GPRv_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_OR_GPRv_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_OR_GPRv_MEMv_IMMz_APX_DEFINED

#define XED_IFORM_OR_GPRv_MEMv_IMMz_APX_DEFINED   1

◆ XED_IFORM_OR_LOCK_MEMb_GPR8_DEFINED

#define XED_IFORM_OR_LOCK_MEMb_GPR8_DEFINED   1

◆ XED_IFORM_OR_LOCK_MEMb_IMMb_80r1_DEFINED

#define XED_IFORM_OR_LOCK_MEMb_IMMb_80r1_DEFINED   1

◆ XED_IFORM_OR_LOCK_MEMb_IMMb_82r1_DEFINED

#define XED_IFORM_OR_LOCK_MEMb_IMMb_82r1_DEFINED   1

◆ XED_IFORM_OR_LOCK_MEMv_GPRv_DEFINED

#define XED_IFORM_OR_LOCK_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_OR_LOCK_MEMv_IMMb_DEFINED

#define XED_IFORM_OR_LOCK_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_OR_LOCK_MEMv_IMMz_DEFINED

#define XED_IFORM_OR_LOCK_MEMv_IMMz_DEFINED   1

◆ XED_IFORM_OR_MEMb_GPR8_DEFINED

#define XED_IFORM_OR_MEMb_GPR8_DEFINED   1

◆ XED_IFORM_OR_MEMb_IMMb_80r1_DEFINED

#define XED_IFORM_OR_MEMb_IMMb_80r1_DEFINED   1

◆ XED_IFORM_OR_MEMb_IMMb_82r1_DEFINED

#define XED_IFORM_OR_MEMb_IMMb_82r1_DEFINED   1

◆ XED_IFORM_OR_MEMi8_GPR8i8_APX_DEFINED

#define XED_IFORM_OR_MEMi8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_OR_MEMi8_IMM8_APX_DEFINED

#define XED_IFORM_OR_MEMi8_IMM8_APX_DEFINED   1

◆ XED_IFORM_OR_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_OR_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_OR_MEMv_GPRv_DEFINED

#define XED_IFORM_OR_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_OR_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_OR_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_OR_MEMv_IMMb_DEFINED

#define XED_IFORM_OR_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_OR_MEMv_IMMz_APX_DEFINED

#define XED_IFORM_OR_MEMv_IMMz_APX_DEFINED   1

◆ XED_IFORM_OR_MEMv_IMMz_DEFINED

#define XED_IFORM_OR_MEMv_IMMz_DEFINED   1

◆ XED_IFORM_OR_OrAX_IMMz_DEFINED

#define XED_IFORM_OR_OrAX_IMMz_DEFINED   1

◆ XED_IFORM_ORPD_XMMxuq_MEMxuq_DEFINED

#define XED_IFORM_ORPD_XMMxuq_MEMxuq_DEFINED   1

◆ XED_IFORM_ORPD_XMMxuq_XMMxuq_DEFINED

#define XED_IFORM_ORPD_XMMxuq_XMMxuq_DEFINED   1

◆ XED_IFORM_ORPS_XMMxud_MEMxud_DEFINED

#define XED_IFORM_ORPS_XMMxud_MEMxud_DEFINED   1

◆ XED_IFORM_ORPS_XMMxud_XMMxud_DEFINED

#define XED_IFORM_ORPS_XMMxud_XMMxud_DEFINED   1

◆ XED_IFORM_OUT_DX_AL_DEFINED

#define XED_IFORM_OUT_DX_AL_DEFINED   1

◆ XED_IFORM_OUT_DX_OeAX_DEFINED

#define XED_IFORM_OUT_DX_OeAX_DEFINED   1

◆ XED_IFORM_OUT_IMMb_AL_DEFINED

#define XED_IFORM_OUT_IMMb_AL_DEFINED   1

◆ XED_IFORM_OUT_IMMb_OeAX_DEFINED

#define XED_IFORM_OUT_IMMb_OeAX_DEFINED   1

◆ XED_IFORM_OUTSB_DEFINED

#define XED_IFORM_OUTSB_DEFINED   1

◆ XED_IFORM_OUTSD_DEFINED

#define XED_IFORM_OUTSD_DEFINED   1

◆ XED_IFORM_OUTSW_DEFINED

#define XED_IFORM_OUTSW_DEFINED   1

◆ XED_IFORM_PABSB_MMXq_MEMq_DEFINED

#define XED_IFORM_PABSB_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PABSB_MMXq_MMXq_DEFINED

#define XED_IFORM_PABSB_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PABSB_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PABSB_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PABSB_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PABSB_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PABSD_MMXq_MEMq_DEFINED

#define XED_IFORM_PABSD_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PABSD_MMXq_MMXq_DEFINED

#define XED_IFORM_PABSD_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PABSD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PABSD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PABSD_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PABSD_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PABSW_MMXq_MEMq_DEFINED

#define XED_IFORM_PABSW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PABSW_MMXq_MMXq_DEFINED

#define XED_IFORM_PABSW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PABSW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PABSW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PABSW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PABSW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PACKSSDW_MMXq_MEMq_DEFINED

#define XED_IFORM_PACKSSDW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PACKSSDW_MMXq_MMXq_DEFINED

#define XED_IFORM_PACKSSDW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PACKSSDW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PACKSSDW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PACKSSDW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PACKSSDW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PACKSSWB_MMXq_MEMq_DEFINED

#define XED_IFORM_PACKSSWB_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PACKSSWB_MMXq_MMXq_DEFINED

#define XED_IFORM_PACKSSWB_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PACKSSWB_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PACKSSWB_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PACKSSWB_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PACKSSWB_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PACKUSDW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PACKUSDW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PACKUSDW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PACKUSDW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PACKUSWB_MMXq_MEMq_DEFINED

#define XED_IFORM_PACKUSWB_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PACKUSWB_MMXq_MMXq_DEFINED

#define XED_IFORM_PACKUSWB_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PACKUSWB_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PACKUSWB_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PACKUSWB_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PACKUSWB_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PADDB_MMXq_MEMq_DEFINED

#define XED_IFORM_PADDB_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PADDB_MMXq_MMXq_DEFINED

#define XED_IFORM_PADDB_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PADDB_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PADDB_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PADDB_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PADDB_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PADDD_MMXq_MEMq_DEFINED

#define XED_IFORM_PADDD_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PADDD_MMXq_MMXq_DEFINED

#define XED_IFORM_PADDD_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PADDD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PADDD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PADDD_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PADDD_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PADDQ_MMXq_MEMq_DEFINED

#define XED_IFORM_PADDQ_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PADDQ_MMXq_MMXq_DEFINED

#define XED_IFORM_PADDQ_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PADDQ_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PADDQ_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PADDQ_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PADDQ_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PADDSB_MMXq_MEMq_DEFINED

#define XED_IFORM_PADDSB_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PADDSB_MMXq_MMXq_DEFINED

#define XED_IFORM_PADDSB_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PADDSB_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PADDSB_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PADDSB_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PADDSB_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PADDSW_MMXq_MEMq_DEFINED

#define XED_IFORM_PADDSW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PADDSW_MMXq_MMXq_DEFINED

#define XED_IFORM_PADDSW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PADDSW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PADDSW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PADDSW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PADDSW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PADDUSB_MMXq_MEMq_DEFINED

#define XED_IFORM_PADDUSB_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PADDUSB_MMXq_MMXq_DEFINED

#define XED_IFORM_PADDUSB_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PADDUSB_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PADDUSB_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PADDUSB_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PADDUSB_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PADDUSW_MMXq_MEMq_DEFINED

#define XED_IFORM_PADDUSW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PADDUSW_MMXq_MMXq_DEFINED

#define XED_IFORM_PADDUSW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PADDUSW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PADDUSW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PADDUSW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PADDUSW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PADDW_MMXq_MEMq_DEFINED

#define XED_IFORM_PADDW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PADDW_MMXq_MMXq_DEFINED

#define XED_IFORM_PADDW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PADDW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PADDW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PADDW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PADDW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PALIGNR_MMXq_MEMq_IMMb_DEFINED

#define XED_IFORM_PALIGNR_MMXq_MEMq_IMMb_DEFINED   1

◆ XED_IFORM_PALIGNR_MMXq_MMXq_IMMb_DEFINED

#define XED_IFORM_PALIGNR_MMXq_MMXq_IMMb_DEFINED   1

◆ XED_IFORM_PALIGNR_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_PALIGNR_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PAND_MMXq_MEMq_DEFINED

#define XED_IFORM_PAND_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PAND_MMXq_MMXq_DEFINED

#define XED_IFORM_PAND_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PAND_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PAND_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PAND_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PAND_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PANDN_MMXq_MEMq_DEFINED

#define XED_IFORM_PANDN_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PANDN_MMXq_MMXq_DEFINED

#define XED_IFORM_PANDN_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PANDN_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PANDN_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PANDN_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PANDN_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PAUSE_DEFINED

#define XED_IFORM_PAUSE_DEFINED   1

◆ XED_IFORM_PAVGB_MMXq_MEMq_DEFINED

#define XED_IFORM_PAVGB_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PAVGB_MMXq_MMXq_DEFINED

#define XED_IFORM_PAVGB_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PAVGB_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PAVGB_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PAVGB_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PAVGB_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PAVGUSB_MMXq_MEMq_DEFINED

#define XED_IFORM_PAVGUSB_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PAVGUSB_MMXq_MMXq_DEFINED

#define XED_IFORM_PAVGUSB_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PAVGW_MMXq_MEMq_DEFINED

#define XED_IFORM_PAVGW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PAVGW_MMXq_MMXq_DEFINED

#define XED_IFORM_PAVGW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PAVGW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PAVGW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PAVGW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PAVGW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PBLENDVB_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PBLENDVB_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PBLENDVB_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PBLENDVB_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PBLENDW_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_PBLENDW_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PBNDKB_DEFINED

#define XED_IFORM_PBNDKB_DEFINED   1

◆ XED_IFORM_PCLMULQDQ_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_PCLMULQDQ_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PCMPEQB_MMXq_MEMq_DEFINED

#define XED_IFORM_PCMPEQB_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PCMPEQB_MMXq_MMXq_DEFINED

#define XED_IFORM_PCMPEQB_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PCMPEQB_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PCMPEQB_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PCMPEQB_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PCMPEQB_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PCMPEQD_MMXq_MEMq_DEFINED

#define XED_IFORM_PCMPEQD_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PCMPEQD_MMXq_MMXq_DEFINED

#define XED_IFORM_PCMPEQD_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PCMPEQD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PCMPEQD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PCMPEQD_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PCMPEQD_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PCMPEQQ_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PCMPEQQ_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PCMPEQQ_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PCMPEQQ_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PCMPEQW_MMXq_MEMq_DEFINED

#define XED_IFORM_PCMPEQW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PCMPEQW_MMXq_MMXq_DEFINED

#define XED_IFORM_PCMPEQW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PCMPEQW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PCMPEQW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PCMPEQW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PCMPEQW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PCMPESTRI64_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_PCMPESTRI64_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_PCMPESTRI64_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_PCMPESTRI64_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PCMPESTRM64_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_PCMPESTRM64_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_PCMPESTRM64_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_PCMPESTRM64_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PCMPGTB_MMXq_MEMq_DEFINED

#define XED_IFORM_PCMPGTB_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PCMPGTB_MMXq_MMXq_DEFINED

#define XED_IFORM_PCMPGTB_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PCMPGTB_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PCMPGTB_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PCMPGTB_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PCMPGTB_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PCMPGTD_MMXq_MEMq_DEFINED

#define XED_IFORM_PCMPGTD_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PCMPGTD_MMXq_MMXq_DEFINED

#define XED_IFORM_PCMPGTD_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PCMPGTD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PCMPGTD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PCMPGTD_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PCMPGTD_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PCMPGTQ_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PCMPGTQ_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PCMPGTQ_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PCMPGTQ_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PCMPGTW_MMXq_MEMq_DEFINED

#define XED_IFORM_PCMPGTW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PCMPGTW_MMXq_MMXq_DEFINED

#define XED_IFORM_PCMPGTW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PCMPGTW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PCMPGTW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PCMPGTW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PCMPGTW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PCMPISTRI64_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_PCMPISTRI64_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_PCMPISTRI64_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_PCMPISTRI64_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PCMPISTRM_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_PCMPISTRM_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PCONFIG64_DEFINED

#define XED_IFORM_PCONFIG64_DEFINED   1

◆ XED_IFORM_PCONFIG_DEFINED

#define XED_IFORM_PCONFIG_DEFINED   1

◆ XED_IFORM_PDEP_GPR32d_GPR32d_GPR32d_DEFINED

#define XED_IFORM_PDEP_GPR32d_GPR32d_GPR32d_DEFINED   1

◆ XED_IFORM_PDEP_GPR32d_GPR32d_MEMd_DEFINED

#define XED_IFORM_PDEP_GPR32d_GPR32d_MEMd_DEFINED   1

◆ XED_IFORM_PDEP_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED

#define XED_IFORM_PDEP_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED   1

◆ XED_IFORM_PDEP_GPR32i32_GPR32i32_MEMi32_APX_DEFINED

#define XED_IFORM_PDEP_GPR32i32_GPR32i32_MEMi32_APX_DEFINED   1

◆ XED_IFORM_PDEP_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED

#define XED_IFORM_PDEP_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED   1

◆ XED_IFORM_PDEP_GPR64i64_GPR64i64_MEMi64_APX_DEFINED

#define XED_IFORM_PDEP_GPR64i64_GPR64i64_MEMi64_APX_DEFINED   1

◆ XED_IFORM_PDEP_GPR64q_GPR64q_GPR64q_DEFINED

#define XED_IFORM_PDEP_GPR64q_GPR64q_GPR64q_DEFINED   1

◆ XED_IFORM_PDEP_GPR64q_GPR64q_MEMq_DEFINED

#define XED_IFORM_PDEP_GPR64q_GPR64q_MEMq_DEFINED   1

◆ XED_IFORM_PEXT_GPR32d_GPR32d_GPR32d_DEFINED

#define XED_IFORM_PEXT_GPR32d_GPR32d_GPR32d_DEFINED   1

◆ XED_IFORM_PEXT_GPR32d_GPR32d_MEMd_DEFINED

#define XED_IFORM_PEXT_GPR32d_GPR32d_MEMd_DEFINED   1

◆ XED_IFORM_PEXT_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED

#define XED_IFORM_PEXT_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED   1

◆ XED_IFORM_PEXT_GPR32i32_GPR32i32_MEMi32_APX_DEFINED

#define XED_IFORM_PEXT_GPR32i32_GPR32i32_MEMi32_APX_DEFINED   1

◆ XED_IFORM_PEXT_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED

#define XED_IFORM_PEXT_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED   1

◆ XED_IFORM_PEXT_GPR64i64_GPR64i64_MEMi64_APX_DEFINED

#define XED_IFORM_PEXT_GPR64i64_GPR64i64_MEMi64_APX_DEFINED   1

◆ XED_IFORM_PEXT_GPR64q_GPR64q_GPR64q_DEFINED

#define XED_IFORM_PEXT_GPR64q_GPR64q_GPR64q_DEFINED   1

◆ XED_IFORM_PEXT_GPR64q_GPR64q_MEMq_DEFINED

#define XED_IFORM_PEXT_GPR64q_GPR64q_MEMq_DEFINED   1

◆ XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb_DEFINED

#define XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PEXTRB_MEMb_XMMdq_IMMb_DEFINED

#define XED_IFORM_PEXTRB_MEMb_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb_DEFINED

#define XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PEXTRD_MEMd_XMMdq_IMMb_DEFINED

#define XED_IFORM_PEXTRD_MEMd_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb_DEFINED

#define XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PEXTRQ_MEMq_XMMdq_IMMb_DEFINED

#define XED_IFORM_PEXTRQ_MEMq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PEXTRW_GPR32_MMXq_IMMb_DEFINED

#define XED_IFORM_PEXTRW_GPR32_MMXq_IMMb_DEFINED   1

◆ XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb_DEFINED

#define XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PEXTRW_SSE4_GPR32_XMMdq_IMMb_DEFINED

#define XED_IFORM_PEXTRW_SSE4_GPR32_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PEXTRW_SSE4_MEMw_XMMdq_IMMb_DEFINED

#define XED_IFORM_PEXTRW_SSE4_MEMw_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PF2ID_MMXq_MEMq_DEFINED

#define XED_IFORM_PF2ID_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PF2ID_MMXq_MMXq_DEFINED

#define XED_IFORM_PF2ID_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PF2IW_MMXq_MEMq_DEFINED

#define XED_IFORM_PF2IW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PF2IW_MMXq_MMXq_DEFINED

#define XED_IFORM_PF2IW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PFACC_MMXq_MEMq_DEFINED

#define XED_IFORM_PFACC_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PFACC_MMXq_MMXq_DEFINED

#define XED_IFORM_PFACC_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PFADD_MMXq_MEMq_DEFINED

#define XED_IFORM_PFADD_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PFADD_MMXq_MMXq_DEFINED

#define XED_IFORM_PFADD_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PFCMPEQ_MMXq_MEMq_DEFINED

#define XED_IFORM_PFCMPEQ_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PFCMPEQ_MMXq_MMXq_DEFINED

#define XED_IFORM_PFCMPEQ_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PFCMPGE_MMXq_MEMq_DEFINED

#define XED_IFORM_PFCMPGE_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PFCMPGE_MMXq_MMXq_DEFINED

#define XED_IFORM_PFCMPGE_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PFCMPGT_MMXq_MEMq_DEFINED

#define XED_IFORM_PFCMPGT_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PFCMPGT_MMXq_MMXq_DEFINED

#define XED_IFORM_PFCMPGT_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PFMAX_MMXq_MEMq_DEFINED

#define XED_IFORM_PFMAX_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PFMAX_MMXq_MMXq_DEFINED

#define XED_IFORM_PFMAX_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PFMIN_MMXq_MEMq_DEFINED

#define XED_IFORM_PFMIN_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PFMIN_MMXq_MMXq_DEFINED

#define XED_IFORM_PFMIN_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PFMUL_MMXq_MEMq_DEFINED

#define XED_IFORM_PFMUL_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PFMUL_MMXq_MMXq_DEFINED

#define XED_IFORM_PFMUL_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PFNACC_MMXq_MEMq_DEFINED

#define XED_IFORM_PFNACC_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PFNACC_MMXq_MMXq_DEFINED

#define XED_IFORM_PFNACC_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PFPNACC_MMXq_MEMq_DEFINED

#define XED_IFORM_PFPNACC_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PFPNACC_MMXq_MMXq_DEFINED

#define XED_IFORM_PFPNACC_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PFRCP_MMXq_MEMq_DEFINED

#define XED_IFORM_PFRCP_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PFRCP_MMXq_MMXq_DEFINED

#define XED_IFORM_PFRCP_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PFRCPIT1_MMXq_MEMq_DEFINED

#define XED_IFORM_PFRCPIT1_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PFRCPIT1_MMXq_MMXq_DEFINED

#define XED_IFORM_PFRCPIT1_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PFRCPIT2_MMXq_MEMq_DEFINED

#define XED_IFORM_PFRCPIT2_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PFRCPIT2_MMXq_MMXq_DEFINED

#define XED_IFORM_PFRCPIT2_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PFRSQIT1_MMXq_MEMq_DEFINED

#define XED_IFORM_PFRSQIT1_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PFRSQIT1_MMXq_MMXq_DEFINED

#define XED_IFORM_PFRSQIT1_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PFRSQRT_MMXq_MEMq_DEFINED

#define XED_IFORM_PFRSQRT_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PFRSQRT_MMXq_MMXq_DEFINED

#define XED_IFORM_PFRSQRT_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PFSUB_MMXq_MEMq_DEFINED

#define XED_IFORM_PFSUB_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PFSUB_MMXq_MMXq_DEFINED

#define XED_IFORM_PFSUB_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PFSUBR_MMXq_MEMq_DEFINED

#define XED_IFORM_PFSUBR_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PFSUBR_MMXq_MMXq_DEFINED

#define XED_IFORM_PFSUBR_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PHADDD_MMXq_MEMq_DEFINED

#define XED_IFORM_PHADDD_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PHADDD_MMXq_MMXq_DEFINED

#define XED_IFORM_PHADDD_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PHADDD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PHADDD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PHADDD_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PHADDD_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PHADDSW_MMXq_MEMq_DEFINED

#define XED_IFORM_PHADDSW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PHADDSW_MMXq_MMXq_DEFINED

#define XED_IFORM_PHADDSW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PHADDSW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PHADDSW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PHADDSW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PHADDSW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PHADDW_MMXq_MEMq_DEFINED

#define XED_IFORM_PHADDW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PHADDW_MMXq_MMXq_DEFINED

#define XED_IFORM_PHADDW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PHADDW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PHADDW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PHADDW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PHADDW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PHMINPOSUW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PHMINPOSUW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PHMINPOSUW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PHMINPOSUW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PHSUBD_MMXq_MEMq_DEFINED

#define XED_IFORM_PHSUBD_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PHSUBD_MMXq_MMXq_DEFINED

#define XED_IFORM_PHSUBD_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PHSUBD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PHSUBD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PHSUBD_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PHSUBD_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PHSUBSW_MMXq_MEMq_DEFINED

#define XED_IFORM_PHSUBSW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PHSUBSW_MMXq_MMXq_DEFINED

#define XED_IFORM_PHSUBSW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PHSUBSW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PHSUBSW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PHSUBSW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PHSUBSW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PHSUBW_MMXq_MEMq_DEFINED

#define XED_IFORM_PHSUBW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PHSUBW_MMXq_MMXq_DEFINED

#define XED_IFORM_PHSUBW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PHSUBW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PHSUBW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PHSUBW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PHSUBW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PI2FD_MMXq_MEMq_DEFINED

#define XED_IFORM_PI2FD_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PI2FD_MMXq_MMXq_DEFINED

#define XED_IFORM_PI2FD_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PI2FW_MMXq_MEMq_DEFINED

#define XED_IFORM_PI2FW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PI2FW_MMXq_MMXq_DEFINED

#define XED_IFORM_PI2FW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb_DEFINED

#define XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb_DEFINED   1

◆ XED_IFORM_PINSRB_XMMdq_MEMb_IMMb_DEFINED

#define XED_IFORM_PINSRB_XMMdq_MEMb_IMMb_DEFINED   1

◆ XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb_DEFINED

#define XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb_DEFINED   1

◆ XED_IFORM_PINSRD_XMMdq_MEMd_IMMb_DEFINED

#define XED_IFORM_PINSRD_XMMdq_MEMd_IMMb_DEFINED   1

◆ XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb_DEFINED

#define XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb_DEFINED   1

◆ XED_IFORM_PINSRQ_XMMdq_MEMq_IMMb_DEFINED

#define XED_IFORM_PINSRQ_XMMdq_MEMq_IMMb_DEFINED   1

◆ XED_IFORM_PINSRW_MMXq_GPR32_IMMb_DEFINED

#define XED_IFORM_PINSRW_MMXq_GPR32_IMMb_DEFINED   1

◆ XED_IFORM_PINSRW_MMXq_MEMw_IMMb_DEFINED

#define XED_IFORM_PINSRW_MMXq_MEMw_IMMb_DEFINED   1

◆ XED_IFORM_PINSRW_XMMdq_GPR32_IMMb_DEFINED

#define XED_IFORM_PINSRW_XMMdq_GPR32_IMMb_DEFINED   1

◆ XED_IFORM_PINSRW_XMMdq_MEMw_IMMb_DEFINED

#define XED_IFORM_PINSRW_XMMdq_MEMw_IMMb_DEFINED   1

◆ XED_IFORM_PMADDUBSW_MMXq_MEMq_DEFINED

#define XED_IFORM_PMADDUBSW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PMADDUBSW_MMXq_MMXq_DEFINED

#define XED_IFORM_PMADDUBSW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PMADDUBSW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PMADDUBSW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PMADDUBSW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PMADDUBSW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PMADDWD_MMXq_MEMq_DEFINED

#define XED_IFORM_PMADDWD_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PMADDWD_MMXq_MMXq_DEFINED

#define XED_IFORM_PMADDWD_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PMADDWD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PMADDWD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PMADDWD_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PMADDWD_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PMAXSB_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PMAXSB_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PMAXSB_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PMAXSB_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PMAXSD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PMAXSD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PMAXSD_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PMAXSD_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PMAXSW_MMXq_MEMq_DEFINED

#define XED_IFORM_PMAXSW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PMAXSW_MMXq_MMXq_DEFINED

#define XED_IFORM_PMAXSW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PMAXSW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PMAXSW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PMAXSW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PMAXSW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PMAXUB_MMXq_MEMq_DEFINED

#define XED_IFORM_PMAXUB_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PMAXUB_MMXq_MMXq_DEFINED

#define XED_IFORM_PMAXUB_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PMAXUB_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PMAXUB_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PMAXUB_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PMAXUB_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PMAXUD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PMAXUD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PMAXUD_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PMAXUD_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PMAXUW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PMAXUW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PMAXUW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PMAXUW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PMINSB_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PMINSB_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PMINSB_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PMINSB_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PMINSD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PMINSD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PMINSD_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PMINSD_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PMINSW_MMXq_MEMq_DEFINED

#define XED_IFORM_PMINSW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PMINSW_MMXq_MMXq_DEFINED

#define XED_IFORM_PMINSW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PMINSW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PMINSW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PMINSW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PMINSW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PMINUB_MMXq_MEMq_DEFINED

#define XED_IFORM_PMINUB_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PMINUB_MMXq_MMXq_DEFINED

#define XED_IFORM_PMINUB_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PMINUB_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PMINUB_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PMINUB_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PMINUB_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PMINUD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PMINUD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PMINUD_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PMINUD_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PMINUW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PMINUW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PMINUW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PMINUW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PMOVMSKB_GPR32_MMXq_DEFINED

#define XED_IFORM_PMOVMSKB_GPR32_MMXq_DEFINED   1

◆ XED_IFORM_PMOVMSKB_GPR32_XMMdq_DEFINED

#define XED_IFORM_PMOVMSKB_GPR32_XMMdq_DEFINED   1

◆ XED_IFORM_PMOVSXBD_XMMdq_MEMd_DEFINED

#define XED_IFORM_PMOVSXBD_XMMdq_MEMd_DEFINED   1

◆ XED_IFORM_PMOVSXBD_XMMdq_XMMd_DEFINED

#define XED_IFORM_PMOVSXBD_XMMdq_XMMd_DEFINED   1

◆ XED_IFORM_PMOVSXBQ_XMMdq_MEMw_DEFINED

#define XED_IFORM_PMOVSXBQ_XMMdq_MEMw_DEFINED   1

◆ XED_IFORM_PMOVSXBQ_XMMdq_XMMw_DEFINED

#define XED_IFORM_PMOVSXBQ_XMMdq_XMMw_DEFINED   1

◆ XED_IFORM_PMOVSXBW_XMMdq_MEMq_DEFINED

#define XED_IFORM_PMOVSXBW_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_PMOVSXBW_XMMdq_XMMq_DEFINED

#define XED_IFORM_PMOVSXBW_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_PMOVSXDQ_XMMdq_MEMq_DEFINED

#define XED_IFORM_PMOVSXDQ_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_PMOVSXDQ_XMMdq_XMMq_DEFINED

#define XED_IFORM_PMOVSXDQ_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_PMOVSXWD_XMMdq_MEMq_DEFINED

#define XED_IFORM_PMOVSXWD_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_PMOVSXWD_XMMdq_XMMq_DEFINED

#define XED_IFORM_PMOVSXWD_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_PMOVSXWQ_XMMdq_MEMd_DEFINED

#define XED_IFORM_PMOVSXWQ_XMMdq_MEMd_DEFINED   1

◆ XED_IFORM_PMOVSXWQ_XMMdq_XMMd_DEFINED

#define XED_IFORM_PMOVSXWQ_XMMdq_XMMd_DEFINED   1

◆ XED_IFORM_PMOVZXBD_XMMdq_MEMd_DEFINED

#define XED_IFORM_PMOVZXBD_XMMdq_MEMd_DEFINED   1

◆ XED_IFORM_PMOVZXBD_XMMdq_XMMd_DEFINED

#define XED_IFORM_PMOVZXBD_XMMdq_XMMd_DEFINED   1

◆ XED_IFORM_PMOVZXBQ_XMMdq_MEMw_DEFINED

#define XED_IFORM_PMOVZXBQ_XMMdq_MEMw_DEFINED   1

◆ XED_IFORM_PMOVZXBQ_XMMdq_XMMw_DEFINED

#define XED_IFORM_PMOVZXBQ_XMMdq_XMMw_DEFINED   1

◆ XED_IFORM_PMOVZXBW_XMMdq_MEMq_DEFINED

#define XED_IFORM_PMOVZXBW_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_PMOVZXBW_XMMdq_XMMq_DEFINED

#define XED_IFORM_PMOVZXBW_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_PMOVZXDQ_XMMdq_MEMq_DEFINED

#define XED_IFORM_PMOVZXDQ_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_PMOVZXDQ_XMMdq_XMMq_DEFINED

#define XED_IFORM_PMOVZXDQ_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_PMOVZXWD_XMMdq_MEMq_DEFINED

#define XED_IFORM_PMOVZXWD_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_PMOVZXWD_XMMdq_XMMq_DEFINED

#define XED_IFORM_PMOVZXWD_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_PMOVZXWQ_XMMdq_MEMd_DEFINED

#define XED_IFORM_PMOVZXWQ_XMMdq_MEMd_DEFINED   1

◆ XED_IFORM_PMOVZXWQ_XMMdq_XMMd_DEFINED

#define XED_IFORM_PMOVZXWQ_XMMdq_XMMd_DEFINED   1

◆ XED_IFORM_PMULDQ_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PMULDQ_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PMULDQ_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PMULDQ_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PMULHRSW_MMXq_MEMq_DEFINED

#define XED_IFORM_PMULHRSW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PMULHRSW_MMXq_MMXq_DEFINED

#define XED_IFORM_PMULHRSW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PMULHRSW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PMULHRSW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PMULHRSW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PMULHRSW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PMULHRW_MMXq_MEMq_DEFINED

#define XED_IFORM_PMULHRW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PMULHRW_MMXq_MMXq_DEFINED

#define XED_IFORM_PMULHRW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PMULHUW_MMXq_MEMq_DEFINED

#define XED_IFORM_PMULHUW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PMULHUW_MMXq_MMXq_DEFINED

#define XED_IFORM_PMULHUW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PMULHUW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PMULHUW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PMULHUW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PMULHUW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PMULHW_MMXq_MEMq_DEFINED

#define XED_IFORM_PMULHW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PMULHW_MMXq_MMXq_DEFINED

#define XED_IFORM_PMULHW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PMULHW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PMULHW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PMULHW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PMULHW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PMULLD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PMULLD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PMULLD_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PMULLD_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PMULLW_MMXq_MEMq_DEFINED

#define XED_IFORM_PMULLW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PMULLW_MMXq_MMXq_DEFINED

#define XED_IFORM_PMULLW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PMULLW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PMULLW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PMULLW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PMULLW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PMULUDQ_MMXq_MEMq_DEFINED

#define XED_IFORM_PMULUDQ_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PMULUDQ_MMXq_MMXq_DEFINED

#define XED_IFORM_PMULUDQ_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PMULUDQ_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PMULUDQ_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PMULUDQ_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PMULUDQ_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_POP2_GPR64u64_GPR64u64_APX_DEFINED

#define XED_IFORM_POP2_GPR64u64_GPR64u64_APX_DEFINED   1

◆ XED_IFORM_POP2P_GPR64u64_GPR64u64_APX_DEFINED

#define XED_IFORM_POP2P_GPR64u64_GPR64u64_APX_DEFINED   1

◆ XED_IFORM_POP_DS_DEFINED

#define XED_IFORM_POP_DS_DEFINED   1

◆ XED_IFORM_POP_ES_DEFINED

#define XED_IFORM_POP_ES_DEFINED   1

◆ XED_IFORM_POP_FS_DEFINED

#define XED_IFORM_POP_FS_DEFINED   1

◆ XED_IFORM_POP_GPRv_58_DEFINED

#define XED_IFORM_POP_GPRv_58_DEFINED   1

◆ XED_IFORM_POP_GPRv_8F_DEFINED

#define XED_IFORM_POP_GPRv_8F_DEFINED   1

◆ XED_IFORM_POP_GS_DEFINED

#define XED_IFORM_POP_GS_DEFINED   1

◆ XED_IFORM_POP_MEMv_DEFINED

#define XED_IFORM_POP_MEMv_DEFINED   1

◆ XED_IFORM_POP_SS_DEFINED

#define XED_IFORM_POP_SS_DEFINED   1

◆ XED_IFORM_POPA_DEFINED

#define XED_IFORM_POPA_DEFINED   1

◆ XED_IFORM_POPAD_DEFINED

#define XED_IFORM_POPAD_DEFINED   1

◆ XED_IFORM_POPCNT_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_POPCNT_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_POPCNT_GPRv_GPRv_DEFINED

#define XED_IFORM_POPCNT_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_POPCNT_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_POPCNT_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_POPCNT_GPRv_MEMv_DEFINED

#define XED_IFORM_POPCNT_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_POPF_DEFINED

#define XED_IFORM_POPF_DEFINED   1

◆ XED_IFORM_POPFD_DEFINED

#define XED_IFORM_POPFD_DEFINED   1

◆ XED_IFORM_POPFQ_DEFINED

#define XED_IFORM_POPFQ_DEFINED   1

◆ XED_IFORM_POPP_GPR64_DEFINED

#define XED_IFORM_POPP_GPR64_DEFINED   1

◆ XED_IFORM_POR_MMXq_MEMq_DEFINED

#define XED_IFORM_POR_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_POR_MMXq_MMXq_DEFINED

#define XED_IFORM_POR_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_POR_XMMdq_MEMdq_DEFINED

#define XED_IFORM_POR_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_POR_XMMdq_XMMdq_DEFINED

#define XED_IFORM_POR_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PREFETCH_EXCLUSIVE_MEMmprefetch_DEFINED

#define XED_IFORM_PREFETCH_EXCLUSIVE_MEMmprefetch_DEFINED   1

◆ XED_IFORM_PREFETCH_RESERVED_0F0Dr4_DEFINED

#define XED_IFORM_PREFETCH_RESERVED_0F0Dr4_DEFINED   1

◆ XED_IFORM_PREFETCH_RESERVED_0F0Dr5_DEFINED

#define XED_IFORM_PREFETCH_RESERVED_0F0Dr5_DEFINED   1

◆ XED_IFORM_PREFETCH_RESERVED_0F0Dr6_DEFINED

#define XED_IFORM_PREFETCH_RESERVED_0F0Dr6_DEFINED   1

◆ XED_IFORM_PREFETCH_RESERVED_0F0Dr7_DEFINED

#define XED_IFORM_PREFETCH_RESERVED_0F0Dr7_DEFINED   1

◆ XED_IFORM_PREFETCHIT0_MEMu8_DEFINED

#define XED_IFORM_PREFETCHIT0_MEMu8_DEFINED   1

◆ XED_IFORM_PREFETCHIT1_MEMu8_DEFINED

#define XED_IFORM_PREFETCHIT1_MEMu8_DEFINED   1

◆ XED_IFORM_PREFETCHNTA_MEMmprefetch_DEFINED

#define XED_IFORM_PREFETCHNTA_MEMmprefetch_DEFINED   1

◆ XED_IFORM_PREFETCHRST2_MEMu8_DEFINED

#define XED_IFORM_PREFETCHRST2_MEMu8_DEFINED   1

◆ XED_IFORM_PREFETCHT0_MEMmprefetch_DEFINED

#define XED_IFORM_PREFETCHT0_MEMmprefetch_DEFINED   1

◆ XED_IFORM_PREFETCHT1_MEMmprefetch_DEFINED

#define XED_IFORM_PREFETCHT1_MEMmprefetch_DEFINED   1

◆ XED_IFORM_PREFETCHT2_MEMmprefetch_DEFINED

#define XED_IFORM_PREFETCHT2_MEMmprefetch_DEFINED   1

◆ XED_IFORM_PREFETCHW_0F0Dr1_DEFINED

#define XED_IFORM_PREFETCHW_0F0Dr1_DEFINED   1

◆ XED_IFORM_PREFETCHW_0F0Dr3_DEFINED

#define XED_IFORM_PREFETCHW_0F0Dr3_DEFINED   1

◆ XED_IFORM_PREFETCHWT1_MEMu8_DEFINED

#define XED_IFORM_PREFETCHWT1_MEMu8_DEFINED   1

◆ XED_IFORM_PSADBW_MMXq_MEMq_DEFINED

#define XED_IFORM_PSADBW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PSADBW_MMXq_MMXq_DEFINED

#define XED_IFORM_PSADBW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PSADBW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PSADBW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PSADBW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PSADBW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PSHUFB_MMXq_MEMq_DEFINED

#define XED_IFORM_PSHUFB_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PSHUFB_MMXq_MMXq_DEFINED

#define XED_IFORM_PSHUFB_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PSHUFB_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PSHUFB_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PSHUFB_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PSHUFB_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PSHUFD_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_PSHUFD_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PSHUFHW_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_PSHUFHW_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PSHUFLW_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_PSHUFLW_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PSHUFW_MMXq_MEMq_IMMb_DEFINED

#define XED_IFORM_PSHUFW_MMXq_MEMq_IMMb_DEFINED   1

◆ XED_IFORM_PSHUFW_MMXq_MMXq_IMMb_DEFINED

#define XED_IFORM_PSHUFW_MMXq_MMXq_IMMb_DEFINED   1

◆ XED_IFORM_PSIGNB_MMXq_MEMq_DEFINED

#define XED_IFORM_PSIGNB_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PSIGNB_MMXq_MMXq_DEFINED

#define XED_IFORM_PSIGNB_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PSIGNB_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PSIGNB_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PSIGNB_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PSIGNB_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PSIGND_MMXq_MEMq_DEFINED

#define XED_IFORM_PSIGND_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PSIGND_MMXq_MMXq_DEFINED

#define XED_IFORM_PSIGND_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PSIGND_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PSIGND_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PSIGND_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PSIGND_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PSIGNW_MMXq_MEMq_DEFINED

#define XED_IFORM_PSIGNW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PSIGNW_MMXq_MMXq_DEFINED

#define XED_IFORM_PSIGNW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PSIGNW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PSIGNW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PSIGNW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PSIGNW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PSLLD_MMXq_IMMb_DEFINED

#define XED_IFORM_PSLLD_MMXq_IMMb_DEFINED   1

◆ XED_IFORM_PSLLD_MMXq_MEMq_DEFINED

#define XED_IFORM_PSLLD_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PSLLD_MMXq_MMXq_DEFINED

#define XED_IFORM_PSLLD_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PSLLD_XMMdq_IMMb_DEFINED

#define XED_IFORM_PSLLD_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PSLLD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PSLLD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PSLLD_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PSLLD_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PSLLDQ_XMMdq_IMMb_DEFINED

#define XED_IFORM_PSLLDQ_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PSLLQ_MMXq_IMMb_DEFINED

#define XED_IFORM_PSLLQ_MMXq_IMMb_DEFINED   1

◆ XED_IFORM_PSLLQ_MMXq_MEMq_DEFINED

#define XED_IFORM_PSLLQ_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PSLLQ_MMXq_MMXq_DEFINED

#define XED_IFORM_PSLLQ_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PSLLQ_XMMdq_IMMb_DEFINED

#define XED_IFORM_PSLLQ_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PSLLQ_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PSLLQ_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PSLLQ_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PSLLQ_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PSLLW_MMXq_IMMb_DEFINED

#define XED_IFORM_PSLLW_MMXq_IMMb_DEFINED   1

◆ XED_IFORM_PSLLW_MMXq_MEMq_DEFINED

#define XED_IFORM_PSLLW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PSLLW_MMXq_MMXq_DEFINED

#define XED_IFORM_PSLLW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PSLLW_XMMdq_IMMb_DEFINED

#define XED_IFORM_PSLLW_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PSLLW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PSLLW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PSLLW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PSLLW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PSMASH_RAX_DEFINED

#define XED_IFORM_PSMASH_RAX_DEFINED   1

◆ XED_IFORM_PSRAD_MMXq_IMMb_DEFINED

#define XED_IFORM_PSRAD_MMXq_IMMb_DEFINED   1

◆ XED_IFORM_PSRAD_MMXq_MEMq_DEFINED

#define XED_IFORM_PSRAD_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PSRAD_MMXq_MMXq_DEFINED

#define XED_IFORM_PSRAD_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PSRAD_XMMdq_IMMb_DEFINED

#define XED_IFORM_PSRAD_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PSRAD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PSRAD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PSRAD_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PSRAD_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PSRAW_MMXq_IMMb_DEFINED

#define XED_IFORM_PSRAW_MMXq_IMMb_DEFINED   1

◆ XED_IFORM_PSRAW_MMXq_MEMq_DEFINED

#define XED_IFORM_PSRAW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PSRAW_MMXq_MMXq_DEFINED

#define XED_IFORM_PSRAW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PSRAW_XMMdq_IMMb_DEFINED

#define XED_IFORM_PSRAW_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PSRAW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PSRAW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PSRAW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PSRAW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PSRLD_MMXq_IMMb_DEFINED

#define XED_IFORM_PSRLD_MMXq_IMMb_DEFINED   1

◆ XED_IFORM_PSRLD_MMXq_MEMq_DEFINED

#define XED_IFORM_PSRLD_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PSRLD_MMXq_MMXq_DEFINED

#define XED_IFORM_PSRLD_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PSRLD_XMMdq_IMMb_DEFINED

#define XED_IFORM_PSRLD_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PSRLD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PSRLD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PSRLD_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PSRLD_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PSRLDQ_XMMdq_IMMb_DEFINED

#define XED_IFORM_PSRLDQ_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PSRLQ_MMXq_IMMb_DEFINED

#define XED_IFORM_PSRLQ_MMXq_IMMb_DEFINED   1

◆ XED_IFORM_PSRLQ_MMXq_MEMq_DEFINED

#define XED_IFORM_PSRLQ_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PSRLQ_MMXq_MMXq_DEFINED

#define XED_IFORM_PSRLQ_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PSRLQ_XMMdq_IMMb_DEFINED

#define XED_IFORM_PSRLQ_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PSRLQ_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PSRLQ_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PSRLQ_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PSRLQ_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PSRLW_MMXq_IMMb_DEFINED

#define XED_IFORM_PSRLW_MMXq_IMMb_DEFINED   1

◆ XED_IFORM_PSRLW_MMXq_MEMq_DEFINED

#define XED_IFORM_PSRLW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PSRLW_MMXq_MMXq_DEFINED

#define XED_IFORM_PSRLW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PSRLW_XMMdq_IMMb_DEFINED

#define XED_IFORM_PSRLW_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_PSRLW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PSRLW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PSRLW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PSRLW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PSUBB_MMXq_MEMq_DEFINED

#define XED_IFORM_PSUBB_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PSUBB_MMXq_MMXq_DEFINED

#define XED_IFORM_PSUBB_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PSUBB_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PSUBB_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PSUBB_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PSUBB_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PSUBD_MMXq_MEMq_DEFINED

#define XED_IFORM_PSUBD_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PSUBD_MMXq_MMXq_DEFINED

#define XED_IFORM_PSUBD_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PSUBD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PSUBD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PSUBD_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PSUBD_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PSUBQ_MMXq_MEMq_DEFINED

#define XED_IFORM_PSUBQ_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PSUBQ_MMXq_MMXq_DEFINED

#define XED_IFORM_PSUBQ_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PSUBQ_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PSUBQ_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PSUBQ_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PSUBQ_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PSUBSB_MMXq_MEMq_DEFINED

#define XED_IFORM_PSUBSB_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PSUBSB_MMXq_MMXq_DEFINED

#define XED_IFORM_PSUBSB_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PSUBSB_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PSUBSB_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PSUBSB_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PSUBSB_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PSUBSW_MMXq_MEMq_DEFINED

#define XED_IFORM_PSUBSW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PSUBSW_MMXq_MMXq_DEFINED

#define XED_IFORM_PSUBSW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PSUBSW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PSUBSW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PSUBSW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PSUBSW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PSUBUSB_MMXq_MEMq_DEFINED

#define XED_IFORM_PSUBUSB_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PSUBUSB_MMXq_MMXq_DEFINED

#define XED_IFORM_PSUBUSB_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PSUBUSB_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PSUBUSB_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PSUBUSB_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PSUBUSB_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PSUBUSW_MMXq_MEMq_DEFINED

#define XED_IFORM_PSUBUSW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PSUBUSW_MMXq_MMXq_DEFINED

#define XED_IFORM_PSUBUSW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PSUBUSW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PSUBUSW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PSUBUSW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PSUBUSW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PSUBW_MMXq_MEMq_DEFINED

#define XED_IFORM_PSUBW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PSUBW_MMXq_MMXq_DEFINED

#define XED_IFORM_PSUBW_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PSUBW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PSUBW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PSUBW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PSUBW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PSWAPD_MMXq_MEMq_DEFINED

#define XED_IFORM_PSWAPD_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PSWAPD_MMXq_MMXq_DEFINED

#define XED_IFORM_PSWAPD_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PTEST_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PTEST_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PTEST_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PTEST_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_PTWRITE_GPRy_DEFINED

#define XED_IFORM_PTWRITE_GPRy_DEFINED   1

◆ XED_IFORM_PTWRITE_MEMy_DEFINED

#define XED_IFORM_PTWRITE_MEMy_DEFINED   1

◆ XED_IFORM_PUNPCKHBW_MMXq_MEMq_DEFINED

#define XED_IFORM_PUNPCKHBW_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PUNPCKHBW_MMXq_MMXd_DEFINED

#define XED_IFORM_PUNPCKHBW_MMXq_MMXd_DEFINED   1

◆ XED_IFORM_PUNPCKHBW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PUNPCKHBW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PUNPCKHBW_XMMdq_XMMq_DEFINED

#define XED_IFORM_PUNPCKHBW_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_PUNPCKHDQ_MMXq_MEMq_DEFINED

#define XED_IFORM_PUNPCKHDQ_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PUNPCKHDQ_MMXq_MMXd_DEFINED

#define XED_IFORM_PUNPCKHDQ_MMXq_MMXd_DEFINED   1

◆ XED_IFORM_PUNPCKHDQ_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PUNPCKHDQ_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PUNPCKHDQ_XMMdq_XMMq_DEFINED

#define XED_IFORM_PUNPCKHDQ_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_PUNPCKHQDQ_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PUNPCKHQDQ_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PUNPCKHQDQ_XMMdq_XMMq_DEFINED

#define XED_IFORM_PUNPCKHQDQ_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_PUNPCKHWD_MMXq_MEMq_DEFINED

#define XED_IFORM_PUNPCKHWD_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PUNPCKHWD_MMXq_MMXd_DEFINED

#define XED_IFORM_PUNPCKHWD_MMXq_MMXd_DEFINED   1

◆ XED_IFORM_PUNPCKHWD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PUNPCKHWD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PUNPCKHWD_XMMdq_XMMq_DEFINED

#define XED_IFORM_PUNPCKHWD_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_PUNPCKLBW_MMXq_MEMd_DEFINED

#define XED_IFORM_PUNPCKLBW_MMXq_MEMd_DEFINED   1

◆ XED_IFORM_PUNPCKLBW_MMXq_MMXd_DEFINED

#define XED_IFORM_PUNPCKLBW_MMXq_MMXd_DEFINED   1

◆ XED_IFORM_PUNPCKLBW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PUNPCKLBW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PUNPCKLBW_XMMdq_XMMq_DEFINED

#define XED_IFORM_PUNPCKLBW_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_PUNPCKLDQ_MMXq_MEMd_DEFINED

#define XED_IFORM_PUNPCKLDQ_MMXq_MEMd_DEFINED   1

◆ XED_IFORM_PUNPCKLDQ_MMXq_MMXd_DEFINED

#define XED_IFORM_PUNPCKLDQ_MMXq_MMXd_DEFINED   1

◆ XED_IFORM_PUNPCKLDQ_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PUNPCKLDQ_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PUNPCKLDQ_XMMdq_XMMq_DEFINED

#define XED_IFORM_PUNPCKLDQ_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_PUNPCKLQDQ_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PUNPCKLQDQ_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PUNPCKLQDQ_XMMdq_XMMq_DEFINED

#define XED_IFORM_PUNPCKLQDQ_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_PUNPCKLWD_MMXq_MEMd_DEFINED

#define XED_IFORM_PUNPCKLWD_MMXq_MEMd_DEFINED   1

◆ XED_IFORM_PUNPCKLWD_MMXq_MMXd_DEFINED

#define XED_IFORM_PUNPCKLWD_MMXq_MMXd_DEFINED   1

◆ XED_IFORM_PUNPCKLWD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PUNPCKLWD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PUNPCKLWD_XMMdq_XMMq_DEFINED

#define XED_IFORM_PUNPCKLWD_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_PUSH2_GPR64u64_GPR64u64_APX_DEFINED

#define XED_IFORM_PUSH2_GPR64u64_GPR64u64_APX_DEFINED   1

◆ XED_IFORM_PUSH2P_GPR64u64_GPR64u64_APX_DEFINED

#define XED_IFORM_PUSH2P_GPR64u64_GPR64u64_APX_DEFINED   1

◆ XED_IFORM_PUSH_CS_DEFINED

#define XED_IFORM_PUSH_CS_DEFINED   1

◆ XED_IFORM_PUSH_DS_DEFINED

#define XED_IFORM_PUSH_DS_DEFINED   1

◆ XED_IFORM_PUSH_ES_DEFINED

#define XED_IFORM_PUSH_ES_DEFINED   1

◆ XED_IFORM_PUSH_FS_DEFINED

#define XED_IFORM_PUSH_FS_DEFINED   1

◆ XED_IFORM_PUSH_GPRv_50_DEFINED

#define XED_IFORM_PUSH_GPRv_50_DEFINED   1

◆ XED_IFORM_PUSH_GPRv_FFr6_DEFINED

#define XED_IFORM_PUSH_GPRv_FFr6_DEFINED   1

◆ XED_IFORM_PUSH_GS_DEFINED

#define XED_IFORM_PUSH_GS_DEFINED   1

◆ XED_IFORM_PUSH_IMMb_DEFINED

#define XED_IFORM_PUSH_IMMb_DEFINED   1

◆ XED_IFORM_PUSH_IMMz_DEFINED

#define XED_IFORM_PUSH_IMMz_DEFINED   1

◆ XED_IFORM_PUSH_MEMv_DEFINED

#define XED_IFORM_PUSH_MEMv_DEFINED   1

◆ XED_IFORM_PUSH_SS_DEFINED

#define XED_IFORM_PUSH_SS_DEFINED   1

◆ XED_IFORM_PUSHA_DEFINED

#define XED_IFORM_PUSHA_DEFINED   1

◆ XED_IFORM_PUSHAD_DEFINED

#define XED_IFORM_PUSHAD_DEFINED   1

◆ XED_IFORM_PUSHF_DEFINED

#define XED_IFORM_PUSHF_DEFINED   1

◆ XED_IFORM_PUSHFD_DEFINED

#define XED_IFORM_PUSHFD_DEFINED   1

◆ XED_IFORM_PUSHFQ_DEFINED

#define XED_IFORM_PUSHFQ_DEFINED   1

◆ XED_IFORM_PUSHP_GPR64_DEFINED

#define XED_IFORM_PUSHP_GPR64_DEFINED   1

◆ XED_IFORM_PVALIDATE_RAX_ECX_EDX_DEFINED

#define XED_IFORM_PVALIDATE_RAX_ECX_EDX_DEFINED   1

◆ XED_IFORM_PXOR_MMXq_MEMq_DEFINED

#define XED_IFORM_PXOR_MMXq_MEMq_DEFINED   1

◆ XED_IFORM_PXOR_MMXq_MMXq_DEFINED

#define XED_IFORM_PXOR_MMXq_MMXq_DEFINED   1

◆ XED_IFORM_PXOR_XMMdq_MEMdq_DEFINED

#define XED_IFORM_PXOR_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_PXOR_XMMdq_XMMdq_DEFINED

#define XED_IFORM_PXOR_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_RCL_GPR8_CL_DEFINED

#define XED_IFORM_RCL_GPR8_CL_DEFINED   1

◆ XED_IFORM_RCL_GPR8_IMMb_DEFINED

#define XED_IFORM_RCL_GPR8_IMMb_DEFINED   1

◆ XED_IFORM_RCL_GPR8_ONE_DEFINED

#define XED_IFORM_RCL_GPR8_ONE_DEFINED   1

◆ XED_IFORM_RCL_GPR8i8_CL_APX_DEFINED

#define XED_IFORM_RCL_GPR8i8_CL_APX_DEFINED   1

◆ XED_IFORM_RCL_GPR8i8_GPR8i8_CL_APX_DEFINED

#define XED_IFORM_RCL_GPR8i8_GPR8i8_CL_APX_DEFINED   1

◆ XED_IFORM_RCL_GPR8i8_GPR8i8_IMM8_APX_DEFINED

#define XED_IFORM_RCL_GPR8i8_GPR8i8_IMM8_APX_DEFINED   1

◆ XED_IFORM_RCL_GPR8i8_GPR8i8_ONE_APX_DEFINED

#define XED_IFORM_RCL_GPR8i8_GPR8i8_ONE_APX_DEFINED   1

◆ XED_IFORM_RCL_GPR8i8_IMM8_APX_DEFINED

#define XED_IFORM_RCL_GPR8i8_IMM8_APX_DEFINED   1

◆ XED_IFORM_RCL_GPR8i8_MEMi8_CL_APX_DEFINED

#define XED_IFORM_RCL_GPR8i8_MEMi8_CL_APX_DEFINED   1

◆ XED_IFORM_RCL_GPR8i8_MEMi8_IMM8_APX_DEFINED

#define XED_IFORM_RCL_GPR8i8_MEMi8_IMM8_APX_DEFINED   1

◆ XED_IFORM_RCL_GPR8i8_MEMi8_ONE_APX_DEFINED

#define XED_IFORM_RCL_GPR8i8_MEMi8_ONE_APX_DEFINED   1

◆ XED_IFORM_RCL_GPR8i8_ONE_APX_DEFINED

#define XED_IFORM_RCL_GPR8i8_ONE_APX_DEFINED   1

◆ XED_IFORM_RCL_GPRv_CL_APX_DEFINED

#define XED_IFORM_RCL_GPRv_CL_APX_DEFINED   1

◆ XED_IFORM_RCL_GPRv_CL_DEFINED

#define XED_IFORM_RCL_GPRv_CL_DEFINED   1

◆ XED_IFORM_RCL_GPRv_GPRv_CL_APX_DEFINED

#define XED_IFORM_RCL_GPRv_GPRv_CL_APX_DEFINED   1

◆ XED_IFORM_RCL_GPRv_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_RCL_GPRv_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_RCL_GPRv_GPRv_ONE_APX_DEFINED

#define XED_IFORM_RCL_GPRv_GPRv_ONE_APX_DEFINED   1

◆ XED_IFORM_RCL_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_RCL_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_RCL_GPRv_IMMb_DEFINED

#define XED_IFORM_RCL_GPRv_IMMb_DEFINED   1

◆ XED_IFORM_RCL_GPRv_MEMv_CL_APX_DEFINED

#define XED_IFORM_RCL_GPRv_MEMv_CL_APX_DEFINED   1

◆ XED_IFORM_RCL_GPRv_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_RCL_GPRv_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_RCL_GPRv_MEMv_ONE_APX_DEFINED

#define XED_IFORM_RCL_GPRv_MEMv_ONE_APX_DEFINED   1

◆ XED_IFORM_RCL_GPRv_ONE_APX_DEFINED

#define XED_IFORM_RCL_GPRv_ONE_APX_DEFINED   1

◆ XED_IFORM_RCL_GPRv_ONE_DEFINED

#define XED_IFORM_RCL_GPRv_ONE_DEFINED   1

◆ XED_IFORM_RCL_MEMb_CL_DEFINED

#define XED_IFORM_RCL_MEMb_CL_DEFINED   1

◆ XED_IFORM_RCL_MEMb_IMMb_DEFINED

#define XED_IFORM_RCL_MEMb_IMMb_DEFINED   1

◆ XED_IFORM_RCL_MEMb_ONE_DEFINED

#define XED_IFORM_RCL_MEMb_ONE_DEFINED   1

◆ XED_IFORM_RCL_MEMi8_CL_APX_DEFINED

#define XED_IFORM_RCL_MEMi8_CL_APX_DEFINED   1

◆ XED_IFORM_RCL_MEMi8_IMM8_APX_DEFINED

#define XED_IFORM_RCL_MEMi8_IMM8_APX_DEFINED   1

◆ XED_IFORM_RCL_MEMi8_ONE_APX_DEFINED

#define XED_IFORM_RCL_MEMi8_ONE_APX_DEFINED   1

◆ XED_IFORM_RCL_MEMv_CL_APX_DEFINED

#define XED_IFORM_RCL_MEMv_CL_APX_DEFINED   1

◆ XED_IFORM_RCL_MEMv_CL_DEFINED

#define XED_IFORM_RCL_MEMv_CL_DEFINED   1

◆ XED_IFORM_RCL_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_RCL_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_RCL_MEMv_IMMb_DEFINED

#define XED_IFORM_RCL_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_RCL_MEMv_ONE_APX_DEFINED

#define XED_IFORM_RCL_MEMv_ONE_APX_DEFINED   1

◆ XED_IFORM_RCL_MEMv_ONE_DEFINED

#define XED_IFORM_RCL_MEMv_ONE_DEFINED   1

◆ XED_IFORM_RCPPS_XMMps_MEMps_DEFINED

#define XED_IFORM_RCPPS_XMMps_MEMps_DEFINED   1

◆ XED_IFORM_RCPPS_XMMps_XMMps_DEFINED

#define XED_IFORM_RCPPS_XMMps_XMMps_DEFINED   1

◆ XED_IFORM_RCPSS_XMMss_MEMss_DEFINED

#define XED_IFORM_RCPSS_XMMss_MEMss_DEFINED   1

◆ XED_IFORM_RCPSS_XMMss_XMMss_DEFINED

#define XED_IFORM_RCPSS_XMMss_XMMss_DEFINED   1

◆ XED_IFORM_RCR_GPR8_CL_DEFINED

#define XED_IFORM_RCR_GPR8_CL_DEFINED   1

◆ XED_IFORM_RCR_GPR8_IMMb_DEFINED

#define XED_IFORM_RCR_GPR8_IMMb_DEFINED   1

◆ XED_IFORM_RCR_GPR8_ONE_DEFINED

#define XED_IFORM_RCR_GPR8_ONE_DEFINED   1

◆ XED_IFORM_RCR_GPR8i8_CL_APX_DEFINED

#define XED_IFORM_RCR_GPR8i8_CL_APX_DEFINED   1

◆ XED_IFORM_RCR_GPR8i8_GPR8i8_CL_APX_DEFINED

#define XED_IFORM_RCR_GPR8i8_GPR8i8_CL_APX_DEFINED   1

◆ XED_IFORM_RCR_GPR8i8_GPR8i8_IMM8_APX_DEFINED

#define XED_IFORM_RCR_GPR8i8_GPR8i8_IMM8_APX_DEFINED   1

◆ XED_IFORM_RCR_GPR8i8_GPR8i8_ONE_APX_DEFINED

#define XED_IFORM_RCR_GPR8i8_GPR8i8_ONE_APX_DEFINED   1

◆ XED_IFORM_RCR_GPR8i8_IMM8_APX_DEFINED

#define XED_IFORM_RCR_GPR8i8_IMM8_APX_DEFINED   1

◆ XED_IFORM_RCR_GPR8i8_MEMi8_CL_APX_DEFINED

#define XED_IFORM_RCR_GPR8i8_MEMi8_CL_APX_DEFINED   1

◆ XED_IFORM_RCR_GPR8i8_MEMi8_IMM8_APX_DEFINED

#define XED_IFORM_RCR_GPR8i8_MEMi8_IMM8_APX_DEFINED   1

◆ XED_IFORM_RCR_GPR8i8_MEMi8_ONE_APX_DEFINED

#define XED_IFORM_RCR_GPR8i8_MEMi8_ONE_APX_DEFINED   1

◆ XED_IFORM_RCR_GPR8i8_ONE_APX_DEFINED

#define XED_IFORM_RCR_GPR8i8_ONE_APX_DEFINED   1

◆ XED_IFORM_RCR_GPRv_CL_APX_DEFINED

#define XED_IFORM_RCR_GPRv_CL_APX_DEFINED   1

◆ XED_IFORM_RCR_GPRv_CL_DEFINED

#define XED_IFORM_RCR_GPRv_CL_DEFINED   1

◆ XED_IFORM_RCR_GPRv_GPRv_CL_APX_DEFINED

#define XED_IFORM_RCR_GPRv_GPRv_CL_APX_DEFINED   1

◆ XED_IFORM_RCR_GPRv_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_RCR_GPRv_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_RCR_GPRv_GPRv_ONE_APX_DEFINED

#define XED_IFORM_RCR_GPRv_GPRv_ONE_APX_DEFINED   1

◆ XED_IFORM_RCR_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_RCR_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_RCR_GPRv_IMMb_DEFINED

#define XED_IFORM_RCR_GPRv_IMMb_DEFINED   1

◆ XED_IFORM_RCR_GPRv_MEMv_CL_APX_DEFINED

#define XED_IFORM_RCR_GPRv_MEMv_CL_APX_DEFINED   1

◆ XED_IFORM_RCR_GPRv_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_RCR_GPRv_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_RCR_GPRv_MEMv_ONE_APX_DEFINED

#define XED_IFORM_RCR_GPRv_MEMv_ONE_APX_DEFINED   1

◆ XED_IFORM_RCR_GPRv_ONE_APX_DEFINED

#define XED_IFORM_RCR_GPRv_ONE_APX_DEFINED   1

◆ XED_IFORM_RCR_GPRv_ONE_DEFINED

#define XED_IFORM_RCR_GPRv_ONE_DEFINED   1

◆ XED_IFORM_RCR_MEMb_CL_DEFINED

#define XED_IFORM_RCR_MEMb_CL_DEFINED   1

◆ XED_IFORM_RCR_MEMb_IMMb_DEFINED

#define XED_IFORM_RCR_MEMb_IMMb_DEFINED   1

◆ XED_IFORM_RCR_MEMb_ONE_DEFINED

#define XED_IFORM_RCR_MEMb_ONE_DEFINED   1

◆ XED_IFORM_RCR_MEMi8_CL_APX_DEFINED

#define XED_IFORM_RCR_MEMi8_CL_APX_DEFINED   1

◆ XED_IFORM_RCR_MEMi8_IMM8_APX_DEFINED

#define XED_IFORM_RCR_MEMi8_IMM8_APX_DEFINED   1

◆ XED_IFORM_RCR_MEMi8_ONE_APX_DEFINED

#define XED_IFORM_RCR_MEMi8_ONE_APX_DEFINED   1

◆ XED_IFORM_RCR_MEMv_CL_APX_DEFINED

#define XED_IFORM_RCR_MEMv_CL_APX_DEFINED   1

◆ XED_IFORM_RCR_MEMv_CL_DEFINED

#define XED_IFORM_RCR_MEMv_CL_DEFINED   1

◆ XED_IFORM_RCR_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_RCR_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_RCR_MEMv_IMMb_DEFINED

#define XED_IFORM_RCR_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_RCR_MEMv_ONE_APX_DEFINED

#define XED_IFORM_RCR_MEMv_ONE_APX_DEFINED   1

◆ XED_IFORM_RCR_MEMv_ONE_DEFINED

#define XED_IFORM_RCR_MEMv_ONE_DEFINED   1

◆ XED_IFORM_RDFSBASE_GPRy_DEFINED

#define XED_IFORM_RDFSBASE_GPRy_DEFINED   1

◆ XED_IFORM_RDGSBASE_GPRy_DEFINED

#define XED_IFORM_RDGSBASE_GPRy_DEFINED   1

◆ XED_IFORM_RDMSR_DEFINED

#define XED_IFORM_RDMSR_DEFINED   1

◆ XED_IFORM_RDMSR_GPR64u64_IMM32_APX_DEFINED

#define XED_IFORM_RDMSR_GPR64u64_IMM32_APX_DEFINED   1

◆ XED_IFORM_RDMSR_GPR64u64_IMM32_DEFINED

#define XED_IFORM_RDMSR_GPR64u64_IMM32_DEFINED   1

◆ XED_IFORM_RDMSRLIST_DEFINED

#define XED_IFORM_RDMSRLIST_DEFINED   1

◆ XED_IFORM_RDPID_GPR32u32_DEFINED

#define XED_IFORM_RDPID_GPR32u32_DEFINED   1

◆ XED_IFORM_RDPID_GPR64u64_DEFINED

#define XED_IFORM_RDPID_GPR64u64_DEFINED   1

◆ XED_IFORM_RDPKRU_DEFINED

#define XED_IFORM_RDPKRU_DEFINED   1

◆ XED_IFORM_RDPMC_DEFINED

#define XED_IFORM_RDPMC_DEFINED   1

◆ XED_IFORM_RDPRU_DEFINED

#define XED_IFORM_RDPRU_DEFINED   1

◆ XED_IFORM_RDRAND_GPRv_DEFINED

#define XED_IFORM_RDRAND_GPRv_DEFINED   1

◆ XED_IFORM_RDSEED_GPRv_DEFINED

#define XED_IFORM_RDSEED_GPRv_DEFINED   1

◆ XED_IFORM_RDSSPD_GPR32u32_DEFINED

#define XED_IFORM_RDSSPD_GPR32u32_DEFINED   1

◆ XED_IFORM_RDSSPQ_GPR64u64_DEFINED

#define XED_IFORM_RDSSPQ_GPR64u64_DEFINED   1

◆ XED_IFORM_RDTSC_DEFINED

#define XED_IFORM_RDTSC_DEFINED   1

◆ XED_IFORM_RDTSCP_DEFINED

#define XED_IFORM_RDTSCP_DEFINED   1

◆ XED_IFORM_REP_INSB_DEFINED

#define XED_IFORM_REP_INSB_DEFINED   1

◆ XED_IFORM_REP_INSD_DEFINED

#define XED_IFORM_REP_INSD_DEFINED   1

◆ XED_IFORM_REP_INSW_DEFINED

#define XED_IFORM_REP_INSW_DEFINED   1

◆ XED_IFORM_REP_LODSB_DEFINED

#define XED_IFORM_REP_LODSB_DEFINED   1

◆ XED_IFORM_REP_LODSD_DEFINED

#define XED_IFORM_REP_LODSD_DEFINED   1

◆ XED_IFORM_REP_LODSQ_DEFINED

#define XED_IFORM_REP_LODSQ_DEFINED   1

◆ XED_IFORM_REP_LODSW_DEFINED

#define XED_IFORM_REP_LODSW_DEFINED   1

◆ XED_IFORM_REP_MONTMUL_DEFINED

#define XED_IFORM_REP_MONTMUL_DEFINED   1

◆ XED_IFORM_REP_MOVSB_DEFINED

#define XED_IFORM_REP_MOVSB_DEFINED   1

◆ XED_IFORM_REP_MOVSD_DEFINED

#define XED_IFORM_REP_MOVSD_DEFINED   1

◆ XED_IFORM_REP_MOVSQ_DEFINED

#define XED_IFORM_REP_MOVSQ_DEFINED   1

◆ XED_IFORM_REP_MOVSW_DEFINED

#define XED_IFORM_REP_MOVSW_DEFINED   1

◆ XED_IFORM_REP_OUTSB_DEFINED

#define XED_IFORM_REP_OUTSB_DEFINED   1

◆ XED_IFORM_REP_OUTSD_DEFINED

#define XED_IFORM_REP_OUTSD_DEFINED   1

◆ XED_IFORM_REP_OUTSW_DEFINED

#define XED_IFORM_REP_OUTSW_DEFINED   1

◆ XED_IFORM_REP_STOSB_DEFINED

#define XED_IFORM_REP_STOSB_DEFINED   1

◆ XED_IFORM_REP_STOSD_DEFINED

#define XED_IFORM_REP_STOSD_DEFINED   1

◆ XED_IFORM_REP_STOSQ_DEFINED

#define XED_IFORM_REP_STOSQ_DEFINED   1

◆ XED_IFORM_REP_STOSW_DEFINED

#define XED_IFORM_REP_STOSW_DEFINED   1

◆ XED_IFORM_REP_XCRYPTCBC_DEFINED

#define XED_IFORM_REP_XCRYPTCBC_DEFINED   1

◆ XED_IFORM_REP_XCRYPTCFB_DEFINED

#define XED_IFORM_REP_XCRYPTCFB_DEFINED   1

◆ XED_IFORM_REP_XCRYPTCTR_DEFINED

#define XED_IFORM_REP_XCRYPTCTR_DEFINED   1

◆ XED_IFORM_REP_XCRYPTECB_DEFINED

#define XED_IFORM_REP_XCRYPTECB_DEFINED   1

◆ XED_IFORM_REP_XCRYPTOFB_DEFINED

#define XED_IFORM_REP_XCRYPTOFB_DEFINED   1

◆ XED_IFORM_REP_XSHA1_DEFINED

#define XED_IFORM_REP_XSHA1_DEFINED   1

◆ XED_IFORM_REP_XSHA256_DEFINED

#define XED_IFORM_REP_XSHA256_DEFINED   1

◆ XED_IFORM_REP_XSTORE_DEFINED

#define XED_IFORM_REP_XSTORE_DEFINED   1

◆ XED_IFORM_REPE_CMPSB_DEFINED

#define XED_IFORM_REPE_CMPSB_DEFINED   1

◆ XED_IFORM_REPE_CMPSD_DEFINED

#define XED_IFORM_REPE_CMPSD_DEFINED   1

◆ XED_IFORM_REPE_CMPSQ_DEFINED

#define XED_IFORM_REPE_CMPSQ_DEFINED   1

◆ XED_IFORM_REPE_CMPSW_DEFINED

#define XED_IFORM_REPE_CMPSW_DEFINED   1

◆ XED_IFORM_REPE_SCASB_DEFINED

#define XED_IFORM_REPE_SCASB_DEFINED   1

◆ XED_IFORM_REPE_SCASD_DEFINED

#define XED_IFORM_REPE_SCASD_DEFINED   1

◆ XED_IFORM_REPE_SCASQ_DEFINED

#define XED_IFORM_REPE_SCASQ_DEFINED   1

◆ XED_IFORM_REPE_SCASW_DEFINED

#define XED_IFORM_REPE_SCASW_DEFINED   1

◆ XED_IFORM_REPNE_CMPSB_DEFINED

#define XED_IFORM_REPNE_CMPSB_DEFINED   1

◆ XED_IFORM_REPNE_CMPSD_DEFINED

#define XED_IFORM_REPNE_CMPSD_DEFINED   1

◆ XED_IFORM_REPNE_CMPSQ_DEFINED

#define XED_IFORM_REPNE_CMPSQ_DEFINED   1

◆ XED_IFORM_REPNE_CMPSW_DEFINED

#define XED_IFORM_REPNE_CMPSW_DEFINED   1

◆ XED_IFORM_REPNE_SCASB_DEFINED

#define XED_IFORM_REPNE_SCASB_DEFINED   1

◆ XED_IFORM_REPNE_SCASD_DEFINED

#define XED_IFORM_REPNE_SCASD_DEFINED   1

◆ XED_IFORM_REPNE_SCASQ_DEFINED

#define XED_IFORM_REPNE_SCASQ_DEFINED   1

◆ XED_IFORM_REPNE_SCASW_DEFINED

#define XED_IFORM_REPNE_SCASW_DEFINED   1

◆ XED_IFORM_RET_FAR_DEFINED

#define XED_IFORM_RET_FAR_DEFINED   1

◆ XED_IFORM_RET_FAR_IMMw_DEFINED

#define XED_IFORM_RET_FAR_IMMw_DEFINED   1

◆ XED_IFORM_RET_NEAR_DEFINED

#define XED_IFORM_RET_NEAR_DEFINED   1

◆ XED_IFORM_RET_NEAR_IMMw_DEFINED

#define XED_IFORM_RET_NEAR_IMMw_DEFINED   1

◆ XED_IFORM_RMPADJUST_RAX_RCX_RDX_DEFINED

#define XED_IFORM_RMPADJUST_RAX_RCX_RDX_DEFINED   1

◆ XED_IFORM_RMPUPDATE_RAX_RCX_DEFINED

#define XED_IFORM_RMPUPDATE_RAX_RCX_DEFINED   1

◆ XED_IFORM_ROL_GPR8_CL_DEFINED

#define XED_IFORM_ROL_GPR8_CL_DEFINED   1

◆ XED_IFORM_ROL_GPR8_IMMb_DEFINED

#define XED_IFORM_ROL_GPR8_IMMb_DEFINED   1

◆ XED_IFORM_ROL_GPR8_ONE_DEFINED

#define XED_IFORM_ROL_GPR8_ONE_DEFINED   1

◆ XED_IFORM_ROL_GPR8i8_CL_APX_DEFINED

#define XED_IFORM_ROL_GPR8i8_CL_APX_DEFINED   1

◆ XED_IFORM_ROL_GPR8i8_GPR8i8_CL_APX_DEFINED

#define XED_IFORM_ROL_GPR8i8_GPR8i8_CL_APX_DEFINED   1

◆ XED_IFORM_ROL_GPR8i8_GPR8i8_IMM8_APX_DEFINED

#define XED_IFORM_ROL_GPR8i8_GPR8i8_IMM8_APX_DEFINED   1

◆ XED_IFORM_ROL_GPR8i8_GPR8i8_ONE_APX_DEFINED

#define XED_IFORM_ROL_GPR8i8_GPR8i8_ONE_APX_DEFINED   1

◆ XED_IFORM_ROL_GPR8i8_IMM8_APX_DEFINED

#define XED_IFORM_ROL_GPR8i8_IMM8_APX_DEFINED   1

◆ XED_IFORM_ROL_GPR8i8_MEMi8_CL_APX_DEFINED

#define XED_IFORM_ROL_GPR8i8_MEMi8_CL_APX_DEFINED   1

◆ XED_IFORM_ROL_GPR8i8_MEMi8_IMM8_APX_DEFINED

#define XED_IFORM_ROL_GPR8i8_MEMi8_IMM8_APX_DEFINED   1

◆ XED_IFORM_ROL_GPR8i8_MEMi8_ONE_APX_DEFINED

#define XED_IFORM_ROL_GPR8i8_MEMi8_ONE_APX_DEFINED   1

◆ XED_IFORM_ROL_GPR8i8_ONE_APX_DEFINED

#define XED_IFORM_ROL_GPR8i8_ONE_APX_DEFINED   1

◆ XED_IFORM_ROL_GPRv_CL_APX_DEFINED

#define XED_IFORM_ROL_GPRv_CL_APX_DEFINED   1

◆ XED_IFORM_ROL_GPRv_CL_DEFINED

#define XED_IFORM_ROL_GPRv_CL_DEFINED   1

◆ XED_IFORM_ROL_GPRv_GPRv_CL_APX_DEFINED

#define XED_IFORM_ROL_GPRv_GPRv_CL_APX_DEFINED   1

◆ XED_IFORM_ROL_GPRv_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_ROL_GPRv_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_ROL_GPRv_GPRv_ONE_APX_DEFINED

#define XED_IFORM_ROL_GPRv_GPRv_ONE_APX_DEFINED   1

◆ XED_IFORM_ROL_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_ROL_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_ROL_GPRv_IMMb_DEFINED

#define XED_IFORM_ROL_GPRv_IMMb_DEFINED   1

◆ XED_IFORM_ROL_GPRv_MEMv_CL_APX_DEFINED

#define XED_IFORM_ROL_GPRv_MEMv_CL_APX_DEFINED   1

◆ XED_IFORM_ROL_GPRv_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_ROL_GPRv_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_ROL_GPRv_MEMv_ONE_APX_DEFINED

#define XED_IFORM_ROL_GPRv_MEMv_ONE_APX_DEFINED   1

◆ XED_IFORM_ROL_GPRv_ONE_APX_DEFINED

#define XED_IFORM_ROL_GPRv_ONE_APX_DEFINED   1

◆ XED_IFORM_ROL_GPRv_ONE_DEFINED

#define XED_IFORM_ROL_GPRv_ONE_DEFINED   1

◆ XED_IFORM_ROL_MEMb_CL_DEFINED

#define XED_IFORM_ROL_MEMb_CL_DEFINED   1

◆ XED_IFORM_ROL_MEMb_IMMb_DEFINED

#define XED_IFORM_ROL_MEMb_IMMb_DEFINED   1

◆ XED_IFORM_ROL_MEMb_ONE_DEFINED

#define XED_IFORM_ROL_MEMb_ONE_DEFINED   1

◆ XED_IFORM_ROL_MEMi8_CL_APX_DEFINED

#define XED_IFORM_ROL_MEMi8_CL_APX_DEFINED   1

◆ XED_IFORM_ROL_MEMi8_IMM8_APX_DEFINED

#define XED_IFORM_ROL_MEMi8_IMM8_APX_DEFINED   1

◆ XED_IFORM_ROL_MEMi8_ONE_APX_DEFINED

#define XED_IFORM_ROL_MEMi8_ONE_APX_DEFINED   1

◆ XED_IFORM_ROL_MEMv_CL_APX_DEFINED

#define XED_IFORM_ROL_MEMv_CL_APX_DEFINED   1

◆ XED_IFORM_ROL_MEMv_CL_DEFINED

#define XED_IFORM_ROL_MEMv_CL_DEFINED   1

◆ XED_IFORM_ROL_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_ROL_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_ROL_MEMv_IMMb_DEFINED

#define XED_IFORM_ROL_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_ROL_MEMv_ONE_APX_DEFINED

#define XED_IFORM_ROL_MEMv_ONE_APX_DEFINED   1

◆ XED_IFORM_ROL_MEMv_ONE_DEFINED

#define XED_IFORM_ROL_MEMv_ONE_DEFINED   1

◆ XED_IFORM_ROR_GPR8_CL_DEFINED

#define XED_IFORM_ROR_GPR8_CL_DEFINED   1

◆ XED_IFORM_ROR_GPR8_IMMb_DEFINED

#define XED_IFORM_ROR_GPR8_IMMb_DEFINED   1

◆ XED_IFORM_ROR_GPR8_ONE_DEFINED

#define XED_IFORM_ROR_GPR8_ONE_DEFINED   1

◆ XED_IFORM_ROR_GPR8i8_CL_APX_DEFINED

#define XED_IFORM_ROR_GPR8i8_CL_APX_DEFINED   1

◆ XED_IFORM_ROR_GPR8i8_GPR8i8_CL_APX_DEFINED

#define XED_IFORM_ROR_GPR8i8_GPR8i8_CL_APX_DEFINED   1

◆ XED_IFORM_ROR_GPR8i8_GPR8i8_IMM8_APX_DEFINED

#define XED_IFORM_ROR_GPR8i8_GPR8i8_IMM8_APX_DEFINED   1

◆ XED_IFORM_ROR_GPR8i8_GPR8i8_ONE_APX_DEFINED

#define XED_IFORM_ROR_GPR8i8_GPR8i8_ONE_APX_DEFINED   1

◆ XED_IFORM_ROR_GPR8i8_IMM8_APX_DEFINED

#define XED_IFORM_ROR_GPR8i8_IMM8_APX_DEFINED   1

◆ XED_IFORM_ROR_GPR8i8_MEMi8_CL_APX_DEFINED

#define XED_IFORM_ROR_GPR8i8_MEMi8_CL_APX_DEFINED   1

◆ XED_IFORM_ROR_GPR8i8_MEMi8_IMM8_APX_DEFINED

#define XED_IFORM_ROR_GPR8i8_MEMi8_IMM8_APX_DEFINED   1

◆ XED_IFORM_ROR_GPR8i8_MEMi8_ONE_APX_DEFINED

#define XED_IFORM_ROR_GPR8i8_MEMi8_ONE_APX_DEFINED   1

◆ XED_IFORM_ROR_GPR8i8_ONE_APX_DEFINED

#define XED_IFORM_ROR_GPR8i8_ONE_APX_DEFINED   1

◆ XED_IFORM_ROR_GPRv_CL_APX_DEFINED

#define XED_IFORM_ROR_GPRv_CL_APX_DEFINED   1

◆ XED_IFORM_ROR_GPRv_CL_DEFINED

#define XED_IFORM_ROR_GPRv_CL_DEFINED   1

◆ XED_IFORM_ROR_GPRv_GPRv_CL_APX_DEFINED

#define XED_IFORM_ROR_GPRv_GPRv_CL_APX_DEFINED   1

◆ XED_IFORM_ROR_GPRv_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_ROR_GPRv_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_ROR_GPRv_GPRv_ONE_APX_DEFINED

#define XED_IFORM_ROR_GPRv_GPRv_ONE_APX_DEFINED   1

◆ XED_IFORM_ROR_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_ROR_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_ROR_GPRv_IMMb_DEFINED

#define XED_IFORM_ROR_GPRv_IMMb_DEFINED   1

◆ XED_IFORM_ROR_GPRv_MEMv_CL_APX_DEFINED

#define XED_IFORM_ROR_GPRv_MEMv_CL_APX_DEFINED   1

◆ XED_IFORM_ROR_GPRv_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_ROR_GPRv_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_ROR_GPRv_MEMv_ONE_APX_DEFINED

#define XED_IFORM_ROR_GPRv_MEMv_ONE_APX_DEFINED   1

◆ XED_IFORM_ROR_GPRv_ONE_APX_DEFINED

#define XED_IFORM_ROR_GPRv_ONE_APX_DEFINED   1

◆ XED_IFORM_ROR_GPRv_ONE_DEFINED

#define XED_IFORM_ROR_GPRv_ONE_DEFINED   1

◆ XED_IFORM_ROR_MEMb_CL_DEFINED

#define XED_IFORM_ROR_MEMb_CL_DEFINED   1

◆ XED_IFORM_ROR_MEMb_IMMb_DEFINED

#define XED_IFORM_ROR_MEMb_IMMb_DEFINED   1

◆ XED_IFORM_ROR_MEMb_ONE_DEFINED

#define XED_IFORM_ROR_MEMb_ONE_DEFINED   1

◆ XED_IFORM_ROR_MEMi8_CL_APX_DEFINED

#define XED_IFORM_ROR_MEMi8_CL_APX_DEFINED   1

◆ XED_IFORM_ROR_MEMi8_IMM8_APX_DEFINED

#define XED_IFORM_ROR_MEMi8_IMM8_APX_DEFINED   1

◆ XED_IFORM_ROR_MEMi8_ONE_APX_DEFINED

#define XED_IFORM_ROR_MEMi8_ONE_APX_DEFINED   1

◆ XED_IFORM_ROR_MEMv_CL_APX_DEFINED

#define XED_IFORM_ROR_MEMv_CL_APX_DEFINED   1

◆ XED_IFORM_ROR_MEMv_CL_DEFINED

#define XED_IFORM_ROR_MEMv_CL_DEFINED   1

◆ XED_IFORM_ROR_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_ROR_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_ROR_MEMv_IMMb_DEFINED

#define XED_IFORM_ROR_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_ROR_MEMv_ONE_APX_DEFINED

#define XED_IFORM_ROR_MEMv_ONE_APX_DEFINED   1

◆ XED_IFORM_ROR_MEMv_ONE_DEFINED

#define XED_IFORM_ROR_MEMv_ONE_DEFINED   1

◆ XED_IFORM_RORX_GPR32d_GPR32d_IMMb_DEFINED

#define XED_IFORM_RORX_GPR32d_GPR32d_IMMb_DEFINED   1

◆ XED_IFORM_RORX_GPR32d_MEMd_IMMb_DEFINED

#define XED_IFORM_RORX_GPR32d_MEMd_IMMb_DEFINED   1

◆ XED_IFORM_RORX_GPR32i32_GPR32i32_IMM8_APX_DEFINED

#define XED_IFORM_RORX_GPR32i32_GPR32i32_IMM8_APX_DEFINED   1

◆ XED_IFORM_RORX_GPR32i32_MEMi32_IMM8_APX_DEFINED

#define XED_IFORM_RORX_GPR32i32_MEMi32_IMM8_APX_DEFINED   1

◆ XED_IFORM_RORX_GPR64i64_GPR64i64_IMM8_APX_DEFINED

#define XED_IFORM_RORX_GPR64i64_GPR64i64_IMM8_APX_DEFINED   1

◆ XED_IFORM_RORX_GPR64i64_MEMi64_IMM8_APX_DEFINED

#define XED_IFORM_RORX_GPR64i64_MEMi64_IMM8_APX_DEFINED   1

◆ XED_IFORM_RORX_GPR64q_GPR64q_IMMb_DEFINED

#define XED_IFORM_RORX_GPR64q_GPR64q_IMMb_DEFINED   1

◆ XED_IFORM_RORX_GPR64q_MEMq_IMMb_DEFINED

#define XED_IFORM_RORX_GPR64q_MEMq_IMMb_DEFINED   1

◆ XED_IFORM_ROUNDPD_XMMpd_MEMpd_IMMb_DEFINED

#define XED_IFORM_ROUNDPD_XMMpd_MEMpd_IMMb_DEFINED   1

◆ XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb_DEFINED

#define XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb_DEFINED   1

◆ XED_IFORM_ROUNDPS_XMMps_MEMps_IMMb_DEFINED

#define XED_IFORM_ROUNDPS_XMMps_MEMps_IMMb_DEFINED   1

◆ XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb_DEFINED

#define XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb_DEFINED   1

◆ XED_IFORM_ROUNDSD_XMMq_MEMq_IMMb_DEFINED

#define XED_IFORM_ROUNDSD_XMMq_MEMq_IMMb_DEFINED   1

◆ XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb_DEFINED

#define XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb_DEFINED   1

◆ XED_IFORM_ROUNDSS_XMMd_MEMd_IMMb_DEFINED

#define XED_IFORM_ROUNDSS_XMMd_MEMd_IMMb_DEFINED   1

◆ XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb_DEFINED

#define XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb_DEFINED   1

◆ XED_IFORM_RSM_DEFINED

#define XED_IFORM_RSM_DEFINED   1

◆ XED_IFORM_RSQRTPS_XMMps_MEMps_DEFINED

#define XED_IFORM_RSQRTPS_XMMps_MEMps_DEFINED   1

◆ XED_IFORM_RSQRTPS_XMMps_XMMps_DEFINED

#define XED_IFORM_RSQRTPS_XMMps_XMMps_DEFINED   1

◆ XED_IFORM_RSQRTSS_XMMss_MEMss_DEFINED

#define XED_IFORM_RSQRTSS_XMMss_MEMss_DEFINED   1

◆ XED_IFORM_RSQRTSS_XMMss_XMMss_DEFINED

#define XED_IFORM_RSQRTSS_XMMss_XMMss_DEFINED   1

◆ XED_IFORM_RSTORSSP_MEMu64_DEFINED

#define XED_IFORM_RSTORSSP_MEMu64_DEFINED   1

◆ XED_IFORM_SAHF_DEFINED

#define XED_IFORM_SAHF_DEFINED   1

◆ XED_IFORM_SALC_DEFINED

#define XED_IFORM_SALC_DEFINED   1

◆ XED_IFORM_SAR_GPR8_CL_DEFINED

#define XED_IFORM_SAR_GPR8_CL_DEFINED   1

◆ XED_IFORM_SAR_GPR8_IMMb_DEFINED

#define XED_IFORM_SAR_GPR8_IMMb_DEFINED   1

◆ XED_IFORM_SAR_GPR8_ONE_DEFINED

#define XED_IFORM_SAR_GPR8_ONE_DEFINED   1

◆ XED_IFORM_SAR_GPR8i8_CL_APX_DEFINED

#define XED_IFORM_SAR_GPR8i8_CL_APX_DEFINED   1

◆ XED_IFORM_SAR_GPR8i8_GPR8i8_CL_APX_DEFINED

#define XED_IFORM_SAR_GPR8i8_GPR8i8_CL_APX_DEFINED   1

◆ XED_IFORM_SAR_GPR8i8_GPR8i8_IMM8_APX_DEFINED

#define XED_IFORM_SAR_GPR8i8_GPR8i8_IMM8_APX_DEFINED   1

◆ XED_IFORM_SAR_GPR8i8_GPR8i8_ONE_APX_DEFINED

#define XED_IFORM_SAR_GPR8i8_GPR8i8_ONE_APX_DEFINED   1

◆ XED_IFORM_SAR_GPR8i8_IMM8_APX_DEFINED

#define XED_IFORM_SAR_GPR8i8_IMM8_APX_DEFINED   1

◆ XED_IFORM_SAR_GPR8i8_MEMi8_CL_APX_DEFINED

#define XED_IFORM_SAR_GPR8i8_MEMi8_CL_APX_DEFINED   1

◆ XED_IFORM_SAR_GPR8i8_MEMi8_IMM8_APX_DEFINED

#define XED_IFORM_SAR_GPR8i8_MEMi8_IMM8_APX_DEFINED   1

◆ XED_IFORM_SAR_GPR8i8_MEMi8_ONE_APX_DEFINED

#define XED_IFORM_SAR_GPR8i8_MEMi8_ONE_APX_DEFINED   1

◆ XED_IFORM_SAR_GPR8i8_ONE_APX_DEFINED

#define XED_IFORM_SAR_GPR8i8_ONE_APX_DEFINED   1

◆ XED_IFORM_SAR_GPRv_CL_APX_DEFINED

#define XED_IFORM_SAR_GPRv_CL_APX_DEFINED   1

◆ XED_IFORM_SAR_GPRv_CL_DEFINED

#define XED_IFORM_SAR_GPRv_CL_DEFINED   1

◆ XED_IFORM_SAR_GPRv_GPRv_CL_APX_DEFINED

#define XED_IFORM_SAR_GPRv_GPRv_CL_APX_DEFINED   1

◆ XED_IFORM_SAR_GPRv_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_SAR_GPRv_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_SAR_GPRv_GPRv_ONE_APX_DEFINED

#define XED_IFORM_SAR_GPRv_GPRv_ONE_APX_DEFINED   1

◆ XED_IFORM_SAR_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_SAR_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_SAR_GPRv_IMMb_DEFINED

#define XED_IFORM_SAR_GPRv_IMMb_DEFINED   1

◆ XED_IFORM_SAR_GPRv_MEMv_CL_APX_DEFINED

#define XED_IFORM_SAR_GPRv_MEMv_CL_APX_DEFINED   1

◆ XED_IFORM_SAR_GPRv_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_SAR_GPRv_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_SAR_GPRv_MEMv_ONE_APX_DEFINED

#define XED_IFORM_SAR_GPRv_MEMv_ONE_APX_DEFINED   1

◆ XED_IFORM_SAR_GPRv_ONE_APX_DEFINED

#define XED_IFORM_SAR_GPRv_ONE_APX_DEFINED   1

◆ XED_IFORM_SAR_GPRv_ONE_DEFINED

#define XED_IFORM_SAR_GPRv_ONE_DEFINED   1

◆ XED_IFORM_SAR_MEMb_CL_DEFINED

#define XED_IFORM_SAR_MEMb_CL_DEFINED   1

◆ XED_IFORM_SAR_MEMb_IMMb_DEFINED

#define XED_IFORM_SAR_MEMb_IMMb_DEFINED   1

◆ XED_IFORM_SAR_MEMb_ONE_DEFINED

#define XED_IFORM_SAR_MEMb_ONE_DEFINED   1

◆ XED_IFORM_SAR_MEMi8_CL_APX_DEFINED

#define XED_IFORM_SAR_MEMi8_CL_APX_DEFINED   1

◆ XED_IFORM_SAR_MEMi8_IMM8_APX_DEFINED

#define XED_IFORM_SAR_MEMi8_IMM8_APX_DEFINED   1

◆ XED_IFORM_SAR_MEMi8_ONE_APX_DEFINED

#define XED_IFORM_SAR_MEMi8_ONE_APX_DEFINED   1

◆ XED_IFORM_SAR_MEMv_CL_APX_DEFINED

#define XED_IFORM_SAR_MEMv_CL_APX_DEFINED   1

◆ XED_IFORM_SAR_MEMv_CL_DEFINED

#define XED_IFORM_SAR_MEMv_CL_DEFINED   1

◆ XED_IFORM_SAR_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_SAR_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_SAR_MEMv_IMMb_DEFINED

#define XED_IFORM_SAR_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_SAR_MEMv_ONE_APX_DEFINED

#define XED_IFORM_SAR_MEMv_ONE_APX_DEFINED   1

◆ XED_IFORM_SAR_MEMv_ONE_DEFINED

#define XED_IFORM_SAR_MEMv_ONE_DEFINED   1

◆ XED_IFORM_SARX_GPR32d_GPR32d_GPR32d_DEFINED

#define XED_IFORM_SARX_GPR32d_GPR32d_GPR32d_DEFINED   1

◆ XED_IFORM_SARX_GPR32d_MEMd_GPR32d_DEFINED

#define XED_IFORM_SARX_GPR32d_MEMd_GPR32d_DEFINED   1

◆ XED_IFORM_SARX_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED

#define XED_IFORM_SARX_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED   1

◆ XED_IFORM_SARX_GPR32i32_MEMi32_GPR32i32_APX_DEFINED

#define XED_IFORM_SARX_GPR32i32_MEMi32_GPR32i32_APX_DEFINED   1

◆ XED_IFORM_SARX_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED

#define XED_IFORM_SARX_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED   1

◆ XED_IFORM_SARX_GPR64i64_MEMi64_GPR64i64_APX_DEFINED

#define XED_IFORM_SARX_GPR64i64_MEMi64_GPR64i64_APX_DEFINED   1

◆ XED_IFORM_SARX_GPR64q_GPR64q_GPR64q_DEFINED

#define XED_IFORM_SARX_GPR64q_GPR64q_GPR64q_DEFINED   1

◆ XED_IFORM_SARX_GPR64q_MEMq_GPR64q_DEFINED

#define XED_IFORM_SARX_GPR64q_MEMq_GPR64q_DEFINED   1

◆ XED_IFORM_SAVEPREVSSP_DEFINED

#define XED_IFORM_SAVEPREVSSP_DEFINED   1

◆ XED_IFORM_SBB_AL_IMMb_DEFINED

#define XED_IFORM_SBB_AL_IMMb_DEFINED   1

◆ XED_IFORM_SBB_GPR8_GPR8_18_DEFINED

#define XED_IFORM_SBB_GPR8_GPR8_18_DEFINED   1

◆ XED_IFORM_SBB_GPR8_GPR8_1A_DEFINED

#define XED_IFORM_SBB_GPR8_GPR8_1A_DEFINED   1

◆ XED_IFORM_SBB_GPR8_IMMb_80r3_DEFINED

#define XED_IFORM_SBB_GPR8_IMMb_80r3_DEFINED   1

◆ XED_IFORM_SBB_GPR8_IMMb_82r3_DEFINED

#define XED_IFORM_SBB_GPR8_IMMb_82r3_DEFINED   1

◆ XED_IFORM_SBB_GPR8_MEMb_DEFINED

#define XED_IFORM_SBB_GPR8_MEMb_DEFINED   1

◆ XED_IFORM_SBB_GPR8i8_GPR8i8_APX_DEFINED

#define XED_IFORM_SBB_GPR8i8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_SBB_GPR8i8_GPR8i8_GPR8i8_APX_DEFINED

#define XED_IFORM_SBB_GPR8i8_GPR8i8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_SBB_GPR8i8_GPR8i8_IMM8_APX_DEFINED

#define XED_IFORM_SBB_GPR8i8_GPR8i8_IMM8_APX_DEFINED   1

◆ XED_IFORM_SBB_GPR8i8_GPR8i8_MEMi8_APX_DEFINED

#define XED_IFORM_SBB_GPR8i8_GPR8i8_MEMi8_APX_DEFINED   1

◆ XED_IFORM_SBB_GPR8i8_IMM8_APX_DEFINED

#define XED_IFORM_SBB_GPR8i8_IMM8_APX_DEFINED   1

◆ XED_IFORM_SBB_GPR8i8_MEMi8_APX_DEFINED

#define XED_IFORM_SBB_GPR8i8_MEMi8_APX_DEFINED   1

◆ XED_IFORM_SBB_GPR8i8_MEMi8_GPR8i8_APX_DEFINED

#define XED_IFORM_SBB_GPR8i8_MEMi8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_SBB_GPR8i8_MEMi8_IMM8_APX_DEFINED

#define XED_IFORM_SBB_GPR8i8_MEMi8_IMM8_APX_DEFINED   1

◆ XED_IFORM_SBB_GPRv_GPRv_19_DEFINED

#define XED_IFORM_SBB_GPRv_GPRv_19_DEFINED   1

◆ XED_IFORM_SBB_GPRv_GPRv_1B_DEFINED

#define XED_IFORM_SBB_GPRv_GPRv_1B_DEFINED   1

◆ XED_IFORM_SBB_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_SBB_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_SBB_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_SBB_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_SBB_GPRv_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_SBB_GPRv_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_SBB_GPRv_GPRv_IMMz_APX_DEFINED

#define XED_IFORM_SBB_GPRv_GPRv_IMMz_APX_DEFINED   1

◆ XED_IFORM_SBB_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_SBB_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_SBB_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_SBB_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_SBB_GPRv_IMMb_DEFINED

#define XED_IFORM_SBB_GPRv_IMMb_DEFINED   1

◆ XED_IFORM_SBB_GPRv_IMMz_APX_DEFINED

#define XED_IFORM_SBB_GPRv_IMMz_APX_DEFINED   1

◆ XED_IFORM_SBB_GPRv_IMMz_DEFINED

#define XED_IFORM_SBB_GPRv_IMMz_DEFINED   1

◆ XED_IFORM_SBB_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_SBB_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_SBB_GPRv_MEMv_DEFINED

#define XED_IFORM_SBB_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_SBB_GPRv_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_SBB_GPRv_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_SBB_GPRv_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_SBB_GPRv_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_SBB_GPRv_MEMv_IMMz_APX_DEFINED

#define XED_IFORM_SBB_GPRv_MEMv_IMMz_APX_DEFINED   1

◆ XED_IFORM_SBB_LOCK_MEMb_GPR8_DEFINED

#define XED_IFORM_SBB_LOCK_MEMb_GPR8_DEFINED   1

◆ XED_IFORM_SBB_LOCK_MEMb_IMMb_80r3_DEFINED

#define XED_IFORM_SBB_LOCK_MEMb_IMMb_80r3_DEFINED   1

◆ XED_IFORM_SBB_LOCK_MEMb_IMMb_82r3_DEFINED

#define XED_IFORM_SBB_LOCK_MEMb_IMMb_82r3_DEFINED   1

◆ XED_IFORM_SBB_LOCK_MEMv_GPRv_DEFINED

#define XED_IFORM_SBB_LOCK_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_SBB_LOCK_MEMv_IMMb_DEFINED

#define XED_IFORM_SBB_LOCK_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_SBB_LOCK_MEMv_IMMz_DEFINED

#define XED_IFORM_SBB_LOCK_MEMv_IMMz_DEFINED   1

◆ XED_IFORM_SBB_MEMb_GPR8_DEFINED

#define XED_IFORM_SBB_MEMb_GPR8_DEFINED   1

◆ XED_IFORM_SBB_MEMb_IMMb_80r3_DEFINED

#define XED_IFORM_SBB_MEMb_IMMb_80r3_DEFINED   1

◆ XED_IFORM_SBB_MEMb_IMMb_82r3_DEFINED

#define XED_IFORM_SBB_MEMb_IMMb_82r3_DEFINED   1

◆ XED_IFORM_SBB_MEMi8_GPR8i8_APX_DEFINED

#define XED_IFORM_SBB_MEMi8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_SBB_MEMi8_IMM8_APX_DEFINED

#define XED_IFORM_SBB_MEMi8_IMM8_APX_DEFINED   1

◆ XED_IFORM_SBB_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_SBB_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_SBB_MEMv_GPRv_DEFINED

#define XED_IFORM_SBB_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_SBB_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_SBB_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_SBB_MEMv_IMMb_DEFINED

#define XED_IFORM_SBB_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_SBB_MEMv_IMMz_APX_DEFINED

#define XED_IFORM_SBB_MEMv_IMMz_APX_DEFINED   1

◆ XED_IFORM_SBB_MEMv_IMMz_DEFINED

#define XED_IFORM_SBB_MEMv_IMMz_DEFINED   1

◆ XED_IFORM_SBB_OrAX_IMMz_DEFINED

#define XED_IFORM_SBB_OrAX_IMMz_DEFINED   1

◆ XED_IFORM_SCASB_DEFINED

#define XED_IFORM_SCASB_DEFINED   1

◆ XED_IFORM_SCASD_DEFINED

#define XED_IFORM_SCASD_DEFINED   1

◆ XED_IFORM_SCASQ_DEFINED

#define XED_IFORM_SCASQ_DEFINED   1

◆ XED_IFORM_SCASW_DEFINED

#define XED_IFORM_SCASW_DEFINED   1

◆ XED_IFORM_SEAMCALL_DEFINED

#define XED_IFORM_SEAMCALL_DEFINED   1

◆ XED_IFORM_SEAMOPS_DEFINED

#define XED_IFORM_SEAMOPS_DEFINED   1

◆ XED_IFORM_SEAMRET_DEFINED

#define XED_IFORM_SEAMRET_DEFINED   1

◆ XED_IFORM_SENDUIPI_GPR64u32_DEFINED

#define XED_IFORM_SENDUIPI_GPR64u32_DEFINED   1

◆ XED_IFORM_SERIALIZE_DEFINED

#define XED_IFORM_SERIALIZE_DEFINED   1

◆ XED_IFORM_SETB_GPR8_DEFINED

#define XED_IFORM_SETB_GPR8_DEFINED   1

◆ XED_IFORM_SETB_GPR8i8_APX_DEFINED

#define XED_IFORM_SETB_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_SETB_GPR8i8_APX_ZU_DEFINED

#define XED_IFORM_SETB_GPR8i8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETB_MEMb_DEFINED

#define XED_IFORM_SETB_MEMb_DEFINED   1

◆ XED_IFORM_SETB_MEMi8_APX_DEFINED

#define XED_IFORM_SETB_MEMi8_APX_DEFINED   1

◆ XED_IFORM_SETB_MEMi8_APX_ZU_DEFINED

#define XED_IFORM_SETB_MEMi8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETBE_GPR8_DEFINED

#define XED_IFORM_SETBE_GPR8_DEFINED   1

◆ XED_IFORM_SETBE_GPR8i8_APX_DEFINED

#define XED_IFORM_SETBE_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_SETBE_GPR8i8_APX_ZU_DEFINED

#define XED_IFORM_SETBE_GPR8i8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETBE_MEMb_DEFINED

#define XED_IFORM_SETBE_MEMb_DEFINED   1

◆ XED_IFORM_SETBE_MEMi8_APX_DEFINED

#define XED_IFORM_SETBE_MEMi8_APX_DEFINED   1

◆ XED_IFORM_SETBE_MEMi8_APX_ZU_DEFINED

#define XED_IFORM_SETBE_MEMi8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETL_GPR8_DEFINED

#define XED_IFORM_SETL_GPR8_DEFINED   1

◆ XED_IFORM_SETL_GPR8i8_APX_DEFINED

#define XED_IFORM_SETL_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_SETL_GPR8i8_APX_ZU_DEFINED

#define XED_IFORM_SETL_GPR8i8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETL_MEMb_DEFINED

#define XED_IFORM_SETL_MEMb_DEFINED   1

◆ XED_IFORM_SETL_MEMi8_APX_DEFINED

#define XED_IFORM_SETL_MEMi8_APX_DEFINED   1

◆ XED_IFORM_SETL_MEMi8_APX_ZU_DEFINED

#define XED_IFORM_SETL_MEMi8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETLE_GPR8_DEFINED

#define XED_IFORM_SETLE_GPR8_DEFINED   1

◆ XED_IFORM_SETLE_GPR8i8_APX_DEFINED

#define XED_IFORM_SETLE_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_SETLE_GPR8i8_APX_ZU_DEFINED

#define XED_IFORM_SETLE_GPR8i8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETLE_MEMb_DEFINED

#define XED_IFORM_SETLE_MEMb_DEFINED   1

◆ XED_IFORM_SETLE_MEMi8_APX_DEFINED

#define XED_IFORM_SETLE_MEMi8_APX_DEFINED   1

◆ XED_IFORM_SETLE_MEMi8_APX_ZU_DEFINED

#define XED_IFORM_SETLE_MEMi8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETNB_GPR8_DEFINED

#define XED_IFORM_SETNB_GPR8_DEFINED   1

◆ XED_IFORM_SETNB_GPR8i8_APX_DEFINED

#define XED_IFORM_SETNB_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_SETNB_GPR8i8_APX_ZU_DEFINED

#define XED_IFORM_SETNB_GPR8i8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETNB_MEMb_DEFINED

#define XED_IFORM_SETNB_MEMb_DEFINED   1

◆ XED_IFORM_SETNB_MEMi8_APX_DEFINED

#define XED_IFORM_SETNB_MEMi8_APX_DEFINED   1

◆ XED_IFORM_SETNB_MEMi8_APX_ZU_DEFINED

#define XED_IFORM_SETNB_MEMi8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETNBE_GPR8_DEFINED

#define XED_IFORM_SETNBE_GPR8_DEFINED   1

◆ XED_IFORM_SETNBE_GPR8i8_APX_DEFINED

#define XED_IFORM_SETNBE_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_SETNBE_GPR8i8_APX_ZU_DEFINED

#define XED_IFORM_SETNBE_GPR8i8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETNBE_MEMb_DEFINED

#define XED_IFORM_SETNBE_MEMb_DEFINED   1

◆ XED_IFORM_SETNBE_MEMi8_APX_DEFINED

#define XED_IFORM_SETNBE_MEMi8_APX_DEFINED   1

◆ XED_IFORM_SETNBE_MEMi8_APX_ZU_DEFINED

#define XED_IFORM_SETNBE_MEMi8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETNL_GPR8_DEFINED

#define XED_IFORM_SETNL_GPR8_DEFINED   1

◆ XED_IFORM_SETNL_GPR8i8_APX_DEFINED

#define XED_IFORM_SETNL_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_SETNL_GPR8i8_APX_ZU_DEFINED

#define XED_IFORM_SETNL_GPR8i8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETNL_MEMb_DEFINED

#define XED_IFORM_SETNL_MEMb_DEFINED   1

◆ XED_IFORM_SETNL_MEMi8_APX_DEFINED

#define XED_IFORM_SETNL_MEMi8_APX_DEFINED   1

◆ XED_IFORM_SETNL_MEMi8_APX_ZU_DEFINED

#define XED_IFORM_SETNL_MEMi8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETNLE_GPR8_DEFINED

#define XED_IFORM_SETNLE_GPR8_DEFINED   1

◆ XED_IFORM_SETNLE_GPR8i8_APX_DEFINED

#define XED_IFORM_SETNLE_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_SETNLE_GPR8i8_APX_ZU_DEFINED

#define XED_IFORM_SETNLE_GPR8i8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETNLE_MEMb_DEFINED

#define XED_IFORM_SETNLE_MEMb_DEFINED   1

◆ XED_IFORM_SETNLE_MEMi8_APX_DEFINED

#define XED_IFORM_SETNLE_MEMi8_APX_DEFINED   1

◆ XED_IFORM_SETNLE_MEMi8_APX_ZU_DEFINED

#define XED_IFORM_SETNLE_MEMi8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETNO_GPR8_DEFINED

#define XED_IFORM_SETNO_GPR8_DEFINED   1

◆ XED_IFORM_SETNO_GPR8i8_APX_DEFINED

#define XED_IFORM_SETNO_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_SETNO_GPR8i8_APX_ZU_DEFINED

#define XED_IFORM_SETNO_GPR8i8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETNO_MEMb_DEFINED

#define XED_IFORM_SETNO_MEMb_DEFINED   1

◆ XED_IFORM_SETNO_MEMi8_APX_DEFINED

#define XED_IFORM_SETNO_MEMi8_APX_DEFINED   1

◆ XED_IFORM_SETNO_MEMi8_APX_ZU_DEFINED

#define XED_IFORM_SETNO_MEMi8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETNP_GPR8_DEFINED

#define XED_IFORM_SETNP_GPR8_DEFINED   1

◆ XED_IFORM_SETNP_GPR8i8_APX_DEFINED

#define XED_IFORM_SETNP_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_SETNP_GPR8i8_APX_ZU_DEFINED

#define XED_IFORM_SETNP_GPR8i8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETNP_MEMb_DEFINED

#define XED_IFORM_SETNP_MEMb_DEFINED   1

◆ XED_IFORM_SETNP_MEMi8_APX_DEFINED

#define XED_IFORM_SETNP_MEMi8_APX_DEFINED   1

◆ XED_IFORM_SETNP_MEMi8_APX_ZU_DEFINED

#define XED_IFORM_SETNP_MEMi8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETNS_GPR8_DEFINED

#define XED_IFORM_SETNS_GPR8_DEFINED   1

◆ XED_IFORM_SETNS_GPR8i8_APX_DEFINED

#define XED_IFORM_SETNS_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_SETNS_GPR8i8_APX_ZU_DEFINED

#define XED_IFORM_SETNS_GPR8i8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETNS_MEMb_DEFINED

#define XED_IFORM_SETNS_MEMb_DEFINED   1

◆ XED_IFORM_SETNS_MEMi8_APX_DEFINED

#define XED_IFORM_SETNS_MEMi8_APX_DEFINED   1

◆ XED_IFORM_SETNS_MEMi8_APX_ZU_DEFINED

#define XED_IFORM_SETNS_MEMi8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETNZ_GPR8_DEFINED

#define XED_IFORM_SETNZ_GPR8_DEFINED   1

◆ XED_IFORM_SETNZ_GPR8i8_APX_DEFINED

#define XED_IFORM_SETNZ_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_SETNZ_GPR8i8_APX_ZU_DEFINED

#define XED_IFORM_SETNZ_GPR8i8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETNZ_MEMb_DEFINED

#define XED_IFORM_SETNZ_MEMb_DEFINED   1

◆ XED_IFORM_SETNZ_MEMi8_APX_DEFINED

#define XED_IFORM_SETNZ_MEMi8_APX_DEFINED   1

◆ XED_IFORM_SETNZ_MEMi8_APX_ZU_DEFINED

#define XED_IFORM_SETNZ_MEMi8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETO_GPR8_DEFINED

#define XED_IFORM_SETO_GPR8_DEFINED   1

◆ XED_IFORM_SETO_GPR8i8_APX_DEFINED

#define XED_IFORM_SETO_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_SETO_GPR8i8_APX_ZU_DEFINED

#define XED_IFORM_SETO_GPR8i8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETO_MEMb_DEFINED

#define XED_IFORM_SETO_MEMb_DEFINED   1

◆ XED_IFORM_SETO_MEMi8_APX_DEFINED

#define XED_IFORM_SETO_MEMi8_APX_DEFINED   1

◆ XED_IFORM_SETO_MEMi8_APX_ZU_DEFINED

#define XED_IFORM_SETO_MEMi8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETP_GPR8_DEFINED

#define XED_IFORM_SETP_GPR8_DEFINED   1

◆ XED_IFORM_SETP_GPR8i8_APX_DEFINED

#define XED_IFORM_SETP_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_SETP_GPR8i8_APX_ZU_DEFINED

#define XED_IFORM_SETP_GPR8i8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETP_MEMb_DEFINED

#define XED_IFORM_SETP_MEMb_DEFINED   1

◆ XED_IFORM_SETP_MEMi8_APX_DEFINED

#define XED_IFORM_SETP_MEMi8_APX_DEFINED   1

◆ XED_IFORM_SETP_MEMi8_APX_ZU_DEFINED

#define XED_IFORM_SETP_MEMi8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETS_GPR8_DEFINED

#define XED_IFORM_SETS_GPR8_DEFINED   1

◆ XED_IFORM_SETS_GPR8i8_APX_DEFINED

#define XED_IFORM_SETS_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_SETS_GPR8i8_APX_ZU_DEFINED

#define XED_IFORM_SETS_GPR8i8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETS_MEMb_DEFINED

#define XED_IFORM_SETS_MEMb_DEFINED   1

◆ XED_IFORM_SETS_MEMi8_APX_DEFINED

#define XED_IFORM_SETS_MEMi8_APX_DEFINED   1

◆ XED_IFORM_SETS_MEMi8_APX_ZU_DEFINED

#define XED_IFORM_SETS_MEMi8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETSSBSY_DEFINED

#define XED_IFORM_SETSSBSY_DEFINED   1

◆ XED_IFORM_SETZ_GPR8_DEFINED

#define XED_IFORM_SETZ_GPR8_DEFINED   1

◆ XED_IFORM_SETZ_GPR8i8_APX_DEFINED

#define XED_IFORM_SETZ_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_SETZ_GPR8i8_APX_ZU_DEFINED

#define XED_IFORM_SETZ_GPR8i8_APX_ZU_DEFINED   1

◆ XED_IFORM_SETZ_MEMb_DEFINED

#define XED_IFORM_SETZ_MEMb_DEFINED   1

◆ XED_IFORM_SETZ_MEMi8_APX_DEFINED

#define XED_IFORM_SETZ_MEMi8_APX_DEFINED   1

◆ XED_IFORM_SETZ_MEMi8_APX_ZU_DEFINED

#define XED_IFORM_SETZ_MEMi8_APX_ZU_DEFINED   1

◆ XED_IFORM_SFENCE_DEFINED

#define XED_IFORM_SFENCE_DEFINED   1

◆ XED_IFORM_SGDT_MEMs64_DEFINED

#define XED_IFORM_SGDT_MEMs64_DEFINED   1

◆ XED_IFORM_SGDT_MEMs_DEFINED

#define XED_IFORM_SGDT_MEMs_DEFINED   1

◆ XED_IFORM_SHA1MSG1_XMMi32_MEMi32_SHA_DEFINED

#define XED_IFORM_SHA1MSG1_XMMi32_MEMi32_SHA_DEFINED   1

◆ XED_IFORM_SHA1MSG1_XMMi32_XMMi32_SHA_DEFINED

#define XED_IFORM_SHA1MSG1_XMMi32_XMMi32_SHA_DEFINED   1

◆ XED_IFORM_SHA1MSG2_XMMi32_MEMi32_SHA_DEFINED

#define XED_IFORM_SHA1MSG2_XMMi32_MEMi32_SHA_DEFINED   1

◆ XED_IFORM_SHA1MSG2_XMMi32_XMMi32_SHA_DEFINED

#define XED_IFORM_SHA1MSG2_XMMi32_XMMi32_SHA_DEFINED   1

◆ XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_SHA_DEFINED

#define XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_SHA_DEFINED   1

◆ XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_SHA_DEFINED

#define XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_SHA_DEFINED   1

◆ XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA_DEFINED

#define XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA_DEFINED   1

◆ XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA_DEFINED

#define XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA_DEFINED   1

◆ XED_IFORM_SHA256MSG1_XMMi32_MEMi32_SHA_DEFINED

#define XED_IFORM_SHA256MSG1_XMMi32_MEMi32_SHA_DEFINED   1

◆ XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA_DEFINED

#define XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA_DEFINED   1

◆ XED_IFORM_SHA256MSG2_XMMi32_MEMi32_SHA_DEFINED

#define XED_IFORM_SHA256MSG2_XMMi32_MEMi32_SHA_DEFINED   1

◆ XED_IFORM_SHA256MSG2_XMMi32_XMMi32_SHA_DEFINED

#define XED_IFORM_SHA256MSG2_XMMi32_XMMi32_SHA_DEFINED   1

◆ XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_SHA_DEFINED

#define XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_SHA_DEFINED   1

◆ XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_SHA_DEFINED

#define XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_SHA_DEFINED   1

◆ XED_IFORM_SHL_GPR8_CL_D2r4_DEFINED

#define XED_IFORM_SHL_GPR8_CL_D2r4_DEFINED   1

◆ XED_IFORM_SHL_GPR8_CL_D2r6_DEFINED

#define XED_IFORM_SHL_GPR8_CL_D2r6_DEFINED   1

◆ XED_IFORM_SHL_GPR8_IMMb_C0r4_DEFINED

#define XED_IFORM_SHL_GPR8_IMMb_C0r4_DEFINED   1

◆ XED_IFORM_SHL_GPR8_IMMb_C0r6_DEFINED

#define XED_IFORM_SHL_GPR8_IMMb_C0r6_DEFINED   1

◆ XED_IFORM_SHL_GPR8_ONE_D0r4_DEFINED

#define XED_IFORM_SHL_GPR8_ONE_D0r4_DEFINED   1

◆ XED_IFORM_SHL_GPR8_ONE_D0r6_DEFINED

#define XED_IFORM_SHL_GPR8_ONE_D0r6_DEFINED   1

◆ XED_IFORM_SHL_GPR8i8_CL_APX_DEFINED

#define XED_IFORM_SHL_GPR8i8_CL_APX_DEFINED   1

◆ XED_IFORM_SHL_GPR8i8_GPR8i8_CL_APX_DEFINED

#define XED_IFORM_SHL_GPR8i8_GPR8i8_CL_APX_DEFINED   1

◆ XED_IFORM_SHL_GPR8i8_GPR8i8_IMM8_APX_DEFINED

#define XED_IFORM_SHL_GPR8i8_GPR8i8_IMM8_APX_DEFINED   1

◆ XED_IFORM_SHL_GPR8i8_GPR8i8_ONE_APX_DEFINED

#define XED_IFORM_SHL_GPR8i8_GPR8i8_ONE_APX_DEFINED   1

◆ XED_IFORM_SHL_GPR8i8_IMM8_APX_DEFINED

#define XED_IFORM_SHL_GPR8i8_IMM8_APX_DEFINED   1

◆ XED_IFORM_SHL_GPR8i8_MEMi8_CL_APX_DEFINED

#define XED_IFORM_SHL_GPR8i8_MEMi8_CL_APX_DEFINED   1

◆ XED_IFORM_SHL_GPR8i8_MEMi8_IMM8_APX_DEFINED

#define XED_IFORM_SHL_GPR8i8_MEMi8_IMM8_APX_DEFINED   1

◆ XED_IFORM_SHL_GPR8i8_MEMi8_ONE_APX_DEFINED

#define XED_IFORM_SHL_GPR8i8_MEMi8_ONE_APX_DEFINED   1

◆ XED_IFORM_SHL_GPR8i8_ONE_APX_DEFINED

#define XED_IFORM_SHL_GPR8i8_ONE_APX_DEFINED   1

◆ XED_IFORM_SHL_GPRv_CL_APX_DEFINED

#define XED_IFORM_SHL_GPRv_CL_APX_DEFINED   1

◆ XED_IFORM_SHL_GPRv_CL_D3r4_DEFINED

#define XED_IFORM_SHL_GPRv_CL_D3r4_DEFINED   1

◆ XED_IFORM_SHL_GPRv_CL_D3r6_DEFINED

#define XED_IFORM_SHL_GPRv_CL_D3r6_DEFINED   1

◆ XED_IFORM_SHL_GPRv_GPRv_CL_APX_DEFINED

#define XED_IFORM_SHL_GPRv_GPRv_CL_APX_DEFINED   1

◆ XED_IFORM_SHL_GPRv_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_SHL_GPRv_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_SHL_GPRv_GPRv_ONE_APX_DEFINED

#define XED_IFORM_SHL_GPRv_GPRv_ONE_APX_DEFINED   1

◆ XED_IFORM_SHL_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_SHL_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_SHL_GPRv_IMMb_C1r4_DEFINED

#define XED_IFORM_SHL_GPRv_IMMb_C1r4_DEFINED   1

◆ XED_IFORM_SHL_GPRv_IMMb_C1r6_DEFINED

#define XED_IFORM_SHL_GPRv_IMMb_C1r6_DEFINED   1

◆ XED_IFORM_SHL_GPRv_MEMv_CL_APX_DEFINED

#define XED_IFORM_SHL_GPRv_MEMv_CL_APX_DEFINED   1

◆ XED_IFORM_SHL_GPRv_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_SHL_GPRv_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_SHL_GPRv_MEMv_ONE_APX_DEFINED

#define XED_IFORM_SHL_GPRv_MEMv_ONE_APX_DEFINED   1

◆ XED_IFORM_SHL_GPRv_ONE_APX_DEFINED

#define XED_IFORM_SHL_GPRv_ONE_APX_DEFINED   1

◆ XED_IFORM_SHL_GPRv_ONE_D1r4_DEFINED

#define XED_IFORM_SHL_GPRv_ONE_D1r4_DEFINED   1

◆ XED_IFORM_SHL_GPRv_ONE_D1r6_DEFINED

#define XED_IFORM_SHL_GPRv_ONE_D1r6_DEFINED   1

◆ XED_IFORM_SHL_MEMb_CL_D2r4_DEFINED

#define XED_IFORM_SHL_MEMb_CL_D2r4_DEFINED   1

◆ XED_IFORM_SHL_MEMb_CL_D2r6_DEFINED

#define XED_IFORM_SHL_MEMb_CL_D2r6_DEFINED   1

◆ XED_IFORM_SHL_MEMb_IMMb_C0r4_DEFINED

#define XED_IFORM_SHL_MEMb_IMMb_C0r4_DEFINED   1

◆ XED_IFORM_SHL_MEMb_IMMb_C0r6_DEFINED

#define XED_IFORM_SHL_MEMb_IMMb_C0r6_DEFINED   1

◆ XED_IFORM_SHL_MEMb_ONE_D0r4_DEFINED

#define XED_IFORM_SHL_MEMb_ONE_D0r4_DEFINED   1

◆ XED_IFORM_SHL_MEMb_ONE_D0r6_DEFINED

#define XED_IFORM_SHL_MEMb_ONE_D0r6_DEFINED   1

◆ XED_IFORM_SHL_MEMi8_CL_APX_DEFINED

#define XED_IFORM_SHL_MEMi8_CL_APX_DEFINED   1

◆ XED_IFORM_SHL_MEMi8_IMM8_APX_DEFINED

#define XED_IFORM_SHL_MEMi8_IMM8_APX_DEFINED   1

◆ XED_IFORM_SHL_MEMi8_ONE_APX_DEFINED

#define XED_IFORM_SHL_MEMi8_ONE_APX_DEFINED   1

◆ XED_IFORM_SHL_MEMv_CL_APX_DEFINED

#define XED_IFORM_SHL_MEMv_CL_APX_DEFINED   1

◆ XED_IFORM_SHL_MEMv_CL_D3r4_DEFINED

#define XED_IFORM_SHL_MEMv_CL_D3r4_DEFINED   1

◆ XED_IFORM_SHL_MEMv_CL_D3r6_DEFINED

#define XED_IFORM_SHL_MEMv_CL_D3r6_DEFINED   1

◆ XED_IFORM_SHL_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_SHL_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_SHL_MEMv_IMMb_C1r4_DEFINED

#define XED_IFORM_SHL_MEMv_IMMb_C1r4_DEFINED   1

◆ XED_IFORM_SHL_MEMv_IMMb_C1r6_DEFINED

#define XED_IFORM_SHL_MEMv_IMMb_C1r6_DEFINED   1

◆ XED_IFORM_SHL_MEMv_ONE_APX_DEFINED

#define XED_IFORM_SHL_MEMv_ONE_APX_DEFINED   1

◆ XED_IFORM_SHL_MEMv_ONE_D1r4_DEFINED

#define XED_IFORM_SHL_MEMv_ONE_D1r4_DEFINED   1

◆ XED_IFORM_SHL_MEMv_ONE_D1r6_DEFINED

#define XED_IFORM_SHL_MEMv_ONE_D1r6_DEFINED   1

◆ XED_IFORM_SHLD_GPRv_GPRv_CL_APX_DEFINED

#define XED_IFORM_SHLD_GPRv_GPRv_CL_APX_DEFINED   1

◆ XED_IFORM_SHLD_GPRv_GPRv_CL_DEFINED

#define XED_IFORM_SHLD_GPRv_GPRv_CL_DEFINED   1

◆ XED_IFORM_SHLD_GPRv_GPRv_GPRv_CL_APX_DEFINED

#define XED_IFORM_SHLD_GPRv_GPRv_GPRv_CL_APX_DEFINED   1

◆ XED_IFORM_SHLD_GPRv_GPRv_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_SHLD_GPRv_GPRv_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_SHLD_GPRv_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_SHLD_GPRv_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_SHLD_GPRv_GPRv_IMMb_DEFINED

#define XED_IFORM_SHLD_GPRv_GPRv_IMMb_DEFINED   1

◆ XED_IFORM_SHLD_GPRv_MEMv_GPRv_CL_APX_DEFINED

#define XED_IFORM_SHLD_GPRv_MEMv_GPRv_CL_APX_DEFINED   1

◆ XED_IFORM_SHLD_GPRv_MEMv_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_SHLD_GPRv_MEMv_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_SHLD_MEMv_GPRv_CL_APX_DEFINED

#define XED_IFORM_SHLD_MEMv_GPRv_CL_APX_DEFINED   1

◆ XED_IFORM_SHLD_MEMv_GPRv_CL_DEFINED

#define XED_IFORM_SHLD_MEMv_GPRv_CL_DEFINED   1

◆ XED_IFORM_SHLD_MEMv_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_SHLD_MEMv_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_SHLD_MEMv_GPRv_IMMb_DEFINED

#define XED_IFORM_SHLD_MEMv_GPRv_IMMb_DEFINED   1

◆ XED_IFORM_SHLX_GPR32d_GPR32d_GPR32d_DEFINED

#define XED_IFORM_SHLX_GPR32d_GPR32d_GPR32d_DEFINED   1

◆ XED_IFORM_SHLX_GPR32d_MEMd_GPR32d_DEFINED

#define XED_IFORM_SHLX_GPR32d_MEMd_GPR32d_DEFINED   1

◆ XED_IFORM_SHLX_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED

#define XED_IFORM_SHLX_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED   1

◆ XED_IFORM_SHLX_GPR32i32_MEMi32_GPR32i32_APX_DEFINED

#define XED_IFORM_SHLX_GPR32i32_MEMi32_GPR32i32_APX_DEFINED   1

◆ XED_IFORM_SHLX_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED

#define XED_IFORM_SHLX_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED   1

◆ XED_IFORM_SHLX_GPR64i64_MEMi64_GPR64i64_APX_DEFINED

#define XED_IFORM_SHLX_GPR64i64_MEMi64_GPR64i64_APX_DEFINED   1

◆ XED_IFORM_SHLX_GPR64q_GPR64q_GPR64q_DEFINED

#define XED_IFORM_SHLX_GPR64q_GPR64q_GPR64q_DEFINED   1

◆ XED_IFORM_SHLX_GPR64q_MEMq_GPR64q_DEFINED

#define XED_IFORM_SHLX_GPR64q_MEMq_GPR64q_DEFINED   1

◆ XED_IFORM_SHR_GPR8_CL_DEFINED

#define XED_IFORM_SHR_GPR8_CL_DEFINED   1

◆ XED_IFORM_SHR_GPR8_IMMb_DEFINED

#define XED_IFORM_SHR_GPR8_IMMb_DEFINED   1

◆ XED_IFORM_SHR_GPR8_ONE_DEFINED

#define XED_IFORM_SHR_GPR8_ONE_DEFINED   1

◆ XED_IFORM_SHR_GPR8i8_CL_APX_DEFINED

#define XED_IFORM_SHR_GPR8i8_CL_APX_DEFINED   1

◆ XED_IFORM_SHR_GPR8i8_GPR8i8_CL_APX_DEFINED

#define XED_IFORM_SHR_GPR8i8_GPR8i8_CL_APX_DEFINED   1

◆ XED_IFORM_SHR_GPR8i8_GPR8i8_IMM8_APX_DEFINED

#define XED_IFORM_SHR_GPR8i8_GPR8i8_IMM8_APX_DEFINED   1

◆ XED_IFORM_SHR_GPR8i8_GPR8i8_ONE_APX_DEFINED

#define XED_IFORM_SHR_GPR8i8_GPR8i8_ONE_APX_DEFINED   1

◆ XED_IFORM_SHR_GPR8i8_IMM8_APX_DEFINED

#define XED_IFORM_SHR_GPR8i8_IMM8_APX_DEFINED   1

◆ XED_IFORM_SHR_GPR8i8_MEMi8_CL_APX_DEFINED

#define XED_IFORM_SHR_GPR8i8_MEMi8_CL_APX_DEFINED   1

◆ XED_IFORM_SHR_GPR8i8_MEMi8_IMM8_APX_DEFINED

#define XED_IFORM_SHR_GPR8i8_MEMi8_IMM8_APX_DEFINED   1

◆ XED_IFORM_SHR_GPR8i8_MEMi8_ONE_APX_DEFINED

#define XED_IFORM_SHR_GPR8i8_MEMi8_ONE_APX_DEFINED   1

◆ XED_IFORM_SHR_GPR8i8_ONE_APX_DEFINED

#define XED_IFORM_SHR_GPR8i8_ONE_APX_DEFINED   1

◆ XED_IFORM_SHR_GPRv_CL_APX_DEFINED

#define XED_IFORM_SHR_GPRv_CL_APX_DEFINED   1

◆ XED_IFORM_SHR_GPRv_CL_DEFINED

#define XED_IFORM_SHR_GPRv_CL_DEFINED   1

◆ XED_IFORM_SHR_GPRv_GPRv_CL_APX_DEFINED

#define XED_IFORM_SHR_GPRv_GPRv_CL_APX_DEFINED   1

◆ XED_IFORM_SHR_GPRv_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_SHR_GPRv_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_SHR_GPRv_GPRv_ONE_APX_DEFINED

#define XED_IFORM_SHR_GPRv_GPRv_ONE_APX_DEFINED   1

◆ XED_IFORM_SHR_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_SHR_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_SHR_GPRv_IMMb_DEFINED

#define XED_IFORM_SHR_GPRv_IMMb_DEFINED   1

◆ XED_IFORM_SHR_GPRv_MEMv_CL_APX_DEFINED

#define XED_IFORM_SHR_GPRv_MEMv_CL_APX_DEFINED   1

◆ XED_IFORM_SHR_GPRv_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_SHR_GPRv_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_SHR_GPRv_MEMv_ONE_APX_DEFINED

#define XED_IFORM_SHR_GPRv_MEMv_ONE_APX_DEFINED   1

◆ XED_IFORM_SHR_GPRv_ONE_APX_DEFINED

#define XED_IFORM_SHR_GPRv_ONE_APX_DEFINED   1

◆ XED_IFORM_SHR_GPRv_ONE_DEFINED

#define XED_IFORM_SHR_GPRv_ONE_DEFINED   1

◆ XED_IFORM_SHR_MEMb_CL_DEFINED

#define XED_IFORM_SHR_MEMb_CL_DEFINED   1

◆ XED_IFORM_SHR_MEMb_IMMb_DEFINED

#define XED_IFORM_SHR_MEMb_IMMb_DEFINED   1

◆ XED_IFORM_SHR_MEMb_ONE_DEFINED

#define XED_IFORM_SHR_MEMb_ONE_DEFINED   1

◆ XED_IFORM_SHR_MEMi8_CL_APX_DEFINED

#define XED_IFORM_SHR_MEMi8_CL_APX_DEFINED   1

◆ XED_IFORM_SHR_MEMi8_IMM8_APX_DEFINED

#define XED_IFORM_SHR_MEMi8_IMM8_APX_DEFINED   1

◆ XED_IFORM_SHR_MEMi8_ONE_APX_DEFINED

#define XED_IFORM_SHR_MEMi8_ONE_APX_DEFINED   1

◆ XED_IFORM_SHR_MEMv_CL_APX_DEFINED

#define XED_IFORM_SHR_MEMv_CL_APX_DEFINED   1

◆ XED_IFORM_SHR_MEMv_CL_DEFINED

#define XED_IFORM_SHR_MEMv_CL_DEFINED   1

◆ XED_IFORM_SHR_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_SHR_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_SHR_MEMv_IMMb_DEFINED

#define XED_IFORM_SHR_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_SHR_MEMv_ONE_APX_DEFINED

#define XED_IFORM_SHR_MEMv_ONE_APX_DEFINED   1

◆ XED_IFORM_SHR_MEMv_ONE_DEFINED

#define XED_IFORM_SHR_MEMv_ONE_DEFINED   1

◆ XED_IFORM_SHRD_GPRv_GPRv_CL_APX_DEFINED

#define XED_IFORM_SHRD_GPRv_GPRv_CL_APX_DEFINED   1

◆ XED_IFORM_SHRD_GPRv_GPRv_CL_DEFINED

#define XED_IFORM_SHRD_GPRv_GPRv_CL_DEFINED   1

◆ XED_IFORM_SHRD_GPRv_GPRv_GPRv_CL_APX_DEFINED

#define XED_IFORM_SHRD_GPRv_GPRv_GPRv_CL_APX_DEFINED   1

◆ XED_IFORM_SHRD_GPRv_GPRv_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_SHRD_GPRv_GPRv_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_SHRD_GPRv_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_SHRD_GPRv_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_SHRD_GPRv_GPRv_IMMb_DEFINED

#define XED_IFORM_SHRD_GPRv_GPRv_IMMb_DEFINED   1

◆ XED_IFORM_SHRD_GPRv_MEMv_GPRv_CL_APX_DEFINED

#define XED_IFORM_SHRD_GPRv_MEMv_GPRv_CL_APX_DEFINED   1

◆ XED_IFORM_SHRD_GPRv_MEMv_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_SHRD_GPRv_MEMv_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_SHRD_MEMv_GPRv_CL_APX_DEFINED

#define XED_IFORM_SHRD_MEMv_GPRv_CL_APX_DEFINED   1

◆ XED_IFORM_SHRD_MEMv_GPRv_CL_DEFINED

#define XED_IFORM_SHRD_MEMv_GPRv_CL_DEFINED   1

◆ XED_IFORM_SHRD_MEMv_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_SHRD_MEMv_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_SHRD_MEMv_GPRv_IMMb_DEFINED

#define XED_IFORM_SHRD_MEMv_GPRv_IMMb_DEFINED   1

◆ XED_IFORM_SHRX_GPR32d_GPR32d_GPR32d_DEFINED

#define XED_IFORM_SHRX_GPR32d_GPR32d_GPR32d_DEFINED   1

◆ XED_IFORM_SHRX_GPR32d_MEMd_GPR32d_DEFINED

#define XED_IFORM_SHRX_GPR32d_MEMd_GPR32d_DEFINED   1

◆ XED_IFORM_SHRX_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED

#define XED_IFORM_SHRX_GPR32i32_GPR32i32_GPR32i32_APX_DEFINED   1

◆ XED_IFORM_SHRX_GPR32i32_MEMi32_GPR32i32_APX_DEFINED

#define XED_IFORM_SHRX_GPR32i32_MEMi32_GPR32i32_APX_DEFINED   1

◆ XED_IFORM_SHRX_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED

#define XED_IFORM_SHRX_GPR64i64_GPR64i64_GPR64i64_APX_DEFINED   1

◆ XED_IFORM_SHRX_GPR64i64_MEMi64_GPR64i64_APX_DEFINED

#define XED_IFORM_SHRX_GPR64i64_MEMi64_GPR64i64_APX_DEFINED   1

◆ XED_IFORM_SHRX_GPR64q_GPR64q_GPR64q_DEFINED

#define XED_IFORM_SHRX_GPR64q_GPR64q_GPR64q_DEFINED   1

◆ XED_IFORM_SHRX_GPR64q_MEMq_GPR64q_DEFINED

#define XED_IFORM_SHRX_GPR64q_MEMq_GPR64q_DEFINED   1

◆ XED_IFORM_SHUFPD_XMMpd_MEMpd_IMMb_DEFINED

#define XED_IFORM_SHUFPD_XMMpd_MEMpd_IMMb_DEFINED   1

◆ XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb_DEFINED

#define XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb_DEFINED   1

◆ XED_IFORM_SHUFPS_XMMps_MEMps_IMMb_DEFINED

#define XED_IFORM_SHUFPS_XMMps_MEMps_IMMb_DEFINED   1

◆ XED_IFORM_SHUFPS_XMMps_XMMps_IMMb_DEFINED

#define XED_IFORM_SHUFPS_XMMps_XMMps_IMMb_DEFINED   1

◆ XED_IFORM_SIDT_MEMs64_DEFINED

#define XED_IFORM_SIDT_MEMs64_DEFINED   1

◆ XED_IFORM_SIDT_MEMs_DEFINED

#define XED_IFORM_SIDT_MEMs_DEFINED   1

◆ XED_IFORM_SKINIT_EAX_DEFINED

#define XED_IFORM_SKINIT_EAX_DEFINED   1

◆ XED_IFORM_SLDT_GPRv_DEFINED

#define XED_IFORM_SLDT_GPRv_DEFINED   1

◆ XED_IFORM_SLDT_MEMw_DEFINED

#define XED_IFORM_SLDT_MEMw_DEFINED   1

◆ XED_IFORM_SLWPCB_GPRyy_DEFINED

#define XED_IFORM_SLWPCB_GPRyy_DEFINED   1

◆ XED_IFORM_SMSW_GPRv_DEFINED

#define XED_IFORM_SMSW_GPRv_DEFINED   1

◆ XED_IFORM_SMSW_MEMw_DEFINED

#define XED_IFORM_SMSW_MEMw_DEFINED   1

◆ XED_IFORM_SQRTPD_XMMpd_MEMpd_DEFINED

#define XED_IFORM_SQRTPD_XMMpd_MEMpd_DEFINED   1

◆ XED_IFORM_SQRTPD_XMMpd_XMMpd_DEFINED

#define XED_IFORM_SQRTPD_XMMpd_XMMpd_DEFINED   1

◆ XED_IFORM_SQRTPS_XMMps_MEMps_DEFINED

#define XED_IFORM_SQRTPS_XMMps_MEMps_DEFINED   1

◆ XED_IFORM_SQRTPS_XMMps_XMMps_DEFINED

#define XED_IFORM_SQRTPS_XMMps_XMMps_DEFINED   1

◆ XED_IFORM_SQRTSD_XMMsd_MEMsd_DEFINED

#define XED_IFORM_SQRTSD_XMMsd_MEMsd_DEFINED   1

◆ XED_IFORM_SQRTSD_XMMsd_XMMsd_DEFINED

#define XED_IFORM_SQRTSD_XMMsd_XMMsd_DEFINED   1

◆ XED_IFORM_SQRTSS_XMMss_MEMss_DEFINED

#define XED_IFORM_SQRTSS_XMMss_MEMss_DEFINED   1

◆ XED_IFORM_SQRTSS_XMMss_XMMss_DEFINED

#define XED_IFORM_SQRTSS_XMMss_XMMss_DEFINED   1

◆ XED_IFORM_STAC_DEFINED

#define XED_IFORM_STAC_DEFINED   1

◆ XED_IFORM_STC_DEFINED

#define XED_IFORM_STC_DEFINED   1

◆ XED_IFORM_STD_DEFINED

#define XED_IFORM_STD_DEFINED   1

◆ XED_IFORM_STGI_DEFINED

#define XED_IFORM_STGI_DEFINED   1

◆ XED_IFORM_STI_DEFINED

#define XED_IFORM_STI_DEFINED   1

◆ XED_IFORM_STMXCSR_MEMd_DEFINED

#define XED_IFORM_STMXCSR_MEMd_DEFINED   1

◆ XED_IFORM_STOSB_DEFINED

#define XED_IFORM_STOSB_DEFINED   1

◆ XED_IFORM_STOSD_DEFINED

#define XED_IFORM_STOSD_DEFINED   1

◆ XED_IFORM_STOSQ_DEFINED

#define XED_IFORM_STOSQ_DEFINED   1

◆ XED_IFORM_STOSW_DEFINED

#define XED_IFORM_STOSW_DEFINED   1

◆ XED_IFORM_STR_GPRv_DEFINED

#define XED_IFORM_STR_GPRv_DEFINED   1

◆ XED_IFORM_STR_MEMw_DEFINED

#define XED_IFORM_STR_MEMw_DEFINED   1

◆ XED_IFORM_STTILECFG_MEM_APX_DEFINED

#define XED_IFORM_STTILECFG_MEM_APX_DEFINED   1

◆ XED_IFORM_STTILECFG_MEM_DEFINED

#define XED_IFORM_STTILECFG_MEM_DEFINED   1

◆ XED_IFORM_STUI_DEFINED

#define XED_IFORM_STUI_DEFINED   1

◆ XED_IFORM_SUB_AL_IMMb_DEFINED

#define XED_IFORM_SUB_AL_IMMb_DEFINED   1

◆ XED_IFORM_SUB_GPR8_GPR8_28_DEFINED

#define XED_IFORM_SUB_GPR8_GPR8_28_DEFINED   1

◆ XED_IFORM_SUB_GPR8_GPR8_2A_DEFINED

#define XED_IFORM_SUB_GPR8_GPR8_2A_DEFINED   1

◆ XED_IFORM_SUB_GPR8_IMMb_80r5_DEFINED

#define XED_IFORM_SUB_GPR8_IMMb_80r5_DEFINED   1

◆ XED_IFORM_SUB_GPR8_IMMb_82r5_DEFINED

#define XED_IFORM_SUB_GPR8_IMMb_82r5_DEFINED   1

◆ XED_IFORM_SUB_GPR8_MEMb_DEFINED

#define XED_IFORM_SUB_GPR8_MEMb_DEFINED   1

◆ XED_IFORM_SUB_GPR8i8_GPR8i8_APX_DEFINED

#define XED_IFORM_SUB_GPR8i8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_SUB_GPR8i8_GPR8i8_GPR8i8_APX_DEFINED

#define XED_IFORM_SUB_GPR8i8_GPR8i8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_SUB_GPR8i8_GPR8i8_IMM8_APX_DEFINED

#define XED_IFORM_SUB_GPR8i8_GPR8i8_IMM8_APX_DEFINED   1

◆ XED_IFORM_SUB_GPR8i8_GPR8i8_MEMi8_APX_DEFINED

#define XED_IFORM_SUB_GPR8i8_GPR8i8_MEMi8_APX_DEFINED   1

◆ XED_IFORM_SUB_GPR8i8_IMM8_APX_DEFINED

#define XED_IFORM_SUB_GPR8i8_IMM8_APX_DEFINED   1

◆ XED_IFORM_SUB_GPR8i8_MEMi8_APX_DEFINED

#define XED_IFORM_SUB_GPR8i8_MEMi8_APX_DEFINED   1

◆ XED_IFORM_SUB_GPR8i8_MEMi8_GPR8i8_APX_DEFINED

#define XED_IFORM_SUB_GPR8i8_MEMi8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_SUB_GPR8i8_MEMi8_IMM8_APX_DEFINED

#define XED_IFORM_SUB_GPR8i8_MEMi8_IMM8_APX_DEFINED   1

◆ XED_IFORM_SUB_GPRv_GPRv_29_DEFINED

#define XED_IFORM_SUB_GPRv_GPRv_29_DEFINED   1

◆ XED_IFORM_SUB_GPRv_GPRv_2B_DEFINED

#define XED_IFORM_SUB_GPRv_GPRv_2B_DEFINED   1

◆ XED_IFORM_SUB_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_SUB_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_SUB_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_SUB_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_SUB_GPRv_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_SUB_GPRv_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_SUB_GPRv_GPRv_IMMz_APX_DEFINED

#define XED_IFORM_SUB_GPRv_GPRv_IMMz_APX_DEFINED   1

◆ XED_IFORM_SUB_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_SUB_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_SUB_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_SUB_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_SUB_GPRv_IMMb_DEFINED

#define XED_IFORM_SUB_GPRv_IMMb_DEFINED   1

◆ XED_IFORM_SUB_GPRv_IMMz_APX_DEFINED

#define XED_IFORM_SUB_GPRv_IMMz_APX_DEFINED   1

◆ XED_IFORM_SUB_GPRv_IMMz_DEFINED

#define XED_IFORM_SUB_GPRv_IMMz_DEFINED   1

◆ XED_IFORM_SUB_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_SUB_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_SUB_GPRv_MEMv_DEFINED

#define XED_IFORM_SUB_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_SUB_GPRv_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_SUB_GPRv_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_SUB_GPRv_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_SUB_GPRv_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_SUB_GPRv_MEMv_IMMz_APX_DEFINED

#define XED_IFORM_SUB_GPRv_MEMv_IMMz_APX_DEFINED   1

◆ XED_IFORM_SUB_LOCK_MEMb_GPR8_DEFINED

#define XED_IFORM_SUB_LOCK_MEMb_GPR8_DEFINED   1

◆ XED_IFORM_SUB_LOCK_MEMb_IMMb_80r5_DEFINED

#define XED_IFORM_SUB_LOCK_MEMb_IMMb_80r5_DEFINED   1

◆ XED_IFORM_SUB_LOCK_MEMb_IMMb_82r5_DEFINED

#define XED_IFORM_SUB_LOCK_MEMb_IMMb_82r5_DEFINED   1

◆ XED_IFORM_SUB_LOCK_MEMv_GPRv_DEFINED

#define XED_IFORM_SUB_LOCK_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_SUB_LOCK_MEMv_IMMb_DEFINED

#define XED_IFORM_SUB_LOCK_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_SUB_LOCK_MEMv_IMMz_DEFINED

#define XED_IFORM_SUB_LOCK_MEMv_IMMz_DEFINED   1

◆ XED_IFORM_SUB_MEMb_GPR8_DEFINED

#define XED_IFORM_SUB_MEMb_GPR8_DEFINED   1

◆ XED_IFORM_SUB_MEMb_IMMb_80r5_DEFINED

#define XED_IFORM_SUB_MEMb_IMMb_80r5_DEFINED   1

◆ XED_IFORM_SUB_MEMb_IMMb_82r5_DEFINED

#define XED_IFORM_SUB_MEMb_IMMb_82r5_DEFINED   1

◆ XED_IFORM_SUB_MEMi8_GPR8i8_APX_DEFINED

#define XED_IFORM_SUB_MEMi8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_SUB_MEMi8_IMM8_APX_DEFINED

#define XED_IFORM_SUB_MEMi8_IMM8_APX_DEFINED   1

◆ XED_IFORM_SUB_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_SUB_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_SUB_MEMv_GPRv_DEFINED

#define XED_IFORM_SUB_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_SUB_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_SUB_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_SUB_MEMv_IMMb_DEFINED

#define XED_IFORM_SUB_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_SUB_MEMv_IMMz_APX_DEFINED

#define XED_IFORM_SUB_MEMv_IMMz_APX_DEFINED   1

◆ XED_IFORM_SUB_MEMv_IMMz_DEFINED

#define XED_IFORM_SUB_MEMv_IMMz_DEFINED   1

◆ XED_IFORM_SUB_OrAX_IMMz_DEFINED

#define XED_IFORM_SUB_OrAX_IMMz_DEFINED   1

◆ XED_IFORM_SUBPD_XMMpd_MEMpd_DEFINED

#define XED_IFORM_SUBPD_XMMpd_MEMpd_DEFINED   1

◆ XED_IFORM_SUBPD_XMMpd_XMMpd_DEFINED

#define XED_IFORM_SUBPD_XMMpd_XMMpd_DEFINED   1

◆ XED_IFORM_SUBPS_XMMps_MEMps_DEFINED

#define XED_IFORM_SUBPS_XMMps_MEMps_DEFINED   1

◆ XED_IFORM_SUBPS_XMMps_XMMps_DEFINED

#define XED_IFORM_SUBPS_XMMps_XMMps_DEFINED   1

◆ XED_IFORM_SUBSD_XMMsd_MEMsd_DEFINED

#define XED_IFORM_SUBSD_XMMsd_MEMsd_DEFINED   1

◆ XED_IFORM_SUBSD_XMMsd_XMMsd_DEFINED

#define XED_IFORM_SUBSD_XMMsd_XMMsd_DEFINED   1

◆ XED_IFORM_SUBSS_XMMss_MEMss_DEFINED

#define XED_IFORM_SUBSS_XMMss_MEMss_DEFINED   1

◆ XED_IFORM_SUBSS_XMMss_XMMss_DEFINED

#define XED_IFORM_SUBSS_XMMss_XMMss_DEFINED   1

◆ XED_IFORM_SWAPGS_DEFINED

#define XED_IFORM_SWAPGS_DEFINED   1

◆ XED_IFORM_SYSCALL_AMD_DEFINED

#define XED_IFORM_SYSCALL_AMD_DEFINED   1

◆ XED_IFORM_SYSCALL_DEFINED

#define XED_IFORM_SYSCALL_DEFINED   1

◆ XED_IFORM_SYSENTER_DEFINED

#define XED_IFORM_SYSENTER_DEFINED   1

◆ XED_IFORM_SYSEXIT_DEFINED

#define XED_IFORM_SYSEXIT_DEFINED   1

◆ XED_IFORM_SYSRET64_DEFINED

#define XED_IFORM_SYSRET64_DEFINED   1

◆ XED_IFORM_SYSRET_AMD_DEFINED

#define XED_IFORM_SYSRET_AMD_DEFINED   1

◆ XED_IFORM_SYSRET_DEFINED

#define XED_IFORM_SYSRET_DEFINED   1

◆ XED_IFORM_T1MSKC_GPR32d_GPR32d_DEFINED

#define XED_IFORM_T1MSKC_GPR32d_GPR32d_DEFINED   1

◆ XED_IFORM_T1MSKC_GPR32d_MEMd_DEFINED

#define XED_IFORM_T1MSKC_GPR32d_MEMd_DEFINED   1

◆ XED_IFORM_T1MSKC_GPRyy_GPRyy_DEFINED

#define XED_IFORM_T1MSKC_GPRyy_GPRyy_DEFINED   1

◆ XED_IFORM_T1MSKC_GPRyy_MEMy_DEFINED

#define XED_IFORM_T1MSKC_GPRyy_MEMy_DEFINED   1

◆ XED_IFORM_T2RPNTLVWZ0_TMM2u16_MEMu16_APX_DEFINED

#define XED_IFORM_T2RPNTLVWZ0_TMM2u16_MEMu16_APX_DEFINED   1

◆ XED_IFORM_T2RPNTLVWZ0_TMM2u16_MEMu16_DEFINED

#define XED_IFORM_T2RPNTLVWZ0_TMM2u16_MEMu16_DEFINED   1

◆ XED_IFORM_T2RPNTLVWZ0RS_TMM2u16_MEMu16_APX_DEFINED

#define XED_IFORM_T2RPNTLVWZ0RS_TMM2u16_MEMu16_APX_DEFINED   1

◆ XED_IFORM_T2RPNTLVWZ0RS_TMM2u16_MEMu16_DEFINED

#define XED_IFORM_T2RPNTLVWZ0RS_TMM2u16_MEMu16_DEFINED   1

◆ XED_IFORM_T2RPNTLVWZ0RST1_TMM2u16_MEMu16_APX_DEFINED

#define XED_IFORM_T2RPNTLVWZ0RST1_TMM2u16_MEMu16_APX_DEFINED   1

◆ XED_IFORM_T2RPNTLVWZ0RST1_TMM2u16_MEMu16_DEFINED

#define XED_IFORM_T2RPNTLVWZ0RST1_TMM2u16_MEMu16_DEFINED   1

◆ XED_IFORM_T2RPNTLVWZ0T1_TMM2u16_MEMu16_APX_DEFINED

#define XED_IFORM_T2RPNTLVWZ0T1_TMM2u16_MEMu16_APX_DEFINED   1

◆ XED_IFORM_T2RPNTLVWZ0T1_TMM2u16_MEMu16_DEFINED

#define XED_IFORM_T2RPNTLVWZ0T1_TMM2u16_MEMu16_DEFINED   1

◆ XED_IFORM_T2RPNTLVWZ1_TMM2u16_MEMu16_APX_DEFINED

#define XED_IFORM_T2RPNTLVWZ1_TMM2u16_MEMu16_APX_DEFINED   1

◆ XED_IFORM_T2RPNTLVWZ1_TMM2u16_MEMu16_DEFINED

#define XED_IFORM_T2RPNTLVWZ1_TMM2u16_MEMu16_DEFINED   1

◆ XED_IFORM_T2RPNTLVWZ1RS_TMM2u16_MEMu16_APX_DEFINED

#define XED_IFORM_T2RPNTLVWZ1RS_TMM2u16_MEMu16_APX_DEFINED   1

◆ XED_IFORM_T2RPNTLVWZ1RS_TMM2u16_MEMu16_DEFINED

#define XED_IFORM_T2RPNTLVWZ1RS_TMM2u16_MEMu16_DEFINED   1

◆ XED_IFORM_T2RPNTLVWZ1RST1_TMM2u16_MEMu16_APX_DEFINED

#define XED_IFORM_T2RPNTLVWZ1RST1_TMM2u16_MEMu16_APX_DEFINED   1

◆ XED_IFORM_T2RPNTLVWZ1RST1_TMM2u16_MEMu16_DEFINED

#define XED_IFORM_T2RPNTLVWZ1RST1_TMM2u16_MEMu16_DEFINED   1

◆ XED_IFORM_T2RPNTLVWZ1T1_TMM2u16_MEMu16_APX_DEFINED

#define XED_IFORM_T2RPNTLVWZ1T1_TMM2u16_MEMu16_APX_DEFINED   1

◆ XED_IFORM_T2RPNTLVWZ1T1_TMM2u16_MEMu16_DEFINED

#define XED_IFORM_T2RPNTLVWZ1T1_TMM2u16_MEMu16_DEFINED   1

◆ XED_IFORM_TCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED

#define XED_IFORM_TCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED   1

◆ XED_IFORM_TCMMRLFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED

#define XED_IFORM_TCMMRLFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED   1

◆ XED_IFORM_TCONJTCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED

#define XED_IFORM_TCONJTCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED   1

◆ XED_IFORM_TCONJTFP16_TMM2f16_TMM2f16_DEFINED

#define XED_IFORM_TCONJTFP16_TMM2f16_TMM2f16_DEFINED   1

◆ XED_IFORM_TCVTROWD2PS_ZMMf32_TMMu32_GPR32u32_DEFINED

#define XED_IFORM_TCVTROWD2PS_ZMMf32_TMMu32_GPR32u32_DEFINED   1

◆ XED_IFORM_TCVTROWD2PS_ZMMf32_TMMu32_IMM8_DEFINED

#define XED_IFORM_TCVTROWD2PS_ZMMf32_TMMu32_IMM8_DEFINED   1

◆ XED_IFORM_TCVTROWPS2BF16H_ZMMbf16_TMMf32_GPR32u32_DEFINED

#define XED_IFORM_TCVTROWPS2BF16H_ZMMbf16_TMMf32_GPR32u32_DEFINED   1

◆ XED_IFORM_TCVTROWPS2BF16H_ZMMbf16_TMMf32_IMM8_DEFINED

#define XED_IFORM_TCVTROWPS2BF16H_ZMMbf16_TMMf32_IMM8_DEFINED   1

◆ XED_IFORM_TCVTROWPS2BF16L_ZMMbf16_TMMf32_GPR32u32_DEFINED

#define XED_IFORM_TCVTROWPS2BF16L_ZMMbf16_TMMf32_GPR32u32_DEFINED   1

◆ XED_IFORM_TCVTROWPS2BF16L_ZMMbf16_TMMf32_IMM8_DEFINED

#define XED_IFORM_TCVTROWPS2BF16L_ZMMbf16_TMMf32_IMM8_DEFINED   1

◆ XED_IFORM_TCVTROWPS2PHH_ZMMf16_TMMf32_GPR32u32_DEFINED

#define XED_IFORM_TCVTROWPS2PHH_ZMMf16_TMMf32_GPR32u32_DEFINED   1

◆ XED_IFORM_TCVTROWPS2PHH_ZMMf16_TMMf32_IMM8_DEFINED

#define XED_IFORM_TCVTROWPS2PHH_ZMMf16_TMMf32_IMM8_DEFINED   1

◆ XED_IFORM_TCVTROWPS2PHL_ZMMf16_TMMf32_GPR32u32_DEFINED

#define XED_IFORM_TCVTROWPS2PHL_ZMMf16_TMMf32_GPR32u32_DEFINED   1

◆ XED_IFORM_TCVTROWPS2PHL_ZMMf16_TMMf32_IMM8_DEFINED

#define XED_IFORM_TCVTROWPS2PHL_ZMMf16_TMMf32_IMM8_DEFINED   1

◆ XED_IFORM_TDCALL_DEFINED

#define XED_IFORM_TDCALL_DEFINED   1

◆ XED_IFORM_TDPBF16PS_TMMf32_TMM2bf16_TMM2bf16_DEFINED

#define XED_IFORM_TDPBF16PS_TMMf32_TMM2bf16_TMM2bf16_DEFINED   1

◆ XED_IFORM_TDPBF8PS_TMMf32_TMM4bf8_TMM4bf8_DEFINED

#define XED_IFORM_TDPBF8PS_TMMf32_TMM4bf8_TMM4bf8_DEFINED   1

◆ XED_IFORM_TDPBHF8PS_TMMf32_TMM4bf8_TMM4hf8_DEFINED

#define XED_IFORM_TDPBHF8PS_TMMf32_TMM4bf8_TMM4hf8_DEFINED   1

◆ XED_IFORM_TDPBSSD_TMMi32_TMM4i8_TMM4i8_DEFINED

#define XED_IFORM_TDPBSSD_TMMi32_TMM4i8_TMM4i8_DEFINED   1

◆ XED_IFORM_TDPBSUD_TMMi32_TMM4i8_TMM4u8_DEFINED

#define XED_IFORM_TDPBSUD_TMMi32_TMM4i8_TMM4u8_DEFINED   1

◆ XED_IFORM_TDPBUSD_TMMi32_TMM4u8_TMM4i8_DEFINED

#define XED_IFORM_TDPBUSD_TMMi32_TMM4u8_TMM4i8_DEFINED   1

◆ XED_IFORM_TDPBUUD_TMMu32_TMM4u8_TMM4u8_DEFINED

#define XED_IFORM_TDPBUUD_TMMu32_TMM4u8_TMM4u8_DEFINED   1

◆ XED_IFORM_TDPFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED

#define XED_IFORM_TDPFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED   1

◆ XED_IFORM_TDPHBF8PS_TMMf32_TMM4hf8_TMM4bf8_DEFINED

#define XED_IFORM_TDPHBF8PS_TMMf32_TMM4hf8_TMM4bf8_DEFINED   1

◆ XED_IFORM_TDPHF8PS_TMMf32_TMM4hf8_TMM4hf8_DEFINED

#define XED_IFORM_TDPHF8PS_TMMf32_TMM4hf8_TMM4hf8_DEFINED   1

◆ XED_IFORM_TEST_AL_IMMb_DEFINED

#define XED_IFORM_TEST_AL_IMMb_DEFINED   1

◆ XED_IFORM_TEST_GPR8_GPR8_DEFINED

#define XED_IFORM_TEST_GPR8_GPR8_DEFINED   1

◆ XED_IFORM_TEST_GPR8_IMMb_F6r0_DEFINED

#define XED_IFORM_TEST_GPR8_IMMb_F6r0_DEFINED   1

◆ XED_IFORM_TEST_GPR8_IMMb_F6r1_DEFINED

#define XED_IFORM_TEST_GPR8_IMMb_F6r1_DEFINED   1

◆ XED_IFORM_TEST_GPRv_GPRv_DEFINED

#define XED_IFORM_TEST_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_TEST_GPRv_IMMz_F7r0_DEFINED

#define XED_IFORM_TEST_GPRv_IMMz_F7r0_DEFINED   1

◆ XED_IFORM_TEST_GPRv_IMMz_F7r1_DEFINED

#define XED_IFORM_TEST_GPRv_IMMz_F7r1_DEFINED   1

◆ XED_IFORM_TEST_MEMb_GPR8_DEFINED

#define XED_IFORM_TEST_MEMb_GPR8_DEFINED   1

◆ XED_IFORM_TEST_MEMb_IMMb_F6r0_DEFINED

#define XED_IFORM_TEST_MEMb_IMMb_F6r0_DEFINED   1

◆ XED_IFORM_TEST_MEMb_IMMb_F6r1_DEFINED

#define XED_IFORM_TEST_MEMb_IMMb_F6r1_DEFINED   1

◆ XED_IFORM_TEST_MEMv_GPRv_DEFINED

#define XED_IFORM_TEST_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_TEST_MEMv_IMMz_F7r0_DEFINED

#define XED_IFORM_TEST_MEMv_IMMz_F7r0_DEFINED   1

◆ XED_IFORM_TEST_MEMv_IMMz_F7r1_DEFINED

#define XED_IFORM_TEST_MEMv_IMMz_F7r1_DEFINED   1

◆ XED_IFORM_TEST_OrAX_IMMz_DEFINED

#define XED_IFORM_TEST_OrAX_IMMz_DEFINED   1

◆ XED_IFORM_TESTUI_DEFINED

#define XED_IFORM_TESTUI_DEFINED   1

◆ XED_IFORM_TILELOADD_TMMu32_MEMu32_APX_DEFINED

#define XED_IFORM_TILELOADD_TMMu32_MEMu32_APX_DEFINED   1

◆ XED_IFORM_TILELOADD_TMMu32_MEMu32_DEFINED

#define XED_IFORM_TILELOADD_TMMu32_MEMu32_DEFINED   1

◆ XED_IFORM_TILELOADDRS_TMMu32_MEMu32_APX_DEFINED

#define XED_IFORM_TILELOADDRS_TMMu32_MEMu32_APX_DEFINED   1

◆ XED_IFORM_TILELOADDRS_TMMu32_MEMu32_DEFINED

#define XED_IFORM_TILELOADDRS_TMMu32_MEMu32_DEFINED   1

◆ XED_IFORM_TILELOADDRST1_TMMu32_MEMu32_APX_DEFINED

#define XED_IFORM_TILELOADDRST1_TMMu32_MEMu32_APX_DEFINED   1

◆ XED_IFORM_TILELOADDRST1_TMMu32_MEMu32_DEFINED

#define XED_IFORM_TILELOADDRST1_TMMu32_MEMu32_DEFINED   1

◆ XED_IFORM_TILELOADDT1_TMMu32_MEMu32_APX_DEFINED

#define XED_IFORM_TILELOADDT1_TMMu32_MEMu32_APX_DEFINED   1

◆ XED_IFORM_TILELOADDT1_TMMu32_MEMu32_DEFINED

#define XED_IFORM_TILELOADDT1_TMMu32_MEMu32_DEFINED   1

◆ XED_IFORM_TILEMOVROW_ZMMu8_TMMu8_GPR32u32_DEFINED

#define XED_IFORM_TILEMOVROW_ZMMu8_TMMu8_GPR32u32_DEFINED   1

◆ XED_IFORM_TILEMOVROW_ZMMu8_TMMu8_IMM8_DEFINED

#define XED_IFORM_TILEMOVROW_ZMMu8_TMMu8_IMM8_DEFINED   1

◆ XED_IFORM_TILERELEASE_DEFINED

#define XED_IFORM_TILERELEASE_DEFINED   1

◆ XED_IFORM_TILESTORED_MEMu32_TMMu32_APX_DEFINED

#define XED_IFORM_TILESTORED_MEMu32_TMMu32_APX_DEFINED   1

◆ XED_IFORM_TILESTORED_MEMu32_TMMu32_DEFINED

#define XED_IFORM_TILESTORED_MEMu32_TMMu32_DEFINED   1

◆ XED_IFORM_TILEZERO_TMMu32_DEFINED

#define XED_IFORM_TILEZERO_TMMu32_DEFINED   1

◆ XED_IFORM_TLBSYNC_DEFINED

#define XED_IFORM_TLBSYNC_DEFINED   1

◆ XED_IFORM_TMMULTF32PS_TMMf32_TMMf32_TMMf32_DEFINED

#define XED_IFORM_TMMULTF32PS_TMMf32_TMMf32_TMMf32_DEFINED   1

◆ XED_IFORM_TPAUSE_GPR32u32_DEFINED

#define XED_IFORM_TPAUSE_GPR32u32_DEFINED   1

◆ XED_IFORM_TTCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED

#define XED_IFORM_TTCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED   1

◆ XED_IFORM_TTCMMRLFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED

#define XED_IFORM_TTCMMRLFP16PS_TMMf32_TMM2f16_TMM2f16_DEFINED   1

◆ XED_IFORM_TTDPBF16PS_TMMf32_TMMbf16_TMMbf16_DEFINED

#define XED_IFORM_TTDPBF16PS_TMMf32_TMMbf16_TMMbf16_DEFINED   1

◆ XED_IFORM_TTDPFP16PS_TMMf32_TMMf16_TMMf16_DEFINED

#define XED_IFORM_TTDPFP16PS_TMMf32_TMMf16_TMMf16_DEFINED   1

◆ XED_IFORM_TTMMULTF32PS_TMMf32_TMMf32_TMMf32_DEFINED

#define XED_IFORM_TTMMULTF32PS_TMMf32_TMMf32_TMMf32_DEFINED   1

◆ XED_IFORM_TTRANSPOSED_TMMu32_TMMu32_DEFINED

#define XED_IFORM_TTRANSPOSED_TMMu32_TMMu32_DEFINED   1

◆ XED_IFORM_TZCNT_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_TZCNT_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_TZCNT_GPRv_GPRv_DEFINED

#define XED_IFORM_TZCNT_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_TZCNT_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_TZCNT_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_TZCNT_GPRv_MEMv_DEFINED

#define XED_IFORM_TZCNT_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_TZMSK_GPR32d_GPR32d_DEFINED

#define XED_IFORM_TZMSK_GPR32d_GPR32d_DEFINED   1

◆ XED_IFORM_TZMSK_GPR32d_MEMd_DEFINED

#define XED_IFORM_TZMSK_GPR32d_MEMd_DEFINED   1

◆ XED_IFORM_TZMSK_GPRyy_GPRyy_DEFINED

#define XED_IFORM_TZMSK_GPRyy_GPRyy_DEFINED   1

◆ XED_IFORM_TZMSK_GPRyy_MEMy_DEFINED

#define XED_IFORM_TZMSK_GPRyy_MEMy_DEFINED   1

◆ XED_IFORM_UCOMISD_XMMsd_MEMsd_DEFINED

#define XED_IFORM_UCOMISD_XMMsd_MEMsd_DEFINED   1

◆ XED_IFORM_UCOMISD_XMMsd_XMMsd_DEFINED

#define XED_IFORM_UCOMISD_XMMsd_XMMsd_DEFINED   1

◆ XED_IFORM_UCOMISS_XMMss_MEMss_DEFINED

#define XED_IFORM_UCOMISS_XMMss_MEMss_DEFINED   1

◆ XED_IFORM_UCOMISS_XMMss_XMMss_DEFINED

#define XED_IFORM_UCOMISS_XMMss_XMMss_DEFINED   1

◆ XED_IFORM_UD0_DEFINED

#define XED_IFORM_UD0_DEFINED   1

◆ XED_IFORM_UD0_GPR32_GPR32_DEFINED

#define XED_IFORM_UD0_GPR32_GPR32_DEFINED   1

◆ XED_IFORM_UD0_GPR32_MEMd_DEFINED

#define XED_IFORM_UD0_GPR32_MEMd_DEFINED   1

◆ XED_IFORM_UD1_GPR32_GPR32_DEFINED

#define XED_IFORM_UD1_GPR32_GPR32_DEFINED   1

◆ XED_IFORM_UD1_GPR32_MEMd_DEFINED

#define XED_IFORM_UD1_GPR32_MEMd_DEFINED   1

◆ XED_IFORM_UD2_DEFINED

#define XED_IFORM_UD2_DEFINED   1

◆ XED_IFORM_UIRET_DEFINED

#define XED_IFORM_UIRET_DEFINED   1

◆ XED_IFORM_UMONITOR_GPRa_DEFINED

#define XED_IFORM_UMONITOR_GPRa_DEFINED   1

◆ XED_IFORM_UMWAIT_GPR32_DEFINED

#define XED_IFORM_UMWAIT_GPR32_DEFINED   1

◆ XED_IFORM_UNPCKHPD_XMMpd_MEMdq_DEFINED

#define XED_IFORM_UNPCKHPD_XMMpd_MEMdq_DEFINED   1

◆ XED_IFORM_UNPCKHPD_XMMpd_XMMq_DEFINED

#define XED_IFORM_UNPCKHPD_XMMpd_XMMq_DEFINED   1

◆ XED_IFORM_UNPCKHPS_XMMps_MEMdq_DEFINED

#define XED_IFORM_UNPCKHPS_XMMps_MEMdq_DEFINED   1

◆ XED_IFORM_UNPCKHPS_XMMps_XMMdq_DEFINED

#define XED_IFORM_UNPCKHPS_XMMps_XMMdq_DEFINED   1

◆ XED_IFORM_UNPCKLPD_XMMpd_MEMdq_DEFINED

#define XED_IFORM_UNPCKLPD_XMMpd_MEMdq_DEFINED   1

◆ XED_IFORM_UNPCKLPD_XMMpd_XMMq_DEFINED

#define XED_IFORM_UNPCKLPD_XMMpd_XMMq_DEFINED   1

◆ XED_IFORM_UNPCKLPS_XMMps_MEMdq_DEFINED

#define XED_IFORM_UNPCKLPS_XMMps_MEMdq_DEFINED   1

◆ XED_IFORM_UNPCKLPS_XMMps_XMMq_DEFINED

#define XED_IFORM_UNPCKLPS_XMMps_XMMq_DEFINED   1

◆ XED_IFORM_URDMSR_GPR64u64_GPR64u64_APX_DEFINED

#define XED_IFORM_URDMSR_GPR64u64_GPR64u64_APX_DEFINED   1

◆ XED_IFORM_URDMSR_GPR64u64_GPR64u64_DEFINED

#define XED_IFORM_URDMSR_GPR64u64_GPR64u64_DEFINED   1

◆ XED_IFORM_URDMSR_GPR64u64_IMM32_APX_DEFINED

#define XED_IFORM_URDMSR_GPR64u64_IMM32_APX_DEFINED   1

◆ XED_IFORM_URDMSR_GPR64u64_IMM32_DEFINED

#define XED_IFORM_URDMSR_GPR64u64_IMM32_DEFINED   1

◆ XED_IFORM_UWRMSR_GPR64u64_GPR64u64_APX_DEFINED

#define XED_IFORM_UWRMSR_GPR64u64_GPR64u64_APX_DEFINED   1

◆ XED_IFORM_UWRMSR_GPR64u64_GPR64u64_DEFINED

#define XED_IFORM_UWRMSR_GPR64u64_GPR64u64_DEFINED   1

◆ XED_IFORM_UWRMSR_IMM32_GPR64u64_APX_DEFINED

#define XED_IFORM_UWRMSR_IMM32_GPR64u64_APX_DEFINED   1

◆ XED_IFORM_UWRMSR_IMM32_GPR64u64_DEFINED

#define XED_IFORM_UWRMSR_IMM32_GPR64u64_DEFINED   1

◆ XED_IFORM_V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VADDBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VADDBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VADDBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

#define XED_IFORM_VADDBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VADDBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VADDBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VADDBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

#define XED_IFORM_VADDBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VADDBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VADDBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VADDBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

#define XED_IFORM_VADDBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VADDPS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VADDPS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VADDPS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VADDPS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VADDSD_XMMdq_XMMdq_MEMq_DEFINED

#define XED_IFORM_VADDSD_XMMdq_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_VADDSD_XMMdq_XMMdq_XMMq_DEFINED

#define XED_IFORM_VADDSD_XMMdq_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd_DEFINED

#define XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd_DEFINED   1

◆ XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd_DEFINED

#define XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd_DEFINED   1

◆ XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VADDSUBPD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VADDSUBPD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VADDSUBPD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VADDSUBPD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VADDSUBPS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VADDSUBPS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VADDSUBPS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VADDSUBPS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VADDSUBPS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VADDSUBPS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VADDSUBPS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VADDSUBPS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VAESDEC_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VAESDEC_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VAESDEC_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VAESDEC_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VAESDEC_XMMu128_XMMu128_MEMu128_AVX512_DEFINED

#define XED_IFORM_VAESDEC_XMMu128_XMMu128_MEMu128_AVX512_DEFINED   1

◆ XED_IFORM_VAESDEC_XMMu128_XMMu128_XMMu128_AVX512_DEFINED

#define XED_IFORM_VAESDEC_XMMu128_XMMu128_XMMu128_AVX512_DEFINED   1

◆ XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_AVX512_DEFINED

#define XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_AVX512_DEFINED   1

◆ XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_DEFINED

#define XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_DEFINED   1

◆ XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_AVX512_DEFINED

#define XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_AVX512_DEFINED   1

◆ XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_DEFINED

#define XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_DEFINED   1

◆ XED_IFORM_VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED

#define XED_IFORM_VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED   1

◆ XED_IFORM_VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED

#define XED_IFORM_VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED   1

◆ XED_IFORM_VAESDECLAST_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VAESDECLAST_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VAESDECLAST_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VAESDECLAST_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512_DEFINED

#define XED_IFORM_VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512_DEFINED   1

◆ XED_IFORM_VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512_DEFINED

#define XED_IFORM_VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512_DEFINED   1

◆ XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512_DEFINED

#define XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512_DEFINED   1

◆ XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_DEFINED

#define XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_DEFINED   1

◆ XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512_DEFINED

#define XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512_DEFINED   1

◆ XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_DEFINED

#define XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_DEFINED   1

◆ XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED

#define XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED   1

◆ XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED

#define XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED   1

◆ XED_IFORM_VAESENC_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VAESENC_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VAESENC_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VAESENC_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VAESENC_XMMu128_XMMu128_MEMu128_AVX512_DEFINED

#define XED_IFORM_VAESENC_XMMu128_XMMu128_MEMu128_AVX512_DEFINED   1

◆ XED_IFORM_VAESENC_XMMu128_XMMu128_XMMu128_AVX512_DEFINED

#define XED_IFORM_VAESENC_XMMu128_XMMu128_XMMu128_AVX512_DEFINED   1

◆ XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_AVX512_DEFINED

#define XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_AVX512_DEFINED   1

◆ XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_DEFINED

#define XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_DEFINED   1

◆ XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_AVX512_DEFINED

#define XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_AVX512_DEFINED   1

◆ XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_DEFINED

#define XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_DEFINED   1

◆ XED_IFORM_VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED

#define XED_IFORM_VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED   1

◆ XED_IFORM_VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED

#define XED_IFORM_VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED   1

◆ XED_IFORM_VAESENCLAST_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VAESENCLAST_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VAESENCLAST_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VAESENCLAST_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512_DEFINED

#define XED_IFORM_VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512_DEFINED   1

◆ XED_IFORM_VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512_DEFINED

#define XED_IFORM_VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512_DEFINED   1

◆ XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512_DEFINED

#define XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512_DEFINED   1

◆ XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_DEFINED

#define XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_DEFINED   1

◆ XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512_DEFINED

#define XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512_DEFINED   1

◆ XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_DEFINED

#define XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_DEFINED   1

◆ XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED

#define XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED   1

◆ XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED

#define XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED   1

◆ XED_IFORM_VAESIMC_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VAESIMC_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VAESIMC_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VAESIMC_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VAESKEYGENASSIST_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VAESKEYGENASSIST_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VAESKEYGENASSIST_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VAESKEYGENASSIST_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VANDNPD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VANDNPD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VANDNPD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VANDNPD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VANDNPD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VANDNPD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VANDNPD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VANDNPD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VANDNPS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VANDNPS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VANDNPS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VANDNPS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VANDNPS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VANDNPS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VANDNPS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VANDNPS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VANDPD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VANDPD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VANDPD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VANDPD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VANDPD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VANDPD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VANDPD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VANDPD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VANDPS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VANDPS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VANDPS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VANDPS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VANDPS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VANDPS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VANDPS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VANDPS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VBCSTNEBF162PS_XMMf32_MEMbf16_DEFINED

#define XED_IFORM_VBCSTNEBF162PS_XMMf32_MEMbf16_DEFINED   1

◆ XED_IFORM_VBCSTNEBF162PS_YMMf32_MEMbf16_DEFINED

#define XED_IFORM_VBCSTNEBF162PS_YMMf32_MEMbf16_DEFINED   1

◆ XED_IFORM_VBCSTNESH2PS_XMMf32_MEMf16_DEFINED

#define XED_IFORM_VBCSTNESH2PS_XMMf32_MEMf16_DEFINED   1

◆ XED_IFORM_VBCSTNESH2PS_YMMf32_MEMf16_DEFINED

#define XED_IFORM_VBCSTNESH2PS_YMMf32_MEMf16_DEFINED   1

◆ XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED

#define XED_IFORM_VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1

◆ XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED

#define XED_IFORM_VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1

◆ XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED

#define XED_IFORM_VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED

#define XED_IFORM_VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VBROADCASTF128_YMMqq_MEMdq_DEFINED

#define XED_IFORM_VBROADCASTF128_YMMqq_MEMdq_DEFINED   1

◆ XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTI128_YMMqq_MEMdq_DEFINED

#define XED_IFORM_VBROADCASTI128_YMMqq_MEMdq_DEFINED   1

◆ XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512_DEFINED

#define XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTSD_YMMqq_MEMq_DEFINED

#define XED_IFORM_VBROADCASTSD_YMMqq_MEMq_DEFINED   1

◆ XED_IFORM_VBROADCASTSD_YMMqq_XMMdq_DEFINED

#define XED_IFORM_VBROADCASTSD_YMMqq_XMMdq_DEFINED   1

◆ XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512_DEFINED

#define XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTSS_XMMdq_MEMd_DEFINED

#define XED_IFORM_VBROADCASTSS_XMMdq_MEMd_DEFINED   1

◆ XED_IFORM_VBROADCASTSS_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VBROADCASTSS_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTSS_YMMqq_MEMd_DEFINED

#define XED_IFORM_VBROADCASTSS_YMMqq_MEMd_DEFINED   1

◆ XED_IFORM_VBROADCASTSS_YMMqq_XMMdq_DEFINED

#define XED_IFORM_VBROADCASTSS_YMMqq_XMMdq_DEFINED   1

◆ XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_XMMbf16_MEMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_XMMbf16_MEMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_XMMbf16_XMMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_XMMbf16_XMMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_YMMbf16_MEMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_YMMbf16_MEMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_YMMbf16_YMMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_YMMbf16_YMMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_ZMMbf16_MEMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_ZMMbf16_MEMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_ZMMbf16_ZMMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_ZMMbf16_ZMMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VCMPPD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED

#define XED_IFORM_VCMPPD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1

◆ XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VCMPPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED

#define XED_IFORM_VCMPPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1

◆ XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb_DEFINED

#define XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb_DEFINED   1

◆ XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb_DEFINED

#define XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb_DEFINED   1

◆ XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb_DEFINED

#define XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb_DEFINED   1

◆ XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb_DEFINED

#define XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb_DEFINED   1

◆ XED_IFORM_VCOMISBF16_XMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VCOMISBF16_XMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VCOMISBF16_XMMbf16_XMMbf16_AVX512_DEFINED

#define XED_IFORM_VCOMISBF16_XMMbf16_XMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VCOMISD_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCOMISD_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCOMISD_XMMq_MEMq_DEFINED

#define XED_IFORM_VCOMISD_XMMq_MEMq_DEFINED   1

◆ XED_IFORM_VCOMISD_XMMq_XMMq_DEFINED

#define XED_IFORM_VCOMISD_XMMq_XMMq_DEFINED   1

◆ XED_IFORM_VCOMISH_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCOMISH_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCOMISS_XMMd_MEMd_DEFINED

#define XED_IFORM_VCOMISS_XMMd_MEMd_DEFINED   1

◆ XED_IFORM_VCOMISS_XMMd_XMMd_DEFINED

#define XED_IFORM_VCOMISS_XMMd_XMMd_DEFINED   1

◆ XED_IFORM_VCOMISS_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCOMISS_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED

#define XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512_DEFINED

#define XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED

#define XED_IFORM_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED

#define XED_IFORM_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCOMXSD_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCOMXSD_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCOMXSD_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VCOMXSD_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCOMXSH_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCOMXSH_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCOMXSH_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCOMXSH_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCOMXSS_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCOMXSS_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCOMXSS_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCOMXSS_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PH2BF8_XMMbf8_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVT2PH2BF8_XMMbf8_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PH2BF8_XMMbf8_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVT2PH2BF8_XMMbf8_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PH2BF8_YMMbf8_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVT2PH2BF8_YMMbf8_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PH2BF8_YMMbf8_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VCVT2PH2BF8_YMMbf8_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PH2BF8_ZMMbf8_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVT2PH2BF8_ZMMbf8_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PH2BF8_ZMMbf8_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VCVT2PH2BF8_ZMMbf8_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PH2BF8S_XMMbf8_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVT2PH2BF8S_XMMbf8_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PH2BF8S_XMMbf8_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVT2PH2BF8S_XMMbf8_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PH2BF8S_YMMbf8_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVT2PH2BF8S_YMMbf8_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PH2BF8S_YMMbf8_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VCVT2PH2BF8S_YMMbf8_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PH2BF8S_ZMMbf8_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVT2PH2BF8S_ZMMbf8_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PH2BF8S_ZMMbf8_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VCVT2PH2BF8S_ZMMbf8_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PH2HF8_XMMhf8_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVT2PH2HF8_XMMhf8_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PH2HF8_XMMhf8_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVT2PH2HF8_XMMhf8_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PH2HF8_YMMhf8_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVT2PH2HF8_YMMhf8_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PH2HF8_YMMhf8_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VCVT2PH2HF8_YMMhf8_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PH2HF8_ZMMhf8_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVT2PH2HF8_ZMMhf8_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PH2HF8_ZMMhf8_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VCVT2PH2HF8_ZMMhf8_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PH2HF8S_XMMhf8_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVT2PH2HF8S_XMMhf8_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PH2HF8S_XMMhf8_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVT2PH2HF8S_XMMhf8_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PH2HF8S_YMMhf8_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVT2PH2HF8S_YMMhf8_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PH2HF8S_YMMhf8_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VCVT2PH2HF8S_YMMhf8_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PH2HF8S_ZMMhf8_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVT2PH2HF8S_ZMMhf8_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PH2HF8S_ZMMhf8_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VCVT2PH2HF8S_ZMMhf8_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PS2PHX_XMMf16_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVT2PS2PHX_XMMf16_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PS2PHX_XMMf16_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVT2PS2PHX_XMMf16_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PS2PHX_YMMf16_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVT2PS2PHX_YMMf16_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PS2PHX_YMMf16_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VCVT2PS2PHX_YMMf16_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PS2PHX_ZMMf16_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVT2PS2PHX_ZMMf16_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVT2PS2PHX_ZMMf16_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VCVT2PS2PHX_ZMMf16_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTBF162IBS_XMMi8_MASKmskw_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VCVTBF162IBS_XMMi8_MASKmskw_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTBF162IBS_XMMi8_MASKmskw_XMMbf16_AVX512_DEFINED

#define XED_IFORM_VCVTBF162IBS_XMMi8_MASKmskw_XMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTBF162IBS_YMMi8_MASKmskw_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VCVTBF162IBS_YMMi8_MASKmskw_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTBF162IBS_YMMi8_MASKmskw_YMMbf16_AVX512_DEFINED

#define XED_IFORM_VCVTBF162IBS_YMMi8_MASKmskw_YMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTBF162IBS_ZMMi8_MASKmskw_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VCVTBF162IBS_ZMMi8_MASKmskw_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTBF162IBS_ZMMi8_MASKmskw_ZMMbf16_AVX512_DEFINED

#define XED_IFORM_VCVTBF162IBS_ZMMi8_MASKmskw_ZMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTBF162IUBS_XMMu8_MASKmskw_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VCVTBF162IUBS_XMMu8_MASKmskw_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTBF162IUBS_XMMu8_MASKmskw_XMMbf16_AVX512_DEFINED

#define XED_IFORM_VCVTBF162IUBS_XMMu8_MASKmskw_XMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTBF162IUBS_YMMu8_MASKmskw_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VCVTBF162IUBS_YMMu8_MASKmskw_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTBF162IUBS_YMMu8_MASKmskw_YMMbf16_AVX512_DEFINED

#define XED_IFORM_VCVTBF162IUBS_YMMu8_MASKmskw_YMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTBF162IUBS_ZMMu8_MASKmskw_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VCVTBF162IUBS_ZMMu8_MASKmskw_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTBF162IUBS_ZMMu8_MASKmskw_ZMMbf16_AVX512_DEFINED

#define XED_IFORM_VCVTBF162IUBS_ZMMu8_MASKmskw_ZMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_XMM2i8_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_XMM2i8_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_YMM2i8_YMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_YMM2i8_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTBIASPH2BF8_YMMbf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTBIASPH2BF8_YMMbf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTBIASPH2BF8_YMMbf8_MASKmskw_ZMM2i8_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTBIASPH2BF8_YMMbf8_MASKmskw_ZMM2i8_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_XMM2i8_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_XMM2i8_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_YMM2i8_YMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_YMM2i8_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTBIASPH2BF8S_YMMbf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTBIASPH2BF8S_YMMbf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTBIASPH2BF8S_YMMbf8_MASKmskw_ZMM2i8_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTBIASPH2BF8S_YMMbf8_MASKmskw_ZMM2i8_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_XMM2i8_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_XMM2i8_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_YMM2i8_YMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_YMM2i8_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTBIASPH2HF8_YMMhf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTBIASPH2HF8_YMMhf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTBIASPH2HF8_YMMhf8_MASKmskw_ZMM2i8_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTBIASPH2HF8_YMMhf8_MASKmskw_ZMM2i8_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_XMM2i8_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_XMM2i8_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_YMM2i8_YMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_YMM2i8_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTBIASPH2HF8S_YMMhf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTBIASPH2HF8S_YMMhf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTBIASPH2HF8S_YMMhf8_MASKmskw_ZMM2i8_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTBIASPH2HF8S_YMMhf8_MASKmskw_ZMM2i8_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTDQ2PD_XMMdq_MEMq_DEFINED

#define XED_IFORM_VCVTDQ2PD_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_VCVTDQ2PD_XMMdq_XMMq_DEFINED

#define XED_IFORM_VCVTDQ2PD_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512_DEFINED

#define XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512_DEFINED

#define XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512_DEFINED

#define XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512_DEFINED

#define XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq_DEFINED

#define XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq_DEFINED   1

◆ XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq_DEFINED

#define XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq_DEFINED   1

◆ XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512_DEFINED

#define XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512_DEFINED

#define XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512_DEFINED

#define XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512_DEFINED

#define XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512_DEFINED

#define XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512_DEFINED

#define XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTDQ2PS_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VCVTDQ2PS_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VCVTDQ2PS_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VCVTDQ2PS_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512_DEFINED

#define XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512_DEFINED

#define XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512_DEFINED

#define XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512_DEFINED

#define XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512_DEFINED

#define XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512_DEFINED

#define XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTHF82PH_XMMf16_MASKmskw_MEMhf8_AVX512_DEFINED

#define XED_IFORM_VCVTHF82PH_XMMf16_MASKmskw_MEMhf8_AVX512_DEFINED   1

◆ XED_IFORM_VCVTHF82PH_XMMf16_MASKmskw_XMMhf8_AVX512_DEFINED

#define XED_IFORM_VCVTHF82PH_XMMf16_MASKmskw_XMMhf8_AVX512_DEFINED   1

◆ XED_IFORM_VCVTHF82PH_YMMf16_MASKmskw_MEMhf8_AVX512_DEFINED

#define XED_IFORM_VCVTHF82PH_YMMf16_MASKmskw_MEMhf8_AVX512_DEFINED   1

◆ XED_IFORM_VCVTHF82PH_YMMf16_MASKmskw_XMMhf8_AVX512_DEFINED

#define XED_IFORM_VCVTHF82PH_YMMf16_MASKmskw_XMMhf8_AVX512_DEFINED   1

◆ XED_IFORM_VCVTHF82PH_ZMMf16_MASKmskw_MEMhf8_AVX512_DEFINED

#define XED_IFORM_VCVTHF82PH_ZMMf16_MASKmskw_MEMhf8_AVX512_DEFINED   1

◆ XED_IFORM_VCVTHF82PH_ZMMf16_MASKmskw_YMMhf8_AVX512_DEFINED

#define XED_IFORM_VCVTHF82PH_ZMMf16_MASKmskw_YMMhf8_AVX512_DEFINED   1

◆ XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTNEEBF162PS_XMMf32_MEM2bf16_DEFINED

#define XED_IFORM_VCVTNEEBF162PS_XMMf32_MEM2bf16_DEFINED   1

◆ XED_IFORM_VCVTNEEBF162PS_YMMf32_MEM2bf16_DEFINED

#define XED_IFORM_VCVTNEEBF162PS_YMMf32_MEM2bf16_DEFINED   1

◆ XED_IFORM_VCVTNEEPH2PS_XMMf32_MEM2f16_DEFINED

#define XED_IFORM_VCVTNEEPH2PS_XMMf32_MEM2f16_DEFINED   1

◆ XED_IFORM_VCVTNEEPH2PS_YMMf32_MEM2f16_DEFINED

#define XED_IFORM_VCVTNEEPH2PS_YMMf32_MEM2f16_DEFINED   1

◆ XED_IFORM_VCVTNEOBF162PS_XMMf32_MEM2bf16_DEFINED

#define XED_IFORM_VCVTNEOBF162PS_XMMf32_MEM2bf16_DEFINED   1

◆ XED_IFORM_VCVTNEOBF162PS_YMMf32_MEM2bf16_DEFINED

#define XED_IFORM_VCVTNEOBF162PS_YMMf32_MEM2bf16_DEFINED   1

◆ XED_IFORM_VCVTNEOPH2PS_XMMf32_MEM2f16_DEFINED

#define XED_IFORM_VCVTNEOPH2PS_XMMf32_MEM2f16_DEFINED   1

◆ XED_IFORM_VCVTNEOPH2PS_YMMf32_MEM2f16_DEFINED

#define XED_IFORM_VCVTNEOPH2PS_YMMf32_MEM2f16_DEFINED   1

◆ XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTNEPS2BF16_XMMbf16_MEMf32_VL128_DEFINED

#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MEMf32_VL128_DEFINED   1

◆ XED_IFORM_VCVTNEPS2BF16_XMMbf16_MEMf32_VL256_DEFINED

#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MEMf32_VL256_DEFINED   1

◆ XED_IFORM_VCVTNEPS2BF16_XMMbf16_XMMf32_DEFINED

#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_XMMf32_DEFINED   1

◆ XED_IFORM_VCVTNEPS2BF16_XMMbf16_YMMf32_DEFINED

#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_YMMf32_DEFINED   1

◆ XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq_DEFINED

#define XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq_DEFINED   1

◆ XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq_DEFINED

#define XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq_DEFINED   1

◆ XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPD2PS_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VCVTPD2PS_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VCVTPD2PS_XMMdq_MEMqq_DEFINED

#define XED_IFORM_VCVTPD2PS_XMMdq_MEMqq_DEFINED   1

◆ XED_IFORM_VCVTPD2PS_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VCVTPD2PS_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VCVTPD2PS_XMMdq_YMMqq_DEFINED

#define XED_IFORM_VCVTPD2PS_XMMdq_YMMqq_DEFINED   1

◆ XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2BF8_XMMbf8_MASKmskw_MEMf16_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTPH2BF8_XMMbf8_MASKmskw_MEMf16_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTPH2BF8_XMMbf8_MASKmskw_MEMf16_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTPH2BF8_XMMbf8_MASKmskw_MEMf16_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTPH2BF8_XMMbf8_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2BF8_XMMbf8_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2BF8_XMMbf8_MASKmskw_YMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2BF8_XMMbf8_MASKmskw_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2BF8_YMMbf8_MASKmskw_MEMf16_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTPH2BF8_YMMbf8_MASKmskw_MEMf16_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTPH2BF8_YMMbf8_MASKmskw_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2BF8_YMMbf8_MASKmskw_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2BF8S_XMMbf8_MASKmskw_MEMf16_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTPH2BF8S_XMMbf8_MASKmskw_MEMf16_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTPH2BF8S_XMMbf8_MASKmskw_MEMf16_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTPH2BF8S_XMMbf8_MASKmskw_MEMf16_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTPH2BF8S_XMMbf8_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2BF8S_XMMbf8_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2BF8S_XMMbf8_MASKmskw_YMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2BF8S_XMMbf8_MASKmskw_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2BF8S_YMMbf8_MASKmskw_MEMf16_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTPH2BF8S_YMMbf8_MASKmskw_MEMf16_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTPH2BF8S_YMMbf8_MASKmskw_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2BF8S_YMMbf8_MASKmskw_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2HF8_XMMhf8_MASKmskw_MEMf16_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTPH2HF8_XMMhf8_MASKmskw_MEMf16_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTPH2HF8_XMMhf8_MASKmskw_MEMf16_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTPH2HF8_XMMhf8_MASKmskw_MEMf16_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTPH2HF8_XMMhf8_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2HF8_XMMhf8_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2HF8_XMMhf8_MASKmskw_YMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2HF8_XMMhf8_MASKmskw_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2HF8_YMMhf8_MASKmskw_MEMf16_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTPH2HF8_YMMhf8_MASKmskw_MEMf16_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTPH2HF8_YMMhf8_MASKmskw_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2HF8_YMMhf8_MASKmskw_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2HF8S_XMMhf8_MASKmskw_MEMf16_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTPH2HF8S_XMMhf8_MASKmskw_MEMf16_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTPH2HF8S_XMMhf8_MASKmskw_MEMf16_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTPH2HF8S_XMMhf8_MASKmskw_MEMf16_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTPH2HF8S_XMMhf8_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2HF8S_XMMhf8_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2HF8S_XMMhf8_MASKmskw_YMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2HF8S_XMMhf8_MASKmskw_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2HF8S_YMMhf8_MASKmskw_MEMf16_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTPH2HF8S_YMMhf8_MASKmskw_MEMf16_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTPH2HF8S_YMMhf8_MASKmskw_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2HF8S_YMMhf8_MASKmskw_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2IBS_XMMi8_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2IBS_XMMi8_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2IBS_XMMi8_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2IBS_XMMi8_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2IBS_YMMi8_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2IBS_YMMi8_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2IBS_YMMi8_MASKmskw_YMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2IBS_YMMi8_MASKmskw_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2IBS_ZMMi8_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2IBS_ZMMi8_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2IBS_ZMMi8_MASKmskw_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2IBS_ZMMi8_MASKmskw_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2IUBS_XMMu8_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2IUBS_XMMu8_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2IUBS_XMMu8_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2IUBS_XMMu8_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2IUBS_YMMu8_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2IUBS_YMMu8_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2IUBS_YMMu8_MASKmskw_YMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2IUBS_YMMu8_MASKmskw_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2IUBS_ZMMu8_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2IUBS_ZMMu8_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2IUBS_ZMMu8_MASKmskw_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2IUBS_ZMMu8_MASKmskw_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2PS_XMMdq_MEMq_DEFINED

#define XED_IFORM_VCVTPH2PS_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_VCVTPH2PS_XMMdq_XMMq_DEFINED

#define XED_IFORM_VCVTPH2PS_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2PS_YMMqq_MEMdq_DEFINED

#define XED_IFORM_VCVTPH2PS_YMMqq_MEMdq_DEFINED   1

◆ XED_IFORM_VCVTPH2PS_YMMqq_XMMdq_DEFINED

#define XED_IFORM_VCVTPH2PS_YMMqq_XMMdq_DEFINED   1

◆ XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2IBS_XMMi8_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2IBS_XMMi8_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2IBS_XMMi8_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2IBS_XMMi8_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2IBS_YMMi8_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2IBS_YMMi8_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2IBS_YMMi8_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2IBS_YMMi8_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2IBS_ZMMi8_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2IBS_ZMMi8_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2IBS_ZMMi8_MASKmskw_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2IBS_ZMMi8_MASKmskw_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2IUBS_XMMu8_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2IUBS_XMMu8_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2IUBS_XMMu8_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2IUBS_XMMu8_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2IUBS_YMMu8_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2IUBS_YMMu8_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2IUBS_YMMu8_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2IUBS_YMMu8_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2IUBS_ZMMu8_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2IUBS_ZMMu8_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2IUBS_ZMMu8_MASKmskw_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2IUBS_ZMMu8_MASKmskw_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2PD_XMMdq_MEMq_DEFINED

#define XED_IFORM_VCVTPS2PD_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_VCVTPS2PD_XMMdq_XMMq_DEFINED

#define XED_IFORM_VCVTPS2PD_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2PD_YMMqq_MEMdq_DEFINED

#define XED_IFORM_VCVTPS2PD_YMMqq_MEMdq_DEFINED   1

◆ XED_IFORM_VCVTPS2PD_YMMqq_XMMdq_DEFINED

#define XED_IFORM_VCVTPS2PD_YMMqq_XMMdq_DEFINED   1

◆ XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTQQ2PD_XMMf64_MASKmskw_MEMi64_AVX512_DEFINED

#define XED_IFORM_VCVTQQ2PD_XMMf64_MASKmskw_MEMi64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTQQ2PD_XMMf64_MASKmskw_XMMi64_AVX512_DEFINED

#define XED_IFORM_VCVTQQ2PD_XMMf64_MASKmskw_XMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTQQ2PD_YMMf64_MASKmskw_MEMi64_AVX512_DEFINED

#define XED_IFORM_VCVTQQ2PD_YMMf64_MASKmskw_MEMi64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTQQ2PD_YMMf64_MASKmskw_YMMi64_AVX512_DEFINED

#define XED_IFORM_VCVTQQ2PD_YMMf64_MASKmskw_YMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTQQ2PD_ZMMf64_MASKmskw_MEMi64_AVX512_DEFINED

#define XED_IFORM_VCVTQQ2PD_ZMMf64_MASKmskw_MEMi64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTQQ2PD_ZMMf64_MASKmskw_ZMMi64_AVX512_DEFINED

#define XED_IFORM_VCVTQQ2PD_ZMMf64_MASKmskw_ZMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_DEFINED

#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSD2SI_GPR32d_MEMq_DEFINED

#define XED_IFORM_VCVTSD2SI_GPR32d_MEMq_DEFINED   1

◆ XED_IFORM_VCVTSD2SI_GPR32d_XMMq_DEFINED

#define XED_IFORM_VCVTSD2SI_GPR32d_XMMq_DEFINED   1

◆ XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSD2SI_GPR64q_MEMq_DEFINED

#define XED_IFORM_VCVTSD2SI_GPR64q_MEMq_DEFINED   1

◆ XED_IFORM_VCVTSD2SI_GPR64q_XMMq_DEFINED

#define XED_IFORM_VCVTSD2SI_GPR64q_XMMq_DEFINED   1

◆ XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq_DEFINED

#define XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq_DEFINED

#define XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSH2SI_GPR32i32_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTSH2SI_GPR32i32_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSH2SI_GPR64i64_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTSH2SI_GPR64i64_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSH2USI_GPR32u32_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTSH2USI_GPR32u32_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSH2USI_GPR64u64_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTSH2USI_GPR64u64_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d_DEFINED

#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d_DEFINED   1

◆ XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q_DEFINED

#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q_DEFINED   1

◆ XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd_DEFINED

#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd_DEFINED   1

◆ XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq_DEFINED

#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512_DEFINED

#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512_DEFINED

#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512_DEFINED

#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512_DEFINED

#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512_DEFINED

#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512_DEFINED

#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512_DEFINED

#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512_DEFINED

#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d_DEFINED

#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d_DEFINED   1

◆ XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q_DEFINED

#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q_DEFINED   1

◆ XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd_DEFINED

#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd_DEFINED   1

◆ XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq_DEFINED

#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512_DEFINED

#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512_DEFINED

#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512_DEFINED

#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512_DEFINED

#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd_DEFINED

#define XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd_DEFINED   1

◆ XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd_DEFINED

#define XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd_DEFINED   1

◆ XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSS2SI_GPR32d_MEMd_DEFINED

#define XED_IFORM_VCVTSS2SI_GPR32d_MEMd_DEFINED   1

◆ XED_IFORM_VCVTSS2SI_GPR32d_XMMd_DEFINED

#define XED_IFORM_VCVTSS2SI_GPR32d_XMMd_DEFINED   1

◆ XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSS2SI_GPR64q_MEMd_DEFINED

#define XED_IFORM_VCVTSS2SI_GPR64q_MEMd_DEFINED   1

◆ XED_IFORM_VCVTSS2SI_GPR64q_XMMd_DEFINED

#define XED_IFORM_VCVTSS2SI_GPR64q_XMMd_DEFINED   1

◆ XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTBF162IBS_XMMi8_MASKmskw_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VCVTTBF162IBS_XMMi8_MASKmskw_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTBF162IBS_XMMi8_MASKmskw_XMMbf16_AVX512_DEFINED

#define XED_IFORM_VCVTTBF162IBS_XMMi8_MASKmskw_XMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTBF162IBS_YMMi8_MASKmskw_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VCVTTBF162IBS_YMMi8_MASKmskw_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTBF162IBS_YMMi8_MASKmskw_YMMbf16_AVX512_DEFINED

#define XED_IFORM_VCVTTBF162IBS_YMMi8_MASKmskw_YMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTBF162IBS_ZMMi8_MASKmskw_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VCVTTBF162IBS_ZMMi8_MASKmskw_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTBF162IBS_ZMMi8_MASKmskw_ZMMbf16_AVX512_DEFINED

#define XED_IFORM_VCVTTBF162IBS_ZMMi8_MASKmskw_ZMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTBF162IUBS_XMMu8_MASKmskw_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VCVTTBF162IUBS_XMMu8_MASKmskw_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTBF162IUBS_XMMu8_MASKmskw_XMMbf16_AVX512_DEFINED

#define XED_IFORM_VCVTTBF162IUBS_XMMu8_MASKmskw_XMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTBF162IUBS_YMMu8_MASKmskw_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VCVTTBF162IUBS_YMMu8_MASKmskw_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTBF162IUBS_YMMu8_MASKmskw_YMMbf16_AVX512_DEFINED

#define XED_IFORM_VCVTTBF162IUBS_YMMu8_MASKmskw_YMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTBF162IUBS_ZMMu8_MASKmskw_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VCVTTBF162IUBS_ZMMu8_MASKmskw_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTBF162IUBS_ZMMu8_MASKmskw_ZMMbf16_AVX512_DEFINED

#define XED_IFORM_VCVTTBF162IUBS_ZMMu8_MASKmskw_ZMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq_DEFINED

#define XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq_DEFINED   1

◆ XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq_DEFINED

#define XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq_DEFINED   1

◆ XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_XMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_YMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2DQS_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTTPD2DQS_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTTPD2DQS_YMMi32_MASKmskw_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2DQS_YMMi32_MASKmskw_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2QQS_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2QQS_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2QQS_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2QQS_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2QQS_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2QQS_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2QQS_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2QQS_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2QQS_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2QQS_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2QQS_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2QQS_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_XMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_YMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2UDQS_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTTPD2UDQS_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTTPD2UDQS_YMMu32_MASKmskw_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2UDQS_YMMu32_MASKmskw_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2UQQS_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2UQQS_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2UQQS_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2UQQS_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2UQQS_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2UQQS_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2UQQS_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2UQQS_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2UQQS_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2UQQS_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPD2UQQS_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTPD2UQQS_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2IBS_XMMi8_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2IBS_XMMi8_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2IBS_XMMi8_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2IBS_XMMi8_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2IBS_YMMi8_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2IBS_YMMi8_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2IBS_YMMi8_MASKmskw_YMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2IBS_YMMi8_MASKmskw_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2IBS_ZMMi8_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2IBS_ZMMi8_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2IBS_ZMMi8_MASKmskw_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2IBS_ZMMi8_MASKmskw_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2IUBS_XMMu8_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2IUBS_XMMu8_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2IUBS_XMMu8_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2IUBS_XMMu8_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2IUBS_YMMu8_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2IUBS_YMMu8_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2IUBS_YMMu8_MASKmskw_YMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2IUBS_YMMu8_MASKmskw_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2IUBS_ZMMu8_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2IUBS_ZMMu8_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2IUBS_ZMMu8_MASKmskw_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2IUBS_ZMMu8_MASKmskw_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2DQS_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2DQS_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2DQS_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2DQS_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2DQS_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2DQS_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2DQS_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2DQS_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2DQS_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2DQS_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2DQS_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2DQS_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2IBS_XMMi8_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2IBS_XMMi8_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2IBS_XMMi8_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2IBS_XMMi8_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2IBS_YMMi8_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2IBS_YMMi8_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2IBS_YMMi8_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2IBS_YMMi8_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2IBS_ZMMi8_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2IBS_ZMMi8_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2IBS_ZMMi8_MASKmskw_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2IBS_ZMMi8_MASKmskw_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2IUBS_XMMu8_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2IUBS_XMMu8_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2IUBS_XMMu8_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2IUBS_XMMu8_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2IUBS_YMMu8_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2IUBS_YMMu8_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2IUBS_YMMu8_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2IUBS_YMMu8_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2IUBS_ZMMu8_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2IUBS_ZMMu8_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2IUBS_ZMMu8_MASKmskw_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2IUBS_ZMMu8_MASKmskw_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2QQS_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2QQS_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2QQS_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2QQS_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2QQS_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2QQS_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2QQS_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2QQS_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2QQS_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2QQS_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2QQS_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2QQS_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2UDQS_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2UDQS_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2UDQS_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2UDQS_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2UDQS_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2UDQS_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2UDQS_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2UDQS_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2UDQS_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2UDQS_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2UDQS_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2UDQS_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2UQQS_XMMu64_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2UQQS_XMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2UQQS_XMMu64_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2UQQS_XMMu64_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2UQQS_YMMu64_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2UQQS_YMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2UQQS_YMMu64_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2UQQS_YMMu64_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2UQQS_ZMMu64_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2UQQS_ZMMu64_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTPS2UQQS_ZMMu64_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTPS2UQQS_ZMMu64_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSD2SI_GPR32d_MEMq_DEFINED

#define XED_IFORM_VCVTTSD2SI_GPR32d_MEMq_DEFINED   1

◆ XED_IFORM_VCVTTSD2SI_GPR32d_XMMq_DEFINED

#define XED_IFORM_VCVTTSD2SI_GPR32d_XMMq_DEFINED   1

◆ XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSD2SI_GPR64q_MEMq_DEFINED

#define XED_IFORM_VCVTTSD2SI_GPR64q_MEMq_DEFINED   1

◆ XED_IFORM_VCVTTSD2SI_GPR64q_XMMq_DEFINED

#define XED_IFORM_VCVTTSD2SI_GPR64q_XMMq_DEFINED   1

◆ XED_IFORM_VCVTTSD2SIS_GPR32i32_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTSD2SIS_GPR32i32_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSD2SIS_GPR32i32_XMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTSD2SIS_GPR32i32_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSD2SIS_GPR64i64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTSD2SIS_GPR64i64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSD2SIS_GPR64i64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTSD2SIS_GPR64i64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSD2USIS_GPR32u32_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTSD2USIS_GPR32u32_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSD2USIS_GPR32u32_XMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTSD2USIS_GPR32u32_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSD2USIS_GPR64u64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTSD2USIS_GPR64u64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSD2USIS_GPR64u64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VCVTTSD2USIS_GPR64u64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSH2SI_GPR32i32_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTSH2SI_GPR32i32_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSH2SI_GPR64i64_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTSH2SI_GPR64i64_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSH2USI_GPR32u32_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTSH2USI_GPR32u32_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSH2USI_GPR64u64_MEMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTSH2USI_GPR64u64_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512_DEFINED

#define XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSS2SI_GPR32d_MEMd_DEFINED

#define XED_IFORM_VCVTTSS2SI_GPR32d_MEMd_DEFINED   1

◆ XED_IFORM_VCVTTSS2SI_GPR32d_XMMd_DEFINED

#define XED_IFORM_VCVTTSS2SI_GPR32d_XMMd_DEFINED   1

◆ XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSS2SI_GPR64q_MEMd_DEFINED

#define XED_IFORM_VCVTTSS2SI_GPR64q_MEMd_DEFINED   1

◆ XED_IFORM_VCVTTSS2SI_GPR64q_XMMd_DEFINED

#define XED_IFORM_VCVTTSS2SI_GPR64q_XMMd_DEFINED   1

◆ XED_IFORM_VCVTTSS2SIS_GPR32i32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTSS2SIS_GPR32i32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSS2SIS_GPR32i32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTSS2SIS_GPR32i32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSS2SIS_GPR64i64_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTSS2SIS_GPR64i64_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSS2SIS_GPR64i64_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTSS2SIS_GPR64i64_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSS2USIS_GPR32u32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTSS2USIS_GPR32u32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSS2USIS_GPR32u32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTSS2USIS_GPR32u32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSS2USIS_GPR64u64_MEMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTSS2USIS_GPR64u64_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTTSS2USIS_GPR64u64_XMMf32_AVX512_DEFINED

#define XED_IFORM_VCVTTSS2USIS_GPR64u64_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512_DEFINED

#define XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512_DEFINED

#define XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512_DEFINED

#define XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512_DEFINED

#define XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_DEFINED

#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128_DEFINED

#define XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256_DEFINED

#define XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512_DEFINED

#define XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512_DEFINED

#define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512_DEFINED

#define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512_DEFINED

#define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512_DEFINED

#define XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512_DEFINED

#define XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512_DEFINED

#define XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512_DEFINED

#define XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512_DEFINED

#define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512_DEFINED

#define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512_DEFINED

#define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512_DEFINED

#define XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512_DEFINED

#define XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512_DEFINED

#define XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512_DEFINED

#define XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512_DEFINED

#define XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512_DEFINED

#define XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512_DEFINED

#define XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512_DEFINED

#define XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512_DEFINED

#define XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512_DEFINED

#define XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512_DEFINED

#define XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VDIVBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VDIVBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VDIVBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

#define XED_IFORM_VDIVBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VDIVBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VDIVBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VDIVBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

#define XED_IFORM_VDIVBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VDIVBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VDIVBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VDIVBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

#define XED_IFORM_VDIVBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VDIVPS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VDIVPS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VDIVPS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VDIVPS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VDIVSD_XMMdq_XMMdq_MEMq_DEFINED

#define XED_IFORM_VDIVSD_XMMdq_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_VDIVSD_XMMdq_XMMdq_XMMq_DEFINED

#define XED_IFORM_VDIVSD_XMMdq_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd_DEFINED

#define XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd_DEFINED   1

◆ XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd_DEFINED

#define XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd_DEFINED   1

◆ XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VDPPHPS_XMMf32_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED

#define XED_IFORM_VDPPHPS_XMMf32_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VDPPHPS_XMMf32_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED

#define XED_IFORM_VDPPHPS_XMMf32_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VDPPHPS_YMMf32_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED

#define XED_IFORM_VDPPHPS_YMMf32_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VDPPHPS_YMMf32_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED

#define XED_IFORM_VDPPHPS_YMMf32_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VDPPHPS_ZMMf32_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED

#define XED_IFORM_VDPPHPS_ZMMf32_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VDPPHPS_ZMMf32_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED

#define XED_IFORM_VDPPHPS_ZMMf32_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED

#define XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1

◆ XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VERR_GPR16_DEFINED

#define XED_IFORM_VERR_GPR16_DEFINED   1

◆ XED_IFORM_VERR_MEMw_DEFINED

#define XED_IFORM_VERR_MEMw_DEFINED   1

◆ XED_IFORM_VERW_GPR16_DEFINED

#define XED_IFORM_VERW_GPR16_DEFINED   1

◆ XED_IFORM_VERW_MEMw_DEFINED

#define XED_IFORM_VERW_MEMw_DEFINED   1

◆ XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER_DEFINED

#define XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER_DEFINED   1

◆ XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER_DEFINED

#define XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER_DEFINED   1

◆ XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER_DEFINED

#define XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER_DEFINED   1

◆ XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER_DEFINED

#define XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER_DEFINED   1

◆ XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED

#define XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED

#define XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VEXTRACTF128_MEMdq_YMMdq_IMMb_DEFINED

#define XED_IFORM_VEXTRACTF128_MEMdq_YMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb_DEFINED

#define XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VEXTRACTI128_MEMdq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VEXTRACTI128_MEMdq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VEXTRACTPS_GPR32_XMMdq_IMMb_DEFINED

#define XED_IFORM_VEXTRACTPS_GPR32_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VEXTRACTPS_MEMd_XMMdq_IMMb_DEFINED

#define XED_IFORM_VEXTRACTPS_MEMd_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED

#define XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED

#define XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED

#define XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED

#define XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED

#define XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED

#define XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED

#define XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED

#define XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED

#define XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED

#define XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED

#define XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED

#define XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED

#define XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED

#define XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED

#define XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED

#define XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFMADD132BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

#define XED_IFORM_VFMADD132BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFMADD132BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

#define XED_IFORM_VFMADD132BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFMADD132BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

#define XED_IFORM_VFMADD132BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132PS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMADD132PS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMADD132PS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMADD132PS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132SD_XMMdq_XMMq_MEMq_DEFINED

#define XED_IFORM_VFMADD132SD_XMMdq_XMMq_MEMq_DEFINED   1

◆ XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq_DEFINED

#define XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq_DEFINED   1

◆ XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd_DEFINED

#define XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd_DEFINED   1

◆ XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd_DEFINED

#define XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd_DEFINED   1

◆ XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFMADD213BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

#define XED_IFORM_VFMADD213BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFMADD213BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

#define XED_IFORM_VFMADD213BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFMADD213BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

#define XED_IFORM_VFMADD213BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213PS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMADD213PS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMADD213PS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMADD213PS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213SD_XMMdq_XMMq_MEMq_DEFINED

#define XED_IFORM_VFMADD213SD_XMMdq_XMMq_MEMq_DEFINED   1

◆ XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq_DEFINED

#define XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq_DEFINED   1

◆ XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd_DEFINED

#define XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd_DEFINED   1

◆ XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd_DEFINED

#define XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd_DEFINED   1

◆ XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFMADD231BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

#define XED_IFORM_VFMADD231BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFMADD231BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

#define XED_IFORM_VFMADD231BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFMADD231BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

#define XED_IFORM_VFMADD231BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231PS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMADD231PS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMADD231PS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMADD231PS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231SD_XMMdq_XMMq_MEMq_DEFINED

#define XED_IFORM_VFMADD231SD_XMMdq_XMMq_MEMq_DEFINED   1

◆ XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq_DEFINED

#define XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq_DEFINED   1

◆ XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd_DEFINED

#define XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd_DEFINED   1

◆ XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd_DEFINED

#define XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd_DEFINED   1

◆ XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED

#define XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED

#define XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED

#define XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED

#define XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED

#define XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED

#define XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED

#define XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED

#define XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED

#define XED_IFORM_VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED

#define XED_IFORM_VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMADDSD_XMMdq_XMMq_MEMq_XMMq_DEFINED

#define XED_IFORM_VFMADDSD_XMMdq_XMMq_MEMq_XMMq_DEFINED   1

◆ XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_MEMq_DEFINED

#define XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_MEMq_DEFINED   1

◆ XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_XMMq_DEFINED

#define XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_XMMq_DEFINED   1

◆ XED_IFORM_VFMADDSS_XMMdq_XMMd_MEMd_XMMd_DEFINED

#define XED_IFORM_VFMADDSS_XMMdq_XMMd_MEMd_XMMd_DEFINED   1

◆ XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_MEMd_DEFINED

#define XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_MEMd_DEFINED   1

◆ XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_XMMd_DEFINED

#define XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_XMMd_DEFINED   1

◆ XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED

#define XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED

#define XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMSUB132BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB132BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB132BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB132BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB132BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB132BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB132BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132SD_XMMdq_XMMq_MEMq_DEFINED

#define XED_IFORM_VFMSUB132SD_XMMdq_XMMq_MEMq_DEFINED   1

◆ XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq_DEFINED

#define XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq_DEFINED   1

◆ XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd_DEFINED

#define XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd_DEFINED   1

◆ XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd_DEFINED

#define XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd_DEFINED   1

◆ XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB213BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB213BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB213BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB213BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB213BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB213BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213SD_XMMdq_XMMq_MEMq_DEFINED

#define XED_IFORM_VFMSUB213SD_XMMdq_XMMq_MEMq_DEFINED   1

◆ XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq_DEFINED

#define XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq_DEFINED   1

◆ XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd_DEFINED

#define XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd_DEFINED   1

◆ XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd_DEFINED

#define XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd_DEFINED   1

◆ XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB231BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB231BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB231BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB231BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB231BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB231BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231SD_XMMdq_XMMq_MEMq_DEFINED

#define XED_IFORM_VFMSUB231SD_XMMdq_XMMq_MEMq_DEFINED   1

◆ XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq_DEFINED

#define XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq_DEFINED   1

◆ XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd_DEFINED

#define XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd_DEFINED   1

◆ XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd_DEFINED

#define XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd_DEFINED   1

◆ XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED

#define XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED

#define XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED

#define XED_IFORM_VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED

#define XED_IFORM_VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFMSUBSD_XMMdq_XMMq_MEMq_XMMq_DEFINED

#define XED_IFORM_VFMSUBSD_XMMdq_XMMq_MEMq_XMMq_DEFINED   1

◆ XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_MEMq_DEFINED

#define XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_MEMq_DEFINED   1

◆ XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_XMMq_DEFINED

#define XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_XMMq_DEFINED   1

◆ XED_IFORM_VFMSUBSS_XMMdq_XMMd_MEMd_XMMd_DEFINED

#define XED_IFORM_VFMSUBSS_XMMdq_XMMd_MEMd_XMMd_DEFINED   1

◆ XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_MEMd_DEFINED

#define XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_MEMd_DEFINED   1

◆ XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_XMMd_DEFINED

#define XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_XMMd_DEFINED   1

◆ XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED

#define XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED

#define XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED

#define XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED

#define XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED

#define XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED

#define XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED

#define XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED

#define XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD132BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD132BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD132BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD132BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD132BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD132BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132SD_XMMdq_XMMq_MEMq_DEFINED

#define XED_IFORM_VFNMADD132SD_XMMdq_XMMq_MEMq_DEFINED   1

◆ XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq_DEFINED

#define XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq_DEFINED   1

◆ XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd_DEFINED

#define XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd_DEFINED   1

◆ XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd_DEFINED

#define XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd_DEFINED   1

◆ XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD213BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD213BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD213BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD213BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD213BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD213BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213SD_XMMdq_XMMq_MEMq_DEFINED

#define XED_IFORM_VFNMADD213SD_XMMdq_XMMq_MEMq_DEFINED   1

◆ XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq_DEFINED

#define XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq_DEFINED   1

◆ XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd_DEFINED

#define XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd_DEFINED   1

◆ XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd_DEFINED

#define XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd_DEFINED   1

◆ XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD231BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD231BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD231BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD231BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD231BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD231BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231SD_XMMdq_XMMq_MEMq_DEFINED

#define XED_IFORM_VFNMADD231SD_XMMdq_XMMq_MEMq_DEFINED   1

◆ XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq_DEFINED

#define XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq_DEFINED   1

◆ XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd_DEFINED

#define XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd_DEFINED   1

◆ XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd_DEFINED

#define XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd_DEFINED   1

◆ XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED

#define XED_IFORM_VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED

#define XED_IFORM_VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFNMADDSD_XMMdq_XMMq_MEMq_XMMq_DEFINED

#define XED_IFORM_VFNMADDSD_XMMdq_XMMq_MEMq_XMMq_DEFINED   1

◆ XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_MEMq_DEFINED

#define XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_MEMq_DEFINED   1

◆ XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_XMMq_DEFINED

#define XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_XMMq_DEFINED   1

◆ XED_IFORM_VFNMADDSS_XMMdq_XMMd_MEMd_XMMd_DEFINED

#define XED_IFORM_VFNMADDSS_XMMdq_XMMd_MEMd_XMMd_DEFINED   1

◆ XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_MEMd_DEFINED

#define XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_MEMd_DEFINED   1

◆ XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd_DEFINED

#define XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd_DEFINED   1

◆ XED_IFORM_VFNMSUB132BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_MEMq_DEFINED

#define XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_MEMq_DEFINED   1

◆ XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq_DEFINED

#define XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq_DEFINED   1

◆ XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd_DEFINED

#define XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd_DEFINED   1

◆ XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd_DEFINED

#define XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd_DEFINED   1

◆ XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_MEMq_DEFINED

#define XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_MEMq_DEFINED   1

◆ XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq_DEFINED

#define XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq_DEFINED   1

◆ XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd_DEFINED

#define XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd_DEFINED   1

◆ XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd_DEFINED

#define XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd_DEFINED   1

◆ XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_MEMq_DEFINED

#define XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_MEMq_DEFINED   1

◆ XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq_DEFINED

#define XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq_DEFINED   1

◆ XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd_DEFINED

#define XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd_DEFINED   1

◆ XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd_DEFINED

#define XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd_DEFINED   1

◆ XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED

#define XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED

#define XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq_DEFINED

#define XED_IFORM_VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq_DEFINED   1

◆ XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq_DEFINED

#define XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq_DEFINED   1

◆ XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq_DEFINED

#define XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq_DEFINED   1

◆ XED_IFORM_VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd_DEFINED

#define XED_IFORM_VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd_DEFINED   1

◆ XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd_DEFINED

#define XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd_DEFINED   1

◆ XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd_DEFINED

#define XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd_DEFINED   1

◆ XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL128_DEFINED

#define XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL256_DEFINED

#define XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL512_DEFINED

#define XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_XMMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_XMMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_YMMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_YMMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_ZMMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_ZMMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128_DEFINED

#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256_DEFINED

#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512_DEFINED

#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128_DEFINED

#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256_DEFINED

#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512_DEFINED

#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128_DEFINED

#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256_DEFINED

#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512_DEFINED

#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VFRCZPD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFRCZPD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFRCZPD_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFRCZPD_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFRCZPD_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFRCZPD_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFRCZPD_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFRCZPD_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFRCZPS_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VFRCZPS_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VFRCZPS_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VFRCZPS_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VFRCZPS_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VFRCZPS_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VFRCZPS_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VFRCZPS_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VFRCZSD_XMMdq_MEMq_DEFINED

#define XED_IFORM_VFRCZSD_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_VFRCZSD_XMMdq_XMMq_DEFINED

#define XED_IFORM_VFRCZSD_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_VFRCZSS_XMMdq_MEMd_DEFINED

#define XED_IFORM_VFRCZSS_XMMdq_MEMd_DEFINED   1

◆ XED_IFORM_VFRCZSS_XMMdq_XMMd_DEFINED

#define XED_IFORM_VFRCZSS_XMMdq_XMMd_DEFINED   1

◆ XED_IFORM_VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128_DEFINED

#define XED_IFORM_VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128_DEFINED

#define XED_IFORM_VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128_DEFINED   1

◆ XED_IFORM_VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256_DEFINED

#define XED_IFORM_VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256_DEFINED

#define XED_IFORM_VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256_DEFINED   1

◆ XED_IFORM_VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512_DEFINED

#define XED_IFORM_VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128_DEFINED

#define XED_IFORM_VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128_DEFINED

#define XED_IFORM_VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128_DEFINED   1

◆ XED_IFORM_VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256_DEFINED

#define XED_IFORM_VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256_DEFINED

#define XED_IFORM_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256_DEFINED   1

◆ XED_IFORM_VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512_DEFINED

#define XED_IFORM_VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED

#define XED_IFORM_VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED   1

◆ XED_IFORM_VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED

#define XED_IFORM_VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED   1

◆ XED_IFORM_VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED

#define XED_IFORM_VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED   1

◆ XED_IFORM_VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED

#define XED_IFORM_VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED   1

◆ XED_IFORM_VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED

#define XED_IFORM_VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED   1

◆ XED_IFORM_VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED

#define XED_IFORM_VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED   1

◆ XED_IFORM_VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED

#define XED_IFORM_VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED   1

◆ XED_IFORM_VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED

#define XED_IFORM_VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED   1

◆ XED_IFORM_VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128_DEFINED

#define XED_IFORM_VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128_DEFINED

#define XED_IFORM_VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128_DEFINED   1

◆ XED_IFORM_VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256_DEFINED

#define XED_IFORM_VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256_DEFINED

#define XED_IFORM_VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256_DEFINED   1

◆ XED_IFORM_VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512_DEFINED

#define XED_IFORM_VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128_DEFINED

#define XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256_DEFINED

#define XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128_DEFINED

#define XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128_DEFINED   1

◆ XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256_DEFINED

#define XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256_DEFINED   1

◆ XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512_DEFINED

#define XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VGETEXPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VGETEXPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512_DEFINED

#define XED_IFORM_VGETEXPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VGETEXPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512_DEFINED

#define XED_IFORM_VGETEXPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VGETEXPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512_DEFINED

#define XED_IFORM_VGETEXPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED

#define XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED

#define XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED

#define XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8_DEFINED

#define XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8_DEFINED   1

◆ XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8_DEFINED

#define XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8_DEFINED   1

◆ XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8_DEFINED

#define XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8_DEFINED   1

◆ XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8_DEFINED

#define XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8_DEFINED   1

◆ XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8_DEFINED

#define XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8_DEFINED   1

◆ XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8_DEFINED

#define XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8_DEFINED   1

◆ XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8_DEFINED

#define XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8_DEFINED   1

◆ XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8_DEFINED

#define XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8_DEFINED   1

◆ XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED

#define XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_MEMu8_DEFINED

#define XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_MEMu8_DEFINED   1

◆ XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_XMMu8_DEFINED

#define XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_XMMu8_DEFINED   1

◆ XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED

#define XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_MEMu8_DEFINED

#define XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_MEMu8_DEFINED   1

◆ XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_YMMu8_DEFINED

#define XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_YMMu8_DEFINED   1

◆ XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED

#define XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VHADDPD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VHADDPD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VHADDPD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VHADDPD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VHADDPD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VHADDPD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VHADDPD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VHADDPD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VHADDPS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VHADDPS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VHADDPS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VHADDPS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VHADDPS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VHADDPS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VHADDPS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VHADDPS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VHSUBPD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VHSUBPD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VHSUBPD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VHSUBPD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VHSUBPD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VHSUBPD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VHSUBPD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VHSUBPD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VHSUBPS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VHSUBPS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VHSUBPS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VHSUBPS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VHSUBPS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VHSUBPS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VHSUBPS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VHSUBPS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VINSERTPS_XMMdq_XMMdq_MEMd_IMMb_DEFINED

#define XED_IFORM_VINSERTPS_XMMdq_XMMdq_MEMd_IMMb_DEFINED   1

◆ XED_IFORM_VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VLDDQU_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VLDDQU_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VLDDQU_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VLDDQU_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VLDMXCSR_MEMd_DEFINED

#define XED_IFORM_VLDMXCSR_MEMd_DEFINED   1

◆ XED_IFORM_VMASKMOVDQU_XMMxub_XMMxub_DEFINED

#define XED_IFORM_VMASKMOVDQU_XMMxub_XMMxub_DEFINED   1

◆ XED_IFORM_VMASKMOVPD_MEMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VMASKMOVPD_MEMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VMASKMOVPD_MEMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VMASKMOVPD_MEMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VMASKMOVPD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VMASKMOVPD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VMASKMOVPD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VMASKMOVPD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VMASKMOVPS_MEMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VMASKMOVPS_MEMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VMAXBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VMAXBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VMAXBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

#define XED_IFORM_VMAXBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VMAXBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VMAXBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VMAXBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

#define XED_IFORM_VMAXBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VMAXBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VMAXBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VMAXBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

#define XED_IFORM_VMAXBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMAXPS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VMAXPS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VMAXPS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VMAXPS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMAXSD_XMMdq_XMMdq_MEMq_DEFINED

#define XED_IFORM_VMAXSD_XMMdq_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_VMAXSD_XMMdq_XMMdq_XMMq_DEFINED

#define XED_IFORM_VMAXSD_XMMdq_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd_DEFINED

#define XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd_DEFINED   1

◆ XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd_DEFINED

#define XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd_DEFINED   1

◆ XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMCALL_DEFINED

#define XED_IFORM_VMCALL_DEFINED   1

◆ XED_IFORM_VMCLEAR_MEMq_DEFINED

#define XED_IFORM_VMCLEAR_MEMq_DEFINED   1

◆ XED_IFORM_VMFUNC_DEFINED

#define XED_IFORM_VMFUNC_DEFINED   1

◆ XED_IFORM_VMINBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VMINBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VMINBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

#define XED_IFORM_VMINBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VMINBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VMINBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VMINBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

#define XED_IFORM_VMINBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VMINBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VMINBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VMINBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

#define XED_IFORM_VMINBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VMINMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMINPS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VMINPS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VMINPS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VMINPS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMINSD_XMMdq_XMMdq_MEMq_DEFINED

#define XED_IFORM_VMINSD_XMMdq_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_VMINSD_XMMdq_XMMdq_XMMq_DEFINED

#define XED_IFORM_VMINSD_XMMdq_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd_DEFINED

#define XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd_DEFINED   1

◆ XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd_DEFINED

#define XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd_DEFINED   1

◆ XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMLAUNCH_DEFINED

#define XED_IFORM_VMLAUNCH_DEFINED   1

◆ XED_IFORM_VMLOAD_ArAX_DEFINED

#define XED_IFORM_VMLOAD_ArAX_DEFINED   1

◆ XED_IFORM_VMMCALL_DEFINED

#define XED_IFORM_VMMCALL_DEFINED   1

◆ XED_IFORM_VMOVAPD_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VMOVAPD_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED

#define XED_IFORM_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512_DEFINED

#define XED_IFORM_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVAPD_MEMqq_YMMqq_DEFINED

#define XED_IFORM_VMOVAPD_MEMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VMOVAPD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VMOVAPD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VMOVAPD_XMMdq_XMMdq_28_DEFINED

#define XED_IFORM_VMOVAPD_XMMdq_XMMdq_28_DEFINED   1

◆ XED_IFORM_VMOVAPD_XMMdq_XMMdq_29_DEFINED

#define XED_IFORM_VMOVAPD_XMMdq_XMMdq_29_DEFINED   1

◆ XED_IFORM_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED

#define XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED

#define XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVAPD_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VMOVAPD_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VMOVAPD_YMMqq_YMMqq_28_DEFINED

#define XED_IFORM_VMOVAPD_YMMqq_YMMqq_28_DEFINED   1

◆ XED_IFORM_VMOVAPD_YMMqq_YMMqq_29_DEFINED

#define XED_IFORM_VMOVAPD_YMMqq_YMMqq_29_DEFINED   1

◆ XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVAPS_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VMOVAPS_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVAPS_MEMqq_YMMqq_DEFINED

#define XED_IFORM_VMOVAPS_MEMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VMOVAPS_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VMOVAPS_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VMOVAPS_XMMdq_XMMdq_28_DEFINED

#define XED_IFORM_VMOVAPS_XMMdq_XMMdq_28_DEFINED   1

◆ XED_IFORM_VMOVAPS_XMMdq_XMMdq_29_DEFINED

#define XED_IFORM_VMOVAPS_XMMdq_XMMdq_29_DEFINED   1

◆ XED_IFORM_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVAPS_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VMOVAPS_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VMOVAPS_YMMqq_YMMqq_28_DEFINED

#define XED_IFORM_VMOVAPS_YMMqq_YMMqq_28_DEFINED   1

◆ XED_IFORM_VMOVAPS_YMMqq_YMMqq_29_DEFINED

#define XED_IFORM_VMOVAPS_YMMqq_YMMqq_29_DEFINED   1

◆ XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVD_GPR32d_XMMd_DEFINED

#define XED_IFORM_VMOVD_GPR32d_XMMd_DEFINED   1

◆ XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVD_MEMd_XMMd_DEFINED

#define XED_IFORM_VMOVD_MEMd_XMMd_DEFINED   1

◆ XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512_MOVZXC_DEFINED

#define XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512_MOVZXC_DEFINED   1

◆ XED_IFORM_VMOVD_XMMdq_GPR32d_DEFINED

#define XED_IFORM_VMOVD_XMMdq_GPR32d_DEFINED   1

◆ XED_IFORM_VMOVD_XMMdq_MEMd_DEFINED

#define XED_IFORM_VMOVD_XMMdq_MEMd_DEFINED   1

◆ XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512_DEFINED

#define XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512_MOVZXC_DEFINED

#define XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512_MOVZXC_DEFINED   1

◆ XED_IFORM_VMOVD_XMMu32_XMMu32_AVX512_MOVZXC_DEFINED

#define XED_IFORM_VMOVD_XMMu32_XMMu32_AVX512_MOVZXC_DEFINED   1

◆ XED_IFORM_VMOVDDUP_XMMdq_MEMq_DEFINED

#define XED_IFORM_VMOVDDUP_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_VMOVDDUP_XMMdq_XMMq_DEFINED

#define XED_IFORM_VMOVDDUP_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED

#define XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED

#define XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDDUP_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VMOVDDUP_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VMOVDDUP_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VMOVDDUP_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512_DEFINED

#define XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED

#define XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512_DEFINED

#define XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED

#define XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQA_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VMOVDQA_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VMOVDQA_MEMqq_YMMqq_DEFINED

#define XED_IFORM_VMOVDQA_MEMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VMOVDQA_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VMOVDQA_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VMOVDQA_XMMdq_XMMdq_6F_DEFINED

#define XED_IFORM_VMOVDQA_XMMdq_XMMdq_6F_DEFINED   1

◆ XED_IFORM_VMOVDQA_XMMdq_XMMdq_7F_DEFINED

#define XED_IFORM_VMOVDQA_XMMdq_XMMdq_7F_DEFINED   1

◆ XED_IFORM_VMOVDQA_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VMOVDQA_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VMOVDQA_YMMqq_YMMqq_6F_DEFINED

#define XED_IFORM_VMOVDQA_YMMqq_YMMqq_6F_DEFINED   1

◆ XED_IFORM_VMOVDQA_YMMqq_YMMqq_7F_DEFINED

#define XED_IFORM_VMOVDQA_YMMqq_YMMqq_7F_DEFINED   1

◆ XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512_DEFINED

#define XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512_DEFINED

#define XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED

#define XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED

#define XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED

#define XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED

#define XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED

#define XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512_DEFINED

#define XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED

#define XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512_DEFINED

#define XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED

#define XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512_DEFINED

#define XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512_DEFINED

#define XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512_DEFINED

#define XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED

#define XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED

#define XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED

#define XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED

#define XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED

#define XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED

#define XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VMOVDQU_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VMOVDQU_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VMOVDQU_MEMqq_YMMqq_DEFINED

#define XED_IFORM_VMOVDQU_MEMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VMOVDQU_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VMOVDQU_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VMOVDQU_XMMdq_XMMdq_6F_DEFINED

#define XED_IFORM_VMOVDQU_XMMdq_XMMdq_6F_DEFINED   1

◆ XED_IFORM_VMOVDQU_XMMdq_XMMdq_7F_DEFINED

#define XED_IFORM_VMOVDQU_XMMdq_XMMdq_7F_DEFINED   1

◆ XED_IFORM_VMOVDQU_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VMOVDQU_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VMOVDQU_YMMqq_YMMqq_6F_DEFINED

#define XED_IFORM_VMOVDQU_YMMqq_YMMqq_6F_DEFINED   1

◆ XED_IFORM_VMOVDQU_YMMqq_YMMqq_7F_DEFINED

#define XED_IFORM_VMOVDQU_YMMqq_YMMqq_7F_DEFINED   1

◆ XED_IFORM_VMOVHLPS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VMOVHLPS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVHPD_MEMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VMOVHPD_MEMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVHPD_MEMq_XMMdq_DEFINED

#define XED_IFORM_VMOVHPD_MEMq_XMMdq_DEFINED   1

◆ XED_IFORM_VMOVHPD_XMMdq_XMMq_MEMq_DEFINED

#define XED_IFORM_VMOVHPD_XMMdq_XMMq_MEMq_DEFINED   1

◆ XED_IFORM_VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVHPS_MEMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VMOVHPS_MEMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVHPS_MEMq_XMMdq_DEFINED

#define XED_IFORM_VMOVHPS_MEMq_XMMdq_DEFINED   1

◆ XED_IFORM_VMOVHPS_XMMdq_XMMq_MEMq_DEFINED

#define XED_IFORM_VMOVHPS_XMMdq_XMMq_MEMq_DEFINED   1

◆ XED_IFORM_VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVLHPS_XMMdq_XMMq_XMMq_DEFINED

#define XED_IFORM_VMOVLHPS_XMMdq_XMMq_XMMq_DEFINED   1

◆ XED_IFORM_VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVLPD_MEMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VMOVLPD_MEMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVLPD_MEMq_XMMq_DEFINED

#define XED_IFORM_VMOVLPD_MEMq_XMMq_DEFINED   1

◆ XED_IFORM_VMOVLPD_XMMdq_XMMdq_MEMq_DEFINED

#define XED_IFORM_VMOVLPD_XMMdq_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVLPS_MEMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VMOVLPS_MEMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVLPS_MEMq_XMMq_DEFINED

#define XED_IFORM_VMOVLPS_MEMq_XMMq_DEFINED   1

◆ XED_IFORM_VMOVLPS_XMMdq_XMMdq_MEMq_DEFINED

#define XED_IFORM_VMOVLPS_XMMdq_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVMSKPD_GPR32d_XMMdq_DEFINED

#define XED_IFORM_VMOVMSKPD_GPR32d_XMMdq_DEFINED   1

◆ XED_IFORM_VMOVMSKPD_GPR32d_YMMqq_DEFINED

#define XED_IFORM_VMOVMSKPD_GPR32d_YMMqq_DEFINED   1

◆ XED_IFORM_VMOVMSKPS_GPR32d_XMMdq_DEFINED

#define XED_IFORM_VMOVMSKPS_GPR32d_XMMdq_DEFINED   1

◆ XED_IFORM_VMOVMSKPS_GPR32d_YMMqq_DEFINED

#define XED_IFORM_VMOVMSKPS_GPR32d_YMMqq_DEFINED   1

◆ XED_IFORM_VMOVNTDQ_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VMOVNTDQ_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VMOVNTDQ_MEMqq_YMMqq_DEFINED

#define XED_IFORM_VMOVNTDQ_MEMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VMOVNTDQ_MEMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VMOVNTDQ_MEMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVNTDQ_MEMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VMOVNTDQ_MEMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVNTDQ_MEMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VMOVNTDQ_MEMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVNTDQA_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VMOVNTDQA_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VMOVNTDQA_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VMOVNTDQA_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVNTDQA_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VMOVNTDQA_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VMOVNTDQA_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VMOVNTDQA_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVNTDQA_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VMOVNTDQA_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVNTPD_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VMOVNTPD_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VMOVNTPD_MEMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VMOVNTPD_MEMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVNTPD_MEMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VMOVNTPD_MEMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVNTPD_MEMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VMOVNTPD_MEMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVNTPD_MEMqq_YMMqq_DEFINED

#define XED_IFORM_VMOVNTPD_MEMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VMOVNTPS_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VMOVNTPS_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VMOVNTPS_MEMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VMOVNTPS_MEMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVNTPS_MEMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VMOVNTPS_MEMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVNTPS_MEMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VMOVNTPS_MEMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVNTPS_MEMqq_YMMqq_DEFINED

#define XED_IFORM_VMOVNTPS_MEMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VMOVQ_GPR64q_XMMq_DEFINED

#define XED_IFORM_VMOVQ_GPR64q_XMMq_DEFINED   1

◆ XED_IFORM_VMOVQ_GPR64u64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VMOVQ_GPR64u64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVQ_MEMq_XMMq_7E_DEFINED

#define XED_IFORM_VMOVQ_MEMq_XMMq_7E_DEFINED   1

◆ XED_IFORM_VMOVQ_MEMq_XMMq_D6_DEFINED

#define XED_IFORM_VMOVQ_MEMq_XMMq_D6_DEFINED   1

◆ XED_IFORM_VMOVQ_MEMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VMOVQ_MEMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVQ_XMMdq_GPR64q_DEFINED

#define XED_IFORM_VMOVQ_XMMdq_GPR64q_DEFINED   1

◆ XED_IFORM_VMOVQ_XMMdq_MEMq_6E_DEFINED

#define XED_IFORM_VMOVQ_XMMdq_MEMq_6E_DEFINED   1

◆ XED_IFORM_VMOVQ_XMMdq_MEMq_7E_DEFINED

#define XED_IFORM_VMOVQ_XMMdq_MEMq_7E_DEFINED   1

◆ XED_IFORM_VMOVQ_XMMdq_XMMq_7E_DEFINED

#define XED_IFORM_VMOVQ_XMMdq_XMMq_7E_DEFINED   1

◆ XED_IFORM_VMOVQ_XMMdq_XMMq_D6_DEFINED

#define XED_IFORM_VMOVQ_XMMdq_XMMq_D6_DEFINED   1

◆ XED_IFORM_VMOVQ_XMMu64_GPR64u64_AVX512_DEFINED

#define XED_IFORM_VMOVQ_XMMu64_GPR64u64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVRSB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED

#define XED_IFORM_VMOVRSB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VMOVRSB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED

#define XED_IFORM_VMOVRSB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VMOVRSB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED

#define XED_IFORM_VMOVRSB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VMOVRSD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VMOVRSD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVRSD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VMOVRSD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVRSD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VMOVRSD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVRSQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_VMOVRSQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVRSQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_VMOVRSQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVRSQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_VMOVRSQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVRSW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED

#define XED_IFORM_VMOVRSW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VMOVRSW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED

#define XED_IFORM_VMOVRSW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VMOVRSW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED

#define XED_IFORM_VMOVRSW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED

#define XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVSD_MEMq_XMMq_DEFINED

#define XED_IFORM_VMOVSD_MEMq_XMMq_DEFINED   1

◆ XED_IFORM_VMOVSD_XMMdq_MEMq_DEFINED

#define XED_IFORM_VMOVSD_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_10_DEFINED

#define XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_10_DEFINED   1

◆ XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_11_DEFINED

#define XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_11_DEFINED   1

◆ XED_IFORM_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMOVSHDUP_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VMOVSHDUP_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VMOVSHDUP_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VMOVSHDUP_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVSHDUP_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VMOVSHDUP_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VMOVSHDUP_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VMOVSHDUP_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVSLDUP_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VMOVSLDUP_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VMOVSLDUP_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VMOVSLDUP_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVSLDUP_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VMOVSLDUP_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VMOVSLDUP_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VMOVSLDUP_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVSS_MEMd_XMMd_DEFINED

#define XED_IFORM_VMOVSS_MEMd_XMMd_DEFINED   1

◆ XED_IFORM_VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVSS_XMMdq_MEMd_DEFINED

#define XED_IFORM_VMOVSS_XMMdq_MEMd_DEFINED   1

◆ XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_10_DEFINED

#define XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_10_DEFINED   1

◆ XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_11_DEFINED

#define XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_11_DEFINED   1

◆ XED_IFORM_VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVUPD_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VMOVUPD_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED

#define XED_IFORM_VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512_DEFINED

#define XED_IFORM_VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVUPD_MEMqq_YMMqq_DEFINED

#define XED_IFORM_VMOVUPD_MEMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VMOVUPD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VMOVUPD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VMOVUPD_XMMdq_XMMdq_10_DEFINED

#define XED_IFORM_VMOVUPD_XMMdq_XMMdq_10_DEFINED   1

◆ XED_IFORM_VMOVUPD_XMMdq_XMMdq_11_DEFINED

#define XED_IFORM_VMOVUPD_XMMdq_XMMdq_11_DEFINED   1

◆ XED_IFORM_VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED

#define XED_IFORM_VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED

#define XED_IFORM_VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVUPD_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VMOVUPD_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VMOVUPD_YMMqq_YMMqq_10_DEFINED

#define XED_IFORM_VMOVUPD_YMMqq_YMMqq_10_DEFINED   1

◆ XED_IFORM_VMOVUPD_YMMqq_YMMqq_11_DEFINED

#define XED_IFORM_VMOVUPD_YMMqq_YMMqq_11_DEFINED   1

◆ XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMOVUPS_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VMOVUPS_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVUPS_MEMqq_YMMqq_DEFINED

#define XED_IFORM_VMOVUPS_MEMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VMOVUPS_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VMOVUPS_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VMOVUPS_XMMdq_XMMdq_10_DEFINED

#define XED_IFORM_VMOVUPS_XMMdq_XMMdq_10_DEFINED   1

◆ XED_IFORM_VMOVUPS_XMMdq_XMMdq_11_DEFINED

#define XED_IFORM_VMOVUPS_XMMdq_XMMdq_11_DEFINED   1

◆ XED_IFORM_VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVUPS_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VMOVUPS_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VMOVUPS_YMMqq_YMMqq_10_DEFINED

#define XED_IFORM_VMOVUPS_YMMqq_YMMqq_10_DEFINED   1

◆ XED_IFORM_VMOVUPS_YMMqq_YMMqq_11_DEFINED

#define XED_IFORM_VMOVUPS_YMMqq_YMMqq_11_DEFINED   1

◆ XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMOVW_GPR32f16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VMOVW_GPR32f16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMOVW_MEMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VMOVW_MEMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMOVW_MEMu16_XMMu16_AVX512_MOVZXC_DEFINED

#define XED_IFORM_VMOVW_MEMu16_XMMu16_AVX512_MOVZXC_DEFINED   1

◆ XED_IFORM_VMOVW_XMMf16_GPR32f16_AVX512_DEFINED

#define XED_IFORM_VMOVW_XMMf16_GPR32f16_AVX512_DEFINED   1

◆ XED_IFORM_VMOVW_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VMOVW_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMOVW_XMMu16_MEMu16_AVX512_MOVZXC_DEFINED

#define XED_IFORM_VMOVW_XMMu16_MEMu16_AVX512_MOVZXC_DEFINED   1

◆ XED_IFORM_VMOVW_XMMu16_XMMu16_AVX512_MOVZXC_DEFINED

#define XED_IFORM_VMOVW_XMMu16_XMMu16_AVX512_MOVZXC_DEFINED   1

◆ XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VMPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VMPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VMPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb_DEFINED

#define XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1

◆ XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VMPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VMPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VMPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VMPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VMPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VMPTRLD_MEMq_DEFINED

#define XED_IFORM_VMPTRLD_MEMq_DEFINED   1

◆ XED_IFORM_VMPTRST_MEMq_DEFINED

#define XED_IFORM_VMPTRST_MEMq_DEFINED   1

◆ XED_IFORM_VMREAD_GPR32_GPR32_DEFINED

#define XED_IFORM_VMREAD_GPR32_GPR32_DEFINED   1

◆ XED_IFORM_VMREAD_GPR64_GPR64_DEFINED

#define XED_IFORM_VMREAD_GPR64_GPR64_DEFINED   1

◆ XED_IFORM_VMREAD_MEMd_GPR32_DEFINED

#define XED_IFORM_VMREAD_MEMd_GPR32_DEFINED   1

◆ XED_IFORM_VMREAD_MEMq_GPR64_DEFINED

#define XED_IFORM_VMREAD_MEMq_GPR64_DEFINED   1

◆ XED_IFORM_VMRESUME_DEFINED

#define XED_IFORM_VMRESUME_DEFINED   1

◆ XED_IFORM_VMRUN_ArAX_DEFINED

#define XED_IFORM_VMRUN_ArAX_DEFINED   1

◆ XED_IFORM_VMSAVE_DEFINED

#define XED_IFORM_VMSAVE_DEFINED   1

◆ XED_IFORM_VMULBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VMULBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VMULBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

#define XED_IFORM_VMULBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VMULBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VMULBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VMULBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

#define XED_IFORM_VMULBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VMULBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VMULBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VMULBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

#define XED_IFORM_VMULBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMULPS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VMULPS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VMULPS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VMULPS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMULSD_XMMdq_XMMdq_MEMq_DEFINED

#define XED_IFORM_VMULSD_XMMdq_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_VMULSD_XMMdq_XMMdq_XMMq_DEFINED

#define XED_IFORM_VMULSD_XMMdq_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd_DEFINED

#define XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd_DEFINED   1

◆ XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd_DEFINED

#define XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd_DEFINED   1

◆ XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VMWRITE_GPR32_GPR32_DEFINED

#define XED_IFORM_VMWRITE_GPR32_GPR32_DEFINED   1

◆ XED_IFORM_VMWRITE_GPR32_MEMd_DEFINED

#define XED_IFORM_VMWRITE_GPR32_MEMd_DEFINED   1

◆ XED_IFORM_VMWRITE_GPR64_GPR64_DEFINED

#define XED_IFORM_VMWRITE_GPR64_GPR64_DEFINED   1

◆ XED_IFORM_VMWRITE_GPR64_MEMq_DEFINED

#define XED_IFORM_VMWRITE_GPR64_MEMq_DEFINED   1

◆ XED_IFORM_VMXOFF_DEFINED

#define XED_IFORM_VMXOFF_DEFINED   1

◆ XED_IFORM_VMXON_MEMq_DEFINED

#define XED_IFORM_VMXON_MEMq_DEFINED   1

◆ XED_IFORM_VORPD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VORPD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VORPD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VORPD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VORPD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VORPD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VORPD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VORPD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VORPS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VORPS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VORPS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VORPS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VORPS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VORPS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VORPS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VORPS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED

#define XED_IFORM_VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED

#define XED_IFORM_VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPABSB_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPABSB_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPABSB_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPABSB_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPABSB_XMMi8_MASKmskw_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPABSB_XMMi8_MASKmskw_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512_DEFINED

#define XED_IFORM_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPABSB_YMMi8_MASKmskw_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPABSB_YMMi8_MASKmskw_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512_DEFINED

#define XED_IFORM_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPABSB_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPABSB_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPABSB_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPABSB_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512_DEFINED

#define XED_IFORM_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPABSD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPABSD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPABSD_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPABSD_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPABSD_XMMi32_MASKmskw_MEMi32_AVX512_DEFINED

#define XED_IFORM_VPABSD_XMMi32_MASKmskw_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPABSD_XMMi32_MASKmskw_XMMi32_AVX512_DEFINED

#define XED_IFORM_VPABSD_XMMi32_MASKmskw_XMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPABSD_YMMi32_MASKmskw_MEMi32_AVX512_DEFINED

#define XED_IFORM_VPABSD_YMMi32_MASKmskw_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPABSD_YMMi32_MASKmskw_YMMi32_AVX512_DEFINED

#define XED_IFORM_VPABSD_YMMi32_MASKmskw_YMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPABSD_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPABSD_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPABSD_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPABSD_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512_DEFINED

#define XED_IFORM_VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512_DEFINED

#define XED_IFORM_VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512_DEFINED

#define XED_IFORM_VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512_DEFINED

#define XED_IFORM_VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512_DEFINED

#define XED_IFORM_VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512_DEFINED

#define XED_IFORM_VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512_DEFINED

#define XED_IFORM_VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512_DEFINED

#define XED_IFORM_VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPABSW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPABSW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPABSW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPABSW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPABSW_XMMi16_MASKmskw_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPABSW_XMMi16_MASKmskw_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPABSW_XMMi16_MASKmskw_XMMi16_AVX512_DEFINED

#define XED_IFORM_VPABSW_XMMi16_MASKmskw_XMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPABSW_YMMi16_MASKmskw_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPABSW_YMMi16_MASKmskw_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPABSW_YMMi16_MASKmskw_YMMi16_AVX512_DEFINED

#define XED_IFORM_VPABSW_YMMi16_MASKmskw_YMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPABSW_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPABSW_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPABSW_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPABSW_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512_DEFINED

#define XED_IFORM_VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPACKSSDW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPACKSSDW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPACKSSDW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPACKSSDW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED

#define XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED

#define XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED

#define XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED

#define XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPACKSSDW_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPACKSSDW_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPACKSSDW_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPACKSSDW_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED

#define XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED

#define XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPACKSSWB_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPACKSSWB_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPACKSSWB_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPACKSSWB_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED

#define XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED

#define XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPACKSSWB_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPACKSSWB_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPACKSSWB_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPACKSSWB_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED

#define XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPACKUSDW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPACKUSDW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPACKUSDW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPACKUSDW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPACKUSDW_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPACKUSDW_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPACKUSDW_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPACKUSDW_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPACKUSWB_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPACKUSWB_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPACKUSWB_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPACKUSWB_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPACKUSWB_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPACKUSWB_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPACKUSWB_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPACKUSWB_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPADDB_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPADDB_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPADDB_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPADDB_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED

#define XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPADDB_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPADDB_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPADDB_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPADDB_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED

#define XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED

#define XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPADDD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPADDD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPADDD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPADDD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPADDD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPADDD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPADDD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPADDD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPADDQ_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPADDQ_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPADDQ_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPADDQ_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPADDQ_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPADDQ_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPADDQ_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPADDQ_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPADDSB_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPADDSB_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPADDSB_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPADDSB_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED

#define XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED

#define XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPADDSB_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPADDSB_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPADDSB_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPADDSB_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED

#define XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPADDSW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPADDSW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPADDSW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPADDSW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED

#define XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED

#define XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPADDSW_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPADDSW_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPADDSW_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPADDSW_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED

#define XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPADDUSB_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPADDUSB_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPADDUSB_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPADDUSB_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED

#define XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPADDUSB_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPADDUSB_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPADDUSB_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPADDUSB_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED

#define XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED

#define XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPADDUSW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPADDUSW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPADDUSW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPADDUSW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPADDUSW_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPADDUSW_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPADDUSW_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPADDUSW_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPADDW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPADDW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPADDW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPADDW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPADDW_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPADDW_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPADDW_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPADDW_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb_DEFINED

#define XED_IFORM_VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPAND_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPAND_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPAND_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPAND_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPAND_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPAND_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPAND_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPAND_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPANDN_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPANDN_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPANDN_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPANDN_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPANDN_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPANDN_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPANDN_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPANDN_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPAVGB_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPAVGB_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPAVGB_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPAVGB_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED

#define XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPAVGB_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPAVGB_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPAVGB_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPAVGB_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED

#define XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED

#define XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPAVGW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPAVGW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPAVGW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPAVGW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPAVGW_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPAVGW_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPAVGW_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPAVGW_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED

#define XED_IFORM_VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED

#define XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED

#define XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED

#define XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED

#define XED_IFORM_VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb_DEFINED

#define XED_IFORM_VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPBROADCASTB_XMMdq_MEMb_DEFINED

#define XED_IFORM_VPBROADCASTB_XMMdq_MEMb_DEFINED   1

◆ XED_IFORM_VPBROADCASTB_XMMdq_XMMb_DEFINED

#define XED_IFORM_VPBROADCASTB_XMMdq_XMMb_DEFINED   1

◆ XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTB_YMMqq_MEMb_DEFINED

#define XED_IFORM_VPBROADCASTB_YMMqq_MEMb_DEFINED   1

◆ XED_IFORM_VPBROADCASTB_YMMqq_XMMb_DEFINED

#define XED_IFORM_VPBROADCASTB_YMMqq_XMMb_DEFINED   1

◆ XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTD_XMMdq_MEMd_DEFINED

#define XED_IFORM_VPBROADCASTD_XMMdq_MEMd_DEFINED   1

◆ XED_IFORM_VPBROADCASTD_XMMdq_XMMd_DEFINED

#define XED_IFORM_VPBROADCASTD_XMMdq_XMMd_DEFINED   1

◆ XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTD_YMMqq_MEMd_DEFINED

#define XED_IFORM_VPBROADCASTD_YMMqq_MEMd_DEFINED   1

◆ XED_IFORM_VPBROADCASTD_YMMqq_XMMd_DEFINED

#define XED_IFORM_VPBROADCASTD_YMMqq_XMMd_DEFINED   1

◆ XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD_DEFINED

#define XED_IFORM_VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD_DEFINED   1

◆ XED_IFORM_VPBROADCASTMW2D_XMMu32_MASKu32_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTMW2D_XMMu32_MASKu32_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTMW2D_YMMu32_MASKu32_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTMW2D_YMMu32_MASKu32_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD_DEFINED

#define XED_IFORM_VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD_DEFINED   1

◆ XED_IFORM_VPBROADCASTQ_XMMdq_MEMq_DEFINED

#define XED_IFORM_VPBROADCASTQ_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_VPBROADCASTQ_XMMdq_XMMq_DEFINED

#define XED_IFORM_VPBROADCASTQ_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTQ_YMMqq_MEMq_DEFINED

#define XED_IFORM_VPBROADCASTQ_YMMqq_MEMq_DEFINED   1

◆ XED_IFORM_VPBROADCASTQ_YMMqq_XMMq_DEFINED

#define XED_IFORM_VPBROADCASTQ_YMMqq_XMMq_DEFINED   1

◆ XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTW_XMMdq_MEMw_DEFINED

#define XED_IFORM_VPBROADCASTW_XMMdq_MEMw_DEFINED   1

◆ XED_IFORM_VPBROADCASTW_XMMdq_XMMw_DEFINED

#define XED_IFORM_VPBROADCASTW_XMMdq_XMMw_DEFINED   1

◆ XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTW_YMMqq_MEMw_DEFINED

#define XED_IFORM_VPBROADCASTW_YMMqq_MEMw_DEFINED   1

◆ XED_IFORM_VPBROADCASTW_YMMqq_XMMw_DEFINED

#define XED_IFORM_VPBROADCASTW_YMMqq_XMMw_DEFINED   1

◆ XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_DEFINED

#define XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_DEFINED   1

◆ XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_DEFINED

#define XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_DEFINED   1

◆ XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED

#define XED_IFORM_VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED

#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED

#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED

#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPEQB_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPCMPEQB_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPCMPEQB_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPCMPEQB_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPCMPEQB_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPCMPEQB_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPCMPEQB_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPCMPEQB_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPEQD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPCMPEQD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPCMPEQD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPCMPEQD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPCMPEQD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPCMPEQD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPCMPEQD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPCMPEQD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPEQW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPCMPEQW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPCMPEQW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPCMPEQW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPCMPEQW_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPCMPEQW_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPCMPEQW_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPCMPEQW_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPCMPESTRI64_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPCMPESTRI64_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCMPESTRI64_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPCMPESTRI64_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCMPESTRM64_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPCMPESTRM64_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCMPESTRM64_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPCMPESTRM64_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED

#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED

#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED

#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPGTB_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPCMPGTB_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPCMPGTB_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPCMPGTB_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPCMPGTB_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPCMPGTB_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPCMPGTB_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPCMPGTB_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED

#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED

#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED

#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED

#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED

#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED

#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPGTD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPCMPGTD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPCMPGTD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPCMPGTD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPCMPGTD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPCMPGTD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPCMPGTD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPCMPGTD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512_DEFINED

#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512_DEFINED

#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512_DEFINED

#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512_DEFINED

#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512_DEFINED

#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512_DEFINED

#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPGTW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPCMPGTW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPCMPGTW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPCMPGTW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPCMPGTW_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPCMPGTW_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPCMPGTW_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPCMPGTW_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPCMPISTRI64_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPCMPISTRI64_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCMPISTRI64_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPCMPISTRI64_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCMPISTRM_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPCMPISTRM_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCMPISTRM_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPCMPISTRM_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPCOMB_XMMdq_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPCOMB_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCOMB_XMMdq_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPCOMB_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCOMD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPCOMD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCOMD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPCOMD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512_DEFINED

#define XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512_DEFINED

#define XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512_DEFINED

#define XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED

#define XED_IFORM_VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED

#define XED_IFORM_VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED

#define XED_IFORM_VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCOMW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPCOMW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCOMW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPCOMW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD_DEFINED

#define XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD_DEFINED   1

◆ XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD_DEFINED

#define XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD_DEFINED   1

◆ XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD_DEFINED

#define XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD_DEFINED   1

◆ XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD_DEFINED

#define XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD_DEFINED   1

◆ XED_IFORM_VPDPBSSD_XMMi32_MASKmskw_XMM4i8_MEM4i8_AVX512_DEFINED

#define XED_IFORM_VPDPBSSD_XMMi32_MASKmskw_XMM4i8_MEM4i8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBSSD_XMMi32_MASKmskw_XMM4i8_XMM4i8_AVX512_DEFINED

#define XED_IFORM_VPDPBSSD_XMMi32_MASKmskw_XMM4i8_XMM4i8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBSSD_XMMi32_XMM4i8_MEM4i8_DEFINED

#define XED_IFORM_VPDPBSSD_XMMi32_XMM4i8_MEM4i8_DEFINED   1

◆ XED_IFORM_VPDPBSSD_XMMi32_XMM4i8_XMM4i8_DEFINED

#define XED_IFORM_VPDPBSSD_XMMi32_XMM4i8_XMM4i8_DEFINED   1

◆ XED_IFORM_VPDPBSSD_YMMi32_MASKmskw_YMM4i8_MEM4i8_AVX512_DEFINED

#define XED_IFORM_VPDPBSSD_YMMi32_MASKmskw_YMM4i8_MEM4i8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBSSD_YMMi32_MASKmskw_YMM4i8_YMM4i8_AVX512_DEFINED

#define XED_IFORM_VPDPBSSD_YMMi32_MASKmskw_YMM4i8_YMM4i8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBSSD_YMMi32_YMM4i8_MEM4i8_DEFINED

#define XED_IFORM_VPDPBSSD_YMMi32_YMM4i8_MEM4i8_DEFINED   1

◆ XED_IFORM_VPDPBSSD_YMMi32_YMM4i8_YMM4i8_DEFINED

#define XED_IFORM_VPDPBSSD_YMMi32_YMM4i8_YMM4i8_DEFINED   1

◆ XED_IFORM_VPDPBSSD_ZMMi32_MASKmskw_ZMM4i8_MEM4i8_AVX512_DEFINED

#define XED_IFORM_VPDPBSSD_ZMMi32_MASKmskw_ZMM4i8_MEM4i8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBSSD_ZMMi32_MASKmskw_ZMM4i8_ZMM4i8_AVX512_DEFINED

#define XED_IFORM_VPDPBSSD_ZMMi32_MASKmskw_ZMM4i8_ZMM4i8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBSSDS_XMMi32_MASKmskw_XMM4i8_MEM4i8_AVX512_DEFINED

#define XED_IFORM_VPDPBSSDS_XMMi32_MASKmskw_XMM4i8_MEM4i8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBSSDS_XMMi32_MASKmskw_XMM4i8_XMM4i8_AVX512_DEFINED

#define XED_IFORM_VPDPBSSDS_XMMi32_MASKmskw_XMM4i8_XMM4i8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBSSDS_XMMi32_XMM4i8_MEM4i8_DEFINED

#define XED_IFORM_VPDPBSSDS_XMMi32_XMM4i8_MEM4i8_DEFINED   1

◆ XED_IFORM_VPDPBSSDS_XMMi32_XMM4i8_XMM4i8_DEFINED

#define XED_IFORM_VPDPBSSDS_XMMi32_XMM4i8_XMM4i8_DEFINED   1

◆ XED_IFORM_VPDPBSSDS_YMMi32_MASKmskw_YMM4i8_MEM4i8_AVX512_DEFINED

#define XED_IFORM_VPDPBSSDS_YMMi32_MASKmskw_YMM4i8_MEM4i8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBSSDS_YMMi32_MASKmskw_YMM4i8_YMM4i8_AVX512_DEFINED

#define XED_IFORM_VPDPBSSDS_YMMi32_MASKmskw_YMM4i8_YMM4i8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBSSDS_YMMi32_YMM4i8_MEM4i8_DEFINED

#define XED_IFORM_VPDPBSSDS_YMMi32_YMM4i8_MEM4i8_DEFINED   1

◆ XED_IFORM_VPDPBSSDS_YMMi32_YMM4i8_YMM4i8_DEFINED

#define XED_IFORM_VPDPBSSDS_YMMi32_YMM4i8_YMM4i8_DEFINED   1

◆ XED_IFORM_VPDPBSSDS_ZMMi32_MASKmskw_ZMM4i8_MEM4i8_AVX512_DEFINED

#define XED_IFORM_VPDPBSSDS_ZMMi32_MASKmskw_ZMM4i8_MEM4i8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBSSDS_ZMMi32_MASKmskw_ZMM4i8_ZMM4i8_AVX512_DEFINED

#define XED_IFORM_VPDPBSSDS_ZMMi32_MASKmskw_ZMM4i8_ZMM4i8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBSUD_XMMi32_MASKmskw_XMM4i8_MEM4u8_AVX512_DEFINED

#define XED_IFORM_VPDPBSUD_XMMi32_MASKmskw_XMM4i8_MEM4u8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBSUD_XMMi32_MASKmskw_XMM4i8_XMM4u8_AVX512_DEFINED

#define XED_IFORM_VPDPBSUD_XMMi32_MASKmskw_XMM4i8_XMM4u8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBSUD_XMMi32_XMM4i8_MEM4u8_DEFINED

#define XED_IFORM_VPDPBSUD_XMMi32_XMM4i8_MEM4u8_DEFINED   1

◆ XED_IFORM_VPDPBSUD_XMMi32_XMM4i8_XMM4u8_DEFINED

#define XED_IFORM_VPDPBSUD_XMMi32_XMM4i8_XMM4u8_DEFINED   1

◆ XED_IFORM_VPDPBSUD_YMMi32_MASKmskw_YMM4i8_MEM4u8_AVX512_DEFINED

#define XED_IFORM_VPDPBSUD_YMMi32_MASKmskw_YMM4i8_MEM4u8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBSUD_YMMi32_MASKmskw_YMM4i8_YMM4u8_AVX512_DEFINED

#define XED_IFORM_VPDPBSUD_YMMi32_MASKmskw_YMM4i8_YMM4u8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBSUD_YMMi32_YMM4i8_MEM4u8_DEFINED

#define XED_IFORM_VPDPBSUD_YMMi32_YMM4i8_MEM4u8_DEFINED   1

◆ XED_IFORM_VPDPBSUD_YMMi32_YMM4i8_YMM4u8_DEFINED

#define XED_IFORM_VPDPBSUD_YMMi32_YMM4i8_YMM4u8_DEFINED   1

◆ XED_IFORM_VPDPBSUD_ZMMi32_MASKmskw_ZMM4i8_MEM4u8_AVX512_DEFINED

#define XED_IFORM_VPDPBSUD_ZMMi32_MASKmskw_ZMM4i8_MEM4u8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBSUD_ZMMi32_MASKmskw_ZMM4i8_ZMM4u8_AVX512_DEFINED

#define XED_IFORM_VPDPBSUD_ZMMi32_MASKmskw_ZMM4i8_ZMM4u8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBSUDS_XMMi32_MASKmskw_XMM4i8_MEM4u8_AVX512_DEFINED

#define XED_IFORM_VPDPBSUDS_XMMi32_MASKmskw_XMM4i8_MEM4u8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBSUDS_XMMi32_MASKmskw_XMM4i8_XMM4u8_AVX512_DEFINED

#define XED_IFORM_VPDPBSUDS_XMMi32_MASKmskw_XMM4i8_XMM4u8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBSUDS_XMMi32_XMM4i8_MEM4u8_DEFINED

#define XED_IFORM_VPDPBSUDS_XMMi32_XMM4i8_MEM4u8_DEFINED   1

◆ XED_IFORM_VPDPBSUDS_XMMi32_XMM4i8_XMM4u8_DEFINED

#define XED_IFORM_VPDPBSUDS_XMMi32_XMM4i8_XMM4u8_DEFINED   1

◆ XED_IFORM_VPDPBSUDS_YMMi32_MASKmskw_YMM4i8_MEM4u8_AVX512_DEFINED

#define XED_IFORM_VPDPBSUDS_YMMi32_MASKmskw_YMM4i8_MEM4u8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBSUDS_YMMi32_MASKmskw_YMM4i8_YMM4u8_AVX512_DEFINED

#define XED_IFORM_VPDPBSUDS_YMMi32_MASKmskw_YMM4i8_YMM4u8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBSUDS_YMMi32_YMM4i8_MEM4u8_DEFINED

#define XED_IFORM_VPDPBSUDS_YMMi32_YMM4i8_MEM4u8_DEFINED   1

◆ XED_IFORM_VPDPBSUDS_YMMi32_YMM4i8_YMM4u8_DEFINED

#define XED_IFORM_VPDPBSUDS_YMMi32_YMM4i8_YMM4u8_DEFINED   1

◆ XED_IFORM_VPDPBSUDS_ZMMi32_MASKmskw_ZMM4i8_MEM4u8_AVX512_DEFINED

#define XED_IFORM_VPDPBSUDS_ZMMi32_MASKmskw_ZMM4i8_MEM4u8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBSUDS_ZMMi32_MASKmskw_ZMM4i8_ZMM4u8_AVX512_DEFINED

#define XED_IFORM_VPDPBSUDS_ZMMi32_MASKmskw_ZMM4i8_ZMM4u8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBUSD_XMMi32_XMMu32_MEMu32_DEFINED

#define XED_IFORM_VPDPBUSD_XMMi32_XMMu32_MEMu32_DEFINED   1

◆ XED_IFORM_VPDPBUSD_XMMi32_XMMu32_XMMu32_DEFINED

#define XED_IFORM_VPDPBUSD_XMMi32_XMMu32_XMMu32_DEFINED   1

◆ XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBUSD_YMMi32_YMMu32_MEMu32_DEFINED

#define XED_IFORM_VPDPBUSD_YMMi32_YMMu32_MEMu32_DEFINED   1

◆ XED_IFORM_VPDPBUSD_YMMi32_YMMu32_YMMu32_DEFINED

#define XED_IFORM_VPDPBUSD_YMMi32_YMMu32_YMMu32_DEFINED   1

◆ XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_MEMu32_DEFINED

#define XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_MEMu32_DEFINED   1

◆ XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_XMMu32_DEFINED

#define XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_XMMu32_DEFINED   1

◆ XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_MEMu32_DEFINED

#define XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_MEMu32_DEFINED   1

◆ XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_YMMu32_DEFINED

#define XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_YMMu32_DEFINED   1

◆ XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBUUD_XMMu32_MASKmskw_XMM4u8_MEM4u8_AVX512_DEFINED

#define XED_IFORM_VPDPBUUD_XMMu32_MASKmskw_XMM4u8_MEM4u8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBUUD_XMMu32_MASKmskw_XMM4u8_XMM4u8_AVX512_DEFINED

#define XED_IFORM_VPDPBUUD_XMMu32_MASKmskw_XMM4u8_XMM4u8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBUUD_XMMu32_XMM4u8_MEM4u8_DEFINED

#define XED_IFORM_VPDPBUUD_XMMu32_XMM4u8_MEM4u8_DEFINED   1

◆ XED_IFORM_VPDPBUUD_XMMu32_XMM4u8_XMM4u8_DEFINED

#define XED_IFORM_VPDPBUUD_XMMu32_XMM4u8_XMM4u8_DEFINED   1

◆ XED_IFORM_VPDPBUUD_YMMu32_MASKmskw_YMM4u8_MEM4u8_AVX512_DEFINED

#define XED_IFORM_VPDPBUUD_YMMu32_MASKmskw_YMM4u8_MEM4u8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBUUD_YMMu32_MASKmskw_YMM4u8_YMM4u8_AVX512_DEFINED

#define XED_IFORM_VPDPBUUD_YMMu32_MASKmskw_YMM4u8_YMM4u8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBUUD_YMMu32_YMM4u8_MEM4u8_DEFINED

#define XED_IFORM_VPDPBUUD_YMMu32_YMM4u8_MEM4u8_DEFINED   1

◆ XED_IFORM_VPDPBUUD_YMMu32_YMM4u8_YMM4u8_DEFINED

#define XED_IFORM_VPDPBUUD_YMMu32_YMM4u8_YMM4u8_DEFINED   1

◆ XED_IFORM_VPDPBUUD_ZMMu32_MASKmskw_ZMM4u8_MEM4u8_AVX512_DEFINED

#define XED_IFORM_VPDPBUUD_ZMMu32_MASKmskw_ZMM4u8_MEM4u8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBUUD_ZMMu32_MASKmskw_ZMM4u8_ZMM4u8_AVX512_DEFINED

#define XED_IFORM_VPDPBUUD_ZMMu32_MASKmskw_ZMM4u8_ZMM4u8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBUUDS_XMMu32_MASKmskw_XMM4u8_MEM4u8_AVX512_DEFINED

#define XED_IFORM_VPDPBUUDS_XMMu32_MASKmskw_XMM4u8_MEM4u8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBUUDS_XMMu32_MASKmskw_XMM4u8_XMM4u8_AVX512_DEFINED

#define XED_IFORM_VPDPBUUDS_XMMu32_MASKmskw_XMM4u8_XMM4u8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBUUDS_XMMu32_XMM4u8_MEM4u8_DEFINED

#define XED_IFORM_VPDPBUUDS_XMMu32_XMM4u8_MEM4u8_DEFINED   1

◆ XED_IFORM_VPDPBUUDS_XMMu32_XMM4u8_XMM4u8_DEFINED

#define XED_IFORM_VPDPBUUDS_XMMu32_XMM4u8_XMM4u8_DEFINED   1

◆ XED_IFORM_VPDPBUUDS_YMMu32_MASKmskw_YMM4u8_MEM4u8_AVX512_DEFINED

#define XED_IFORM_VPDPBUUDS_YMMu32_MASKmskw_YMM4u8_MEM4u8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBUUDS_YMMu32_MASKmskw_YMM4u8_YMM4u8_AVX512_DEFINED

#define XED_IFORM_VPDPBUUDS_YMMu32_MASKmskw_YMM4u8_YMM4u8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBUUDS_YMMu32_YMM4u8_MEM4u8_DEFINED

#define XED_IFORM_VPDPBUUDS_YMMu32_YMM4u8_MEM4u8_DEFINED   1

◆ XED_IFORM_VPDPBUUDS_YMMu32_YMM4u8_YMM4u8_DEFINED

#define XED_IFORM_VPDPBUUDS_YMMu32_YMM4u8_YMM4u8_DEFINED   1

◆ XED_IFORM_VPDPBUUDS_ZMMu32_MASKmskw_ZMM4u8_MEM4u8_AVX512_DEFINED

#define XED_IFORM_VPDPBUUDS_ZMMu32_MASKmskw_ZMM4u8_MEM4u8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPBUUDS_ZMMu32_MASKmskw_ZMM4u8_ZMM4u8_AVX512_DEFINED

#define XED_IFORM_VPDPBUUDS_ZMMu32_MASKmskw_ZMM4u8_ZMM4u8_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWSSD_XMMi32_XMMu32_MEMu32_DEFINED

#define XED_IFORM_VPDPWSSD_XMMi32_XMMu32_MEMu32_DEFINED   1

◆ XED_IFORM_VPDPWSSD_XMMi32_XMMu32_XMMu32_DEFINED

#define XED_IFORM_VPDPWSSD_XMMi32_XMMu32_XMMu32_DEFINED   1

◆ XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWSSD_YMMi32_YMMu32_MEMu32_DEFINED

#define XED_IFORM_VPDPWSSD_YMMi32_YMMu32_MEMu32_DEFINED   1

◆ XED_IFORM_VPDPWSSD_YMMi32_YMMu32_YMMu32_DEFINED

#define XED_IFORM_VPDPWSSD_YMMi32_YMMu32_YMMu32_DEFINED   1

◆ XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_MEMu32_DEFINED

#define XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_MEMu32_DEFINED   1

◆ XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_XMMu32_DEFINED

#define XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_XMMu32_DEFINED   1

◆ XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_MEMu32_DEFINED

#define XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_MEMu32_DEFINED   1

◆ XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_YMMu32_DEFINED

#define XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_YMMu32_DEFINED   1

◆ XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWSUD_XMMi32_MASKmskw_XMM2i16_MEM2u16_AVX512_DEFINED

#define XED_IFORM_VPDPWSUD_XMMi32_MASKmskw_XMM2i16_MEM2u16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWSUD_XMMi32_MASKmskw_XMM2i16_XMM2u16_AVX512_DEFINED

#define XED_IFORM_VPDPWSUD_XMMi32_MASKmskw_XMM2i16_XMM2u16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWSUD_XMMi32_XMM2i16_MEM2u16_DEFINED

#define XED_IFORM_VPDPWSUD_XMMi32_XMM2i16_MEM2u16_DEFINED   1

◆ XED_IFORM_VPDPWSUD_XMMi32_XMM2i16_XMM2u16_DEFINED

#define XED_IFORM_VPDPWSUD_XMMi32_XMM2i16_XMM2u16_DEFINED   1

◆ XED_IFORM_VPDPWSUD_YMMi32_MASKmskw_YMM2i16_MEM2u16_AVX512_DEFINED

#define XED_IFORM_VPDPWSUD_YMMi32_MASKmskw_YMM2i16_MEM2u16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWSUD_YMMi32_MASKmskw_YMM2i16_YMM2u16_AVX512_DEFINED

#define XED_IFORM_VPDPWSUD_YMMi32_MASKmskw_YMM2i16_YMM2u16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWSUD_YMMi32_YMM2i16_MEM2u16_DEFINED

#define XED_IFORM_VPDPWSUD_YMMi32_YMM2i16_MEM2u16_DEFINED   1

◆ XED_IFORM_VPDPWSUD_YMMi32_YMM2i16_YMM2u16_DEFINED

#define XED_IFORM_VPDPWSUD_YMMi32_YMM2i16_YMM2u16_DEFINED   1

◆ XED_IFORM_VPDPWSUD_ZMMi32_MASKmskw_ZMM2i16_MEM2u16_AVX512_DEFINED

#define XED_IFORM_VPDPWSUD_ZMMi32_MASKmskw_ZMM2i16_MEM2u16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWSUD_ZMMi32_MASKmskw_ZMM2i16_ZMM2u16_AVX512_DEFINED

#define XED_IFORM_VPDPWSUD_ZMMi32_MASKmskw_ZMM2i16_ZMM2u16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWSUDS_XMMi32_MASKmskw_XMM2i16_MEM2u16_AVX512_DEFINED

#define XED_IFORM_VPDPWSUDS_XMMi32_MASKmskw_XMM2i16_MEM2u16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWSUDS_XMMi32_MASKmskw_XMM2i16_XMM2u16_AVX512_DEFINED

#define XED_IFORM_VPDPWSUDS_XMMi32_MASKmskw_XMM2i16_XMM2u16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWSUDS_XMMi32_XMM2i16_MEM2u16_DEFINED

#define XED_IFORM_VPDPWSUDS_XMMi32_XMM2i16_MEM2u16_DEFINED   1

◆ XED_IFORM_VPDPWSUDS_XMMi32_XMM2i16_XMM2u16_DEFINED

#define XED_IFORM_VPDPWSUDS_XMMi32_XMM2i16_XMM2u16_DEFINED   1

◆ XED_IFORM_VPDPWSUDS_YMMi32_MASKmskw_YMM2i16_MEM2u16_AVX512_DEFINED

#define XED_IFORM_VPDPWSUDS_YMMi32_MASKmskw_YMM2i16_MEM2u16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWSUDS_YMMi32_MASKmskw_YMM2i16_YMM2u16_AVX512_DEFINED

#define XED_IFORM_VPDPWSUDS_YMMi32_MASKmskw_YMM2i16_YMM2u16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWSUDS_YMMi32_YMM2i16_MEM2u16_DEFINED

#define XED_IFORM_VPDPWSUDS_YMMi32_YMM2i16_MEM2u16_DEFINED   1

◆ XED_IFORM_VPDPWSUDS_YMMi32_YMM2i16_YMM2u16_DEFINED

#define XED_IFORM_VPDPWSUDS_YMMi32_YMM2i16_YMM2u16_DEFINED   1

◆ XED_IFORM_VPDPWSUDS_ZMMi32_MASKmskw_ZMM2i16_MEM2u16_AVX512_DEFINED

#define XED_IFORM_VPDPWSUDS_ZMMi32_MASKmskw_ZMM2i16_MEM2u16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWSUDS_ZMMi32_MASKmskw_ZMM2i16_ZMM2u16_AVX512_DEFINED

#define XED_IFORM_VPDPWSUDS_ZMMi32_MASKmskw_ZMM2i16_ZMM2u16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWUSD_XMMi32_MASKmskw_XMM2u16_MEM2i16_AVX512_DEFINED

#define XED_IFORM_VPDPWUSD_XMMi32_MASKmskw_XMM2u16_MEM2i16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWUSD_XMMi32_MASKmskw_XMM2u16_XMM2i16_AVX512_DEFINED

#define XED_IFORM_VPDPWUSD_XMMi32_MASKmskw_XMM2u16_XMM2i16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWUSD_XMMi32_XMM2u16_MEM2i16_DEFINED

#define XED_IFORM_VPDPWUSD_XMMi32_XMM2u16_MEM2i16_DEFINED   1

◆ XED_IFORM_VPDPWUSD_XMMi32_XMM2u16_XMM2i16_DEFINED

#define XED_IFORM_VPDPWUSD_XMMi32_XMM2u16_XMM2i16_DEFINED   1

◆ XED_IFORM_VPDPWUSD_YMMi32_MASKmskw_YMM2u16_MEM2i16_AVX512_DEFINED

#define XED_IFORM_VPDPWUSD_YMMi32_MASKmskw_YMM2u16_MEM2i16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWUSD_YMMi32_MASKmskw_YMM2u16_YMM2i16_AVX512_DEFINED

#define XED_IFORM_VPDPWUSD_YMMi32_MASKmskw_YMM2u16_YMM2i16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWUSD_YMMi32_YMM2u16_MEM2i16_DEFINED

#define XED_IFORM_VPDPWUSD_YMMi32_YMM2u16_MEM2i16_DEFINED   1

◆ XED_IFORM_VPDPWUSD_YMMi32_YMM2u16_YMM2i16_DEFINED

#define XED_IFORM_VPDPWUSD_YMMi32_YMM2u16_YMM2i16_DEFINED   1

◆ XED_IFORM_VPDPWUSD_ZMMi32_MASKmskw_ZMM2u16_MEM2i16_AVX512_DEFINED

#define XED_IFORM_VPDPWUSD_ZMMi32_MASKmskw_ZMM2u16_MEM2i16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWUSD_ZMMi32_MASKmskw_ZMM2u16_ZMM2i16_AVX512_DEFINED

#define XED_IFORM_VPDPWUSD_ZMMi32_MASKmskw_ZMM2u16_ZMM2i16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWUSDS_XMMi32_MASKmskw_XMM2u16_MEM2i16_AVX512_DEFINED

#define XED_IFORM_VPDPWUSDS_XMMi32_MASKmskw_XMM2u16_MEM2i16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWUSDS_XMMi32_MASKmskw_XMM2u16_XMM2i16_AVX512_DEFINED

#define XED_IFORM_VPDPWUSDS_XMMi32_MASKmskw_XMM2u16_XMM2i16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWUSDS_XMMi32_XMM2u16_MEM2i16_DEFINED

#define XED_IFORM_VPDPWUSDS_XMMi32_XMM2u16_MEM2i16_DEFINED   1

◆ XED_IFORM_VPDPWUSDS_XMMi32_XMM2u16_XMM2i16_DEFINED

#define XED_IFORM_VPDPWUSDS_XMMi32_XMM2u16_XMM2i16_DEFINED   1

◆ XED_IFORM_VPDPWUSDS_YMMi32_MASKmskw_YMM2u16_MEM2i16_AVX512_DEFINED

#define XED_IFORM_VPDPWUSDS_YMMi32_MASKmskw_YMM2u16_MEM2i16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWUSDS_YMMi32_MASKmskw_YMM2u16_YMM2i16_AVX512_DEFINED

#define XED_IFORM_VPDPWUSDS_YMMi32_MASKmskw_YMM2u16_YMM2i16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWUSDS_YMMi32_YMM2u16_MEM2i16_DEFINED

#define XED_IFORM_VPDPWUSDS_YMMi32_YMM2u16_MEM2i16_DEFINED   1

◆ XED_IFORM_VPDPWUSDS_YMMi32_YMM2u16_YMM2i16_DEFINED

#define XED_IFORM_VPDPWUSDS_YMMi32_YMM2u16_YMM2i16_DEFINED   1

◆ XED_IFORM_VPDPWUSDS_ZMMi32_MASKmskw_ZMM2u16_MEM2i16_AVX512_DEFINED

#define XED_IFORM_VPDPWUSDS_ZMMi32_MASKmskw_ZMM2u16_MEM2i16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWUSDS_ZMMi32_MASKmskw_ZMM2u16_ZMM2i16_AVX512_DEFINED

#define XED_IFORM_VPDPWUSDS_ZMMi32_MASKmskw_ZMM2u16_ZMM2i16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWUUD_XMMu32_MASKmskw_XMM2u16_MEM2u16_AVX512_DEFINED

#define XED_IFORM_VPDPWUUD_XMMu32_MASKmskw_XMM2u16_MEM2u16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWUUD_XMMu32_MASKmskw_XMM2u16_XMM2u16_AVX512_DEFINED

#define XED_IFORM_VPDPWUUD_XMMu32_MASKmskw_XMM2u16_XMM2u16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWUUD_XMMu32_XMM2u16_MEM2u16_DEFINED

#define XED_IFORM_VPDPWUUD_XMMu32_XMM2u16_MEM2u16_DEFINED   1

◆ XED_IFORM_VPDPWUUD_XMMu32_XMM2u16_XMM2u16_DEFINED

#define XED_IFORM_VPDPWUUD_XMMu32_XMM2u16_XMM2u16_DEFINED   1

◆ XED_IFORM_VPDPWUUD_YMMu32_MASKmskw_YMM2u16_MEM2u16_AVX512_DEFINED

#define XED_IFORM_VPDPWUUD_YMMu32_MASKmskw_YMM2u16_MEM2u16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWUUD_YMMu32_MASKmskw_YMM2u16_YMM2u16_AVX512_DEFINED

#define XED_IFORM_VPDPWUUD_YMMu32_MASKmskw_YMM2u16_YMM2u16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWUUD_YMMu32_YMM2u16_MEM2u16_DEFINED

#define XED_IFORM_VPDPWUUD_YMMu32_YMM2u16_MEM2u16_DEFINED   1

◆ XED_IFORM_VPDPWUUD_YMMu32_YMM2u16_YMM2u16_DEFINED

#define XED_IFORM_VPDPWUUD_YMMu32_YMM2u16_YMM2u16_DEFINED   1

◆ XED_IFORM_VPDPWUUD_ZMMu32_MASKmskw_ZMM2u16_MEM2u16_AVX512_DEFINED

#define XED_IFORM_VPDPWUUD_ZMMu32_MASKmskw_ZMM2u16_MEM2u16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWUUD_ZMMu32_MASKmskw_ZMM2u16_ZMM2u16_AVX512_DEFINED

#define XED_IFORM_VPDPWUUD_ZMMu32_MASKmskw_ZMM2u16_ZMM2u16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWUUDS_XMMu32_MASKmskw_XMM2u16_MEM2u16_AVX512_DEFINED

#define XED_IFORM_VPDPWUUDS_XMMu32_MASKmskw_XMM2u16_MEM2u16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWUUDS_XMMu32_MASKmskw_XMM2u16_XMM2u16_AVX512_DEFINED

#define XED_IFORM_VPDPWUUDS_XMMu32_MASKmskw_XMM2u16_XMM2u16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWUUDS_XMMu32_XMM2u16_MEM2u16_DEFINED

#define XED_IFORM_VPDPWUUDS_XMMu32_XMM2u16_MEM2u16_DEFINED   1

◆ XED_IFORM_VPDPWUUDS_XMMu32_XMM2u16_XMM2u16_DEFINED

#define XED_IFORM_VPDPWUUDS_XMMu32_XMM2u16_XMM2u16_DEFINED   1

◆ XED_IFORM_VPDPWUUDS_YMMu32_MASKmskw_YMM2u16_MEM2u16_AVX512_DEFINED

#define XED_IFORM_VPDPWUUDS_YMMu32_MASKmskw_YMM2u16_MEM2u16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWUUDS_YMMu32_MASKmskw_YMM2u16_YMM2u16_AVX512_DEFINED

#define XED_IFORM_VPDPWUUDS_YMMu32_MASKmskw_YMM2u16_YMM2u16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWUUDS_YMMu32_YMM2u16_MEM2u16_DEFINED

#define XED_IFORM_VPDPWUUDS_YMMu32_YMM2u16_MEM2u16_DEFINED   1

◆ XED_IFORM_VPDPWUUDS_YMMu32_YMM2u16_YMM2u16_DEFINED

#define XED_IFORM_VPDPWUUDS_YMMu32_YMM2u16_YMM2u16_DEFINED   1

◆ XED_IFORM_VPDPWUUDS_ZMMu32_MASKmskw_ZMM2u16_MEM2u16_AVX512_DEFINED

#define XED_IFORM_VPDPWUUDS_ZMMu32_MASKmskw_ZMM2u16_MEM2u16_AVX512_DEFINED   1

◆ XED_IFORM_VPDPWUUDS_ZMMu32_MASKmskw_ZMM2u16_ZMM2u16_AVX512_DEFINED

#define XED_IFORM_VPDPWUUDS_ZMMu32_MASKmskw_ZMM2u16_ZMM2u16_AVX512_DEFINED   1

◆ XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb_DEFINED

#define XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb_DEFINED

#define XED_IFORM_VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED

#define XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED

#define XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED

#define XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPERMD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPERMD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPERMD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED

#define XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED

#define XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED

#define XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb_DEFINED

#define XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb_DEFINED

#define XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPERMILPD_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPERMILPD_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPERMILPD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPERMILPD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPERMILPD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPERMILPD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMILPD_YMMqq_MEMqq_IMMb_DEFINED

#define XED_IFORM_VPERMILPD_YMMqq_MEMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPERMILPD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPERMILPD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPERMILPD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPERMILPD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMILPS_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPERMILPS_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPERMILPS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPERMILPS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPERMILPS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPERMILPS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMILPS_YMMqq_MEMqq_IMMb_DEFINED

#define XED_IFORM_VPERMILPS_YMMqq_MEMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPERMILPS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPERMILPS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPERMILPS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPERMILPS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMPD_YMMqq_MEMqq_IMMb_DEFINED

#define XED_IFORM_VPERMPD_YMMqq_MEMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMPS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPERMPS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPERMPS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPERMPS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMQ_YMMqq_MEMqq_IMMb_DEFINED

#define XED_IFORM_VPERMQ_YMMqq_MEMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED

#define XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED

#define XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED

#define XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED

#define XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED

#define XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED

#define XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPEXTRB_GPR32d_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPEXTRB_GPR32d_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPEXTRB_MEMb_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPEXTRB_MEMb_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPEXTRB_MEMu8_XMMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPEXTRB_MEMu8_XMMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPEXTRQ_GPR64q_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPEXTRQ_GPR64q_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPEXTRQ_MEMq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPEXTRQ_MEMq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_15_DEFINED

#define XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_15_DEFINED   1

◆ XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_C5_DEFINED

#define XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_C5_DEFINED   1

◆ XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5_DEFINED

#define XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5_DEFINED   1

◆ XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPEXTRW_MEMu16_XMMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPEXTRW_MEMu16_XMMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPEXTRW_MEMw_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPEXTRW_MEMw_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128_DEFINED

#define XED_IFORM_VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VPGATHERDD_XMMu32_MEMd_XMMi32_VL128_DEFINED

#define XED_IFORM_VPGATHERDD_XMMu32_MEMd_XMMi32_VL128_DEFINED   1

◆ XED_IFORM_VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256_DEFINED

#define XED_IFORM_VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VPGATHERDD_YMMu32_MEMd_YMMi32_VL256_DEFINED

#define XED_IFORM_VPGATHERDD_YMMu32_MEMd_YMMi32_VL256_DEFINED   1

◆ XED_IFORM_VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512_DEFINED

#define XED_IFORM_VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128_DEFINED

#define XED_IFORM_VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128_DEFINED

#define XED_IFORM_VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128_DEFINED   1

◆ XED_IFORM_VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256_DEFINED

#define XED_IFORM_VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256_DEFINED

#define XED_IFORM_VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256_DEFINED   1

◆ XED_IFORM_VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512_DEFINED

#define XED_IFORM_VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128_DEFINED

#define XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256_DEFINED

#define XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL128_DEFINED

#define XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL128_DEFINED   1

◆ XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL256_DEFINED

#define XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL256_DEFINED   1

◆ XED_IFORM_VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512_DEFINED

#define XED_IFORM_VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128_DEFINED

#define XED_IFORM_VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128_DEFINED

#define XED_IFORM_VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128_DEFINED   1

◆ XED_IFORM_VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256_DEFINED

#define XED_IFORM_VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256_DEFINED

#define XED_IFORM_VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256_DEFINED   1

◆ XED_IFORM_VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512_DEFINED

#define XED_IFORM_VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VPHADDBD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPHADDBD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPHADDBD_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPHADDBD_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPHADDBQ_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPHADDBQ_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPHADDBQ_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPHADDBQ_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPHADDBW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPHADDBW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPHADDBW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPHADDBW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPHADDD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPHADDD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPHADDD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPHADDD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPHADDD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPHADDD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPHADDD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPHADDD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPHADDDQ_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPHADDDQ_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPHADDDQ_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPHADDDQ_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPHADDSW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPHADDSW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPHADDSW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPHADDSW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPHADDSW_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPHADDSW_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPHADDSW_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPHADDSW_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPHADDUBD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPHADDUBD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPHADDUBD_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPHADDUBD_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPHADDUBQ_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPHADDUBQ_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPHADDUBQ_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPHADDUBQ_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPHADDUBW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPHADDUBW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPHADDUBW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPHADDUBW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPHADDUDQ_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPHADDUDQ_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPHADDUDQ_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPHADDUDQ_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPHADDUWD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPHADDUWD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPHADDUWD_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPHADDUWD_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPHADDUWQ_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPHADDUWQ_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPHADDUWQ_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPHADDUWQ_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPHADDW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPHADDW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPHADDW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPHADDW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPHADDW_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPHADDW_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPHADDW_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPHADDW_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPHADDWD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPHADDWD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPHADDWD_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPHADDWD_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPHADDWQ_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPHADDWQ_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPHADDWQ_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPHADDWQ_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPHMINPOSUW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPHMINPOSUW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPHMINPOSUW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPHMINPOSUW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPHSUBBW_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPHSUBBW_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPHSUBBW_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPHSUBBW_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPHSUBD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPHSUBD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPHSUBD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPHSUBD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPHSUBD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPHSUBD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPHSUBD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPHSUBD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPHSUBDQ_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPHSUBDQ_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPHSUBDQ_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPHSUBDQ_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPHSUBSW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPHSUBSW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPHSUBSW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPHSUBSW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPHSUBSW_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPHSUBSW_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPHSUBSW_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPHSUBSW_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPHSUBW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPHSUBW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPHSUBW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPHSUBW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPHSUBW_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPHSUBW_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPHSUBW_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPHSUBW_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPHSUBWD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPHSUBWD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPHSUBWD_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPHSUBWD_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPINSRB_XMMdq_XMMdq_GPR32d_IMMb_DEFINED

#define XED_IFORM_VPINSRB_XMMdq_XMMdq_GPR32d_IMMb_DEFINED   1

◆ XED_IFORM_VPINSRB_XMMdq_XMMdq_MEMb_IMMb_DEFINED

#define XED_IFORM_VPINSRB_XMMdq_XMMdq_MEMb_IMMb_DEFINED   1

◆ XED_IFORM_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb_DEFINED

#define XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb_DEFINED   1

◆ XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb_DEFINED

#define XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb_DEFINED   1

◆ XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb_DEFINED

#define XED_IFORM_VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb_DEFINED   1

◆ XED_IFORM_VPINSRQ_XMMdq_XMMdq_MEMq_IMMb_DEFINED

#define XED_IFORM_VPINSRQ_XMMdq_XMMdq_MEMq_IMMb_DEFINED   1

◆ XED_IFORM_VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPINSRW_XMMdq_XMMdq_GPR32d_IMMb_DEFINED

#define XED_IFORM_VPINSRW_XMMdq_XMMdq_GPR32d_IMMb_DEFINED   1

◆ XED_IFORM_VPINSRW_XMMdq_XMMdq_MEMw_IMMb_DEFINED

#define XED_IFORM_VPINSRW_XMMdq_XMMdq_MEMw_IMMb_DEFINED   1

◆ XED_IFORM_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD_DEFINED

#define XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD_DEFINED   1

◆ XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD_DEFINED

#define XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD_DEFINED   1

◆ XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD_DEFINED

#define XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD_DEFINED   1

◆ XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD_DEFINED

#define XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD_DEFINED   1

◆ XED_IFORM_VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMADD52HUQ_XMMu64_XMMu64_MEMu64_DEFINED

#define XED_IFORM_VPMADD52HUQ_XMMu64_XMMu64_MEMu64_DEFINED   1

◆ XED_IFORM_VPMADD52HUQ_XMMu64_XMMu64_XMMu64_DEFINED

#define XED_IFORM_VPMADD52HUQ_XMMu64_XMMu64_XMMu64_DEFINED   1

◆ XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMADD52HUQ_YMMu64_YMMu64_MEMu64_DEFINED

#define XED_IFORM_VPMADD52HUQ_YMMu64_YMMu64_MEMu64_DEFINED   1

◆ XED_IFORM_VPMADD52HUQ_YMMu64_YMMu64_YMMu64_DEFINED

#define XED_IFORM_VPMADD52HUQ_YMMu64_YMMu64_YMMu64_DEFINED   1

◆ XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMADD52LUQ_XMMu64_XMMu64_MEMu64_DEFINED

#define XED_IFORM_VPMADD52LUQ_XMMu64_XMMu64_MEMu64_DEFINED   1

◆ XED_IFORM_VPMADD52LUQ_XMMu64_XMMu64_XMMu64_DEFINED

#define XED_IFORM_VPMADD52LUQ_XMMu64_XMMu64_XMMu64_DEFINED   1

◆ XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMADD52LUQ_YMMu64_YMMu64_MEMu64_DEFINED

#define XED_IFORM_VPMADD52LUQ_YMMu64_YMMu64_MEMu64_DEFINED   1

◆ XED_IFORM_VPMADD52LUQ_YMMu64_YMMu64_YMMu64_DEFINED

#define XED_IFORM_VPMADD52LUQ_YMMu64_YMMu64_YMMu64_DEFINED   1

◆ XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED

#define XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED

#define XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED

#define XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMADDWD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPMADDWD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMADDWD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMADDWD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED

#define XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED

#define XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMADDWD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPMADDWD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPMADDWD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPMADDWD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED

#define XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMASKMOVD_MEMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMASKMOVD_MEMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMASKMOVD_MEMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPMASKMOVD_MEMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMASKMOVD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPMASKMOVD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPMASKMOVQ_MEMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMASKMOVQ_MEMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMASKMOVQ_MEMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPMASKMOVQ_MEMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPMASKMOVQ_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPMASKMOVQ_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMASKMOVQ_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPMASKMOVQ_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPMAXSB_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPMAXSB_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMAXSB_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMAXSB_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED

#define XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED

#define XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXSB_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPMAXSB_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPMAXSB_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPMAXSB_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED

#define XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXSD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPMAXSD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMAXSD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMAXSD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED

#define XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED

#define XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED

#define XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED

#define XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXSD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPMAXSD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPMAXSD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPMAXSD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED

#define XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED

#define XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512_DEFINED

#define XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512_DEFINED

#define XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512_DEFINED

#define XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512_DEFINED

#define XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512_DEFINED

#define XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512_DEFINED

#define XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXSW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPMAXSW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMAXSW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMAXSW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED

#define XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED

#define XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXSW_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPMAXSW_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPMAXSW_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPMAXSW_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED

#define XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXUB_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPMAXUB_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMAXUB_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMAXUB_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED

#define XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXUB_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPMAXUB_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPMAXUB_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPMAXUB_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED

#define XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED

#define XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXUD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPMAXUD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMAXUD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMAXUD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXUD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPMAXUD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPMAXUD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPMAXUD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXUW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPMAXUW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMAXUW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMAXUW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXUW_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPMAXUW_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPMAXUW_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPMAXUW_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMINSB_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPMINSB_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMINSB_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMINSB_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED

#define XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED

#define XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMINSB_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPMINSB_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPMINSB_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPMINSB_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED

#define XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMINSD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPMINSD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMINSD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMINSD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED

#define XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED

#define XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED

#define XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED

#define XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMINSD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPMINSD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPMINSD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPMINSD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED

#define XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED

#define XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512_DEFINED

#define XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512_DEFINED

#define XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512_DEFINED

#define XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512_DEFINED

#define XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512_DEFINED

#define XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512_DEFINED

#define XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMINSW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPMINSW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMINSW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMINSW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED

#define XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED

#define XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMINSW_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPMINSW_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPMINSW_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPMINSW_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED

#define XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMINUB_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPMINUB_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMINUB_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMINUB_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED

#define XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPMINUB_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPMINUB_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPMINUB_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPMINUB_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED

#define XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED

#define XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPMINUD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPMINUD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMINUD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMINUD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMINUD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPMINUD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPMINUD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPMINUD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMINUW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPMINUW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMINUW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMINUW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMINUW_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPMINUW_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPMINUW_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPMINUW_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVB2M_MASKmskw_XMMu8_AVX512_DEFINED

#define XED_IFORM_VPMOVB2M_MASKmskw_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVB2M_MASKmskw_YMMu8_AVX512_DEFINED

#define XED_IFORM_VPMOVB2M_MASKmskw_YMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVB2M_MASKmskw_ZMMu8_AVX512_DEFINED

#define XED_IFORM_VPMOVB2M_MASKmskw_ZMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVD2M_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPMOVD2M_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVD2M_MASKmskw_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPMOVD2M_MASKmskw_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVD2M_MASKmskw_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPMOVD2M_MASKmskw_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVM2B_XMMu8_MASKmskw_AVX512_DEFINED

#define XED_IFORM_VPMOVM2B_XMMu8_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVM2B_YMMu8_MASKmskw_AVX512_DEFINED

#define XED_IFORM_VPMOVM2B_YMMu8_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVM2B_ZMMu8_MASKmskw_AVX512_DEFINED

#define XED_IFORM_VPMOVM2B_ZMMu8_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVM2D_XMMu32_MASKmskw_AVX512_DEFINED

#define XED_IFORM_VPMOVM2D_XMMu32_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVM2D_YMMu32_MASKmskw_AVX512_DEFINED

#define XED_IFORM_VPMOVM2D_YMMu32_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVM2D_ZMMu32_MASKmskw_AVX512_DEFINED

#define XED_IFORM_VPMOVM2D_ZMMu32_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVM2Q_XMMu64_MASKmskw_AVX512_DEFINED

#define XED_IFORM_VPMOVM2Q_XMMu64_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVM2Q_YMMu64_MASKmskw_AVX512_DEFINED

#define XED_IFORM_VPMOVM2Q_YMMu64_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVM2Q_ZMMu64_MASKmskw_AVX512_DEFINED

#define XED_IFORM_VPMOVM2Q_ZMMu64_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVM2W_XMMu16_MASKmskw_AVX512_DEFINED

#define XED_IFORM_VPMOVM2W_XMMu16_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVM2W_YMMu16_MASKmskw_AVX512_DEFINED

#define XED_IFORM_VPMOVM2W_YMMu16_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVM2W_ZMMu16_MASKmskw_AVX512_DEFINED

#define XED_IFORM_VPMOVM2W_ZMMu16_MASKmskw_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVMSKB_GPR32d_XMMdq_DEFINED

#define XED_IFORM_VPMOVMSKB_GPR32d_XMMdq_DEFINED   1

◆ XED_IFORM_VPMOVMSKB_GPR32d_YMMqq_DEFINED

#define XED_IFORM_VPMOVMSKB_GPR32d_YMMqq_DEFINED   1

◆ XED_IFORM_VPMOVQ2M_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVQ2M_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVQ2M_MASKmskw_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVQ2M_MASKmskw_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVQ2M_MASKmskw_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVQ2M_MASKmskw_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512_DEFINED

#define XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512_DEFINED

#define XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512_DEFINED

#define XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512_DEFINED

#define XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512_DEFINED

#define XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512_DEFINED

#define XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512_DEFINED

#define XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512_DEFINED

#define XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512_DEFINED

#define XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512_DEFINED

#define XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512_DEFINED

#define XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512_DEFINED

#define XED_IFORM_VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512_DEFINED

#define XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512_DEFINED

#define XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512_DEFINED

#define XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512_DEFINED

#define XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512_DEFINED

#define XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512_DEFINED

#define XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512_DEFINED

#define XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512_DEFINED

#define XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512_DEFINED

#define XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512_DEFINED

#define XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512_DEFINED

#define XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512_DEFINED

#define XED_IFORM_VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512_DEFINED

#define XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512_DEFINED

#define XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512_DEFINED

#define XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512_DEFINED

#define XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512_DEFINED

#define XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512_DEFINED

#define XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXBD_XMMdq_MEMd_DEFINED

#define XED_IFORM_VPMOVSXBD_XMMdq_MEMd_DEFINED   1

◆ XED_IFORM_VPMOVSXBD_XMMdq_XMMd_DEFINED

#define XED_IFORM_VPMOVSXBD_XMMdq_XMMd_DEFINED   1

◆ XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXBD_YMMqq_MEMq_DEFINED

#define XED_IFORM_VPMOVSXBD_YMMqq_MEMq_DEFINED   1

◆ XED_IFORM_VPMOVSXBD_YMMqq_XMMq_DEFINED

#define XED_IFORM_VPMOVSXBD_YMMqq_XMMq_DEFINED   1

◆ XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXBQ_XMMdq_MEMw_DEFINED

#define XED_IFORM_VPMOVSXBQ_XMMdq_MEMw_DEFINED   1

◆ XED_IFORM_VPMOVSXBQ_XMMdq_XMMw_DEFINED

#define XED_IFORM_VPMOVSXBQ_XMMdq_XMMw_DEFINED   1

◆ XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXBQ_YMMqq_MEMd_DEFINED

#define XED_IFORM_VPMOVSXBQ_YMMqq_MEMd_DEFINED   1

◆ XED_IFORM_VPMOVSXBQ_YMMqq_XMMd_DEFINED

#define XED_IFORM_VPMOVSXBQ_YMMqq_XMMd_DEFINED   1

◆ XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXBW_XMMdq_MEMq_DEFINED

#define XED_IFORM_VPMOVSXBW_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_VPMOVSXBW_XMMdq_XMMq_DEFINED

#define XED_IFORM_VPMOVSXBW_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXBW_YMMqq_MEMdq_DEFINED

#define XED_IFORM_VPMOVSXBW_YMMqq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMOVSXBW_YMMqq_XMMdq_DEFINED

#define XED_IFORM_VPMOVSXBW_YMMqq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXDQ_XMMdq_MEMq_DEFINED

#define XED_IFORM_VPMOVSXDQ_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_VPMOVSXDQ_XMMdq_XMMq_DEFINED

#define XED_IFORM_VPMOVSXDQ_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512_DEFINED

#define XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512_DEFINED

#define XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512_DEFINED

#define XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512_DEFINED

#define XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXDQ_YMMqq_MEMdq_DEFINED

#define XED_IFORM_VPMOVSXDQ_YMMqq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMOVSXDQ_YMMqq_XMMdq_DEFINED

#define XED_IFORM_VPMOVSXDQ_YMMqq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512_DEFINED

#define XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512_DEFINED

#define XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXWD_XMMdq_MEMq_DEFINED

#define XED_IFORM_VPMOVSXWD_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_VPMOVSXWD_XMMdq_XMMq_DEFINED

#define XED_IFORM_VPMOVSXWD_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXWD_YMMqq_MEMdq_DEFINED

#define XED_IFORM_VPMOVSXWD_YMMqq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMOVSXWD_YMMqq_XMMdq_DEFINED

#define XED_IFORM_VPMOVSXWD_YMMqq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXWQ_XMMdq_MEMd_DEFINED

#define XED_IFORM_VPMOVSXWQ_XMMdq_MEMd_DEFINED   1

◆ XED_IFORM_VPMOVSXWQ_XMMdq_XMMd_DEFINED

#define XED_IFORM_VPMOVSXWQ_XMMdq_XMMd_DEFINED   1

◆ XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXWQ_YMMqq_MEMq_DEFINED

#define XED_IFORM_VPMOVSXWQ_YMMqq_MEMq_DEFINED   1

◆ XED_IFORM_VPMOVSXWQ_YMMqq_XMMq_DEFINED

#define XED_IFORM_VPMOVSXWQ_YMMqq_XMMq_DEFINED   1

◆ XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVW2M_MASKmskw_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPMOVW2M_MASKmskw_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVW2M_MASKmskw_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPMOVW2M_MASKmskw_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVW2M_MASKmskw_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPMOVW2M_MASKmskw_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXBD_XMMdq_MEMd_DEFINED

#define XED_IFORM_VPMOVZXBD_XMMdq_MEMd_DEFINED   1

◆ XED_IFORM_VPMOVZXBD_XMMdq_XMMd_DEFINED

#define XED_IFORM_VPMOVZXBD_XMMdq_XMMd_DEFINED   1

◆ XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXBD_YMMqq_MEMq_DEFINED

#define XED_IFORM_VPMOVZXBD_YMMqq_MEMq_DEFINED   1

◆ XED_IFORM_VPMOVZXBD_YMMqq_XMMq_DEFINED

#define XED_IFORM_VPMOVZXBD_YMMqq_XMMq_DEFINED   1

◆ XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXBQ_XMMdq_MEMw_DEFINED

#define XED_IFORM_VPMOVZXBQ_XMMdq_MEMw_DEFINED   1

◆ XED_IFORM_VPMOVZXBQ_XMMdq_XMMw_DEFINED

#define XED_IFORM_VPMOVZXBQ_XMMdq_XMMw_DEFINED   1

◆ XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXBQ_YMMqq_MEMd_DEFINED

#define XED_IFORM_VPMOVZXBQ_YMMqq_MEMd_DEFINED   1

◆ XED_IFORM_VPMOVZXBQ_YMMqq_XMMd_DEFINED

#define XED_IFORM_VPMOVZXBQ_YMMqq_XMMd_DEFINED   1

◆ XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXBW_XMMdq_MEMq_DEFINED

#define XED_IFORM_VPMOVZXBW_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_VPMOVZXBW_XMMdq_XMMq_DEFINED

#define XED_IFORM_VPMOVZXBW_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXBW_YMMqq_MEMdq_DEFINED

#define XED_IFORM_VPMOVZXBW_YMMqq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMOVZXBW_YMMqq_XMMdq_DEFINED

#define XED_IFORM_VPMOVZXBW_YMMqq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512_DEFINED

#define XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXDQ_XMMdq_MEMq_DEFINED

#define XED_IFORM_VPMOVZXDQ_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_VPMOVZXDQ_XMMdq_XMMq_DEFINED

#define XED_IFORM_VPMOVZXDQ_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512_DEFINED

#define XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512_DEFINED

#define XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512_DEFINED

#define XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512_DEFINED

#define XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXDQ_YMMqq_MEMdq_DEFINED

#define XED_IFORM_VPMOVZXDQ_YMMqq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMOVZXDQ_YMMqq_XMMdq_DEFINED

#define XED_IFORM_VPMOVZXDQ_YMMqq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512_DEFINED

#define XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512_DEFINED

#define XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXWD_XMMdq_MEMq_DEFINED

#define XED_IFORM_VPMOVZXWD_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_VPMOVZXWD_XMMdq_XMMq_DEFINED

#define XED_IFORM_VPMOVZXWD_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXWD_YMMqq_MEMdq_DEFINED

#define XED_IFORM_VPMOVZXWD_YMMqq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMOVZXWD_YMMqq_XMMdq_DEFINED

#define XED_IFORM_VPMOVZXWD_YMMqq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXWQ_XMMdq_MEMd_DEFINED

#define XED_IFORM_VPMOVZXWQ_XMMdq_MEMd_DEFINED   1

◆ XED_IFORM_VPMOVZXWQ_XMMdq_XMMd_DEFINED

#define XED_IFORM_VPMOVZXWQ_XMMdq_XMMd_DEFINED   1

◆ XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXWQ_YMMqq_MEMq_DEFINED

#define XED_IFORM_VPMOVZXWQ_YMMqq_MEMq_DEFINED   1

◆ XED_IFORM_VPMOVZXWQ_YMMqq_XMMq_DEFINED

#define XED_IFORM_VPMOVZXWQ_YMMqq_XMMq_DEFINED   1

◆ XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512_DEFINED

#define XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMULDQ_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPMULDQ_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMULDQ_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMULDQ_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512_DEFINED

#define XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512_DEFINED

#define XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512_DEFINED

#define XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512_DEFINED

#define XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMULDQ_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPMULDQ_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPMULDQ_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPMULDQ_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512_DEFINED

#define XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512_DEFINED

#define XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512_DEFINED   1

◆ XED_IFORM_VPMULHRSW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPMULHRSW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMULHRSW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMULHRSW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED

#define XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED

#define XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMULHRSW_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPMULHRSW_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPMULHRSW_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPMULHRSW_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED

#define XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPMULHUW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPMULHUW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMULHUW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMULHUW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMULHUW_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPMULHUW_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPMULHUW_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPMULHUW_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMULHW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPMULHW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMULHW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMULHW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMULHW_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPMULHW_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPMULHW_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPMULHW_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMULLD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPMULLD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMULLD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMULLD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMULLD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPMULLD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPMULLD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPMULLD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMULLW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPMULLW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMULLW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMULLW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMULLW_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPMULLW_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPMULLW_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPMULLW_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMULUDQ_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPMULUDQ_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPMULUDQ_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPMULUDQ_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMULUDQ_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPMULUDQ_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPMULUDQ_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPMULUDQ_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED

#define XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED

#define XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED

#define XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPOR_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPOR_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPOR_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPOR_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPOR_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPOR_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPOR_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPOR_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPPERM_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VPPERM_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPROTB_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPROTB_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPROTB_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VPROTB_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPROTB_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPROTB_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPROTB_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPROTB_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPROTB_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPROTB_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPROTD_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPROTD_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPROTD_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VPROTD_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPROTD_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPROTD_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPROTD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPROTD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPROTD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPROTD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPROTQ_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPROTQ_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPROTQ_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VPROTQ_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPROTQ_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPROTQ_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPROTQ_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPROTQ_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPROTQ_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPROTQ_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPROTW_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPROTW_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPROTW_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VPROTW_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPROTW_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPROTW_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPROTW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPROTW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPROTW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPROTW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSADBW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSADBW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSADBW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSADBW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSADBW_XMMu16_XMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPSADBW_XMMu16_XMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSADBW_XMMu16_XMMu8_XMMu8_AVX512_DEFINED

#define XED_IFORM_VPSADBW_XMMu16_XMMu8_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSADBW_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPSADBW_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPSADBW_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPSADBW_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPSADBW_YMMu16_YMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPSADBW_YMMu16_YMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSADBW_YMMu16_YMMu8_YMMu8_AVX512_DEFINED

#define XED_IFORM_VPSADBW_YMMu16_YMMu8_YMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512_DEFINED

#define XED_IFORM_VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128_DEFINED

#define XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256_DEFINED

#define XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512_DEFINED

#define XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128_DEFINED

#define XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256_DEFINED

#define XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512_DEFINED

#define XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128_DEFINED

#define XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256_DEFINED

#define XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512_DEFINED

#define XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128_DEFINED

#define XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256_DEFINED

#define XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512_DEFINED

#define XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VPSHAB_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VPSHAB_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSHAB_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSHAB_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSHAB_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSHAB_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSHAD_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VPSHAD_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSHAD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSHAD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSHAD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSHAD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSHAQ_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VPSHAQ_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSHAQ_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSHAQ_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSHAQ_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSHAQ_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSHAW_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VPSHAW_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSHAW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSHAW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSHAW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSHAW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSHLB_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VPSHLB_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSHLB_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSHLB_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSHLB_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSHLB_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSHLD_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VPSHLD_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSHLD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSHLD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSHLD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSHLD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHLQ_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VPSHLQ_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSHLQ_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSHLQ_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSHLQ_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSHLQ_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSHLW_XMMdq_MEMdq_XMMdq_DEFINED

#define XED_IFORM_VPSHLW_XMMdq_MEMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSHLW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSHLW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSHLW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSHLW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFB_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSHUFB_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSHUFB_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSHUFB_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED

#define XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFB_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPSHUFB_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPSHUFB_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPSHUFB_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED

#define XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED

#define XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512_DEFINED

#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512_DEFINED

#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512_DEFINED

#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFD_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPSHUFD_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPSHUFD_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPSHUFD_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFD_YMMqq_MEMqq_IMMb_DEFINED

#define XED_IFORM_VPSHUFD_YMMqq_MEMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFHW_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPSHUFHW_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPSHUFHW_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPSHUFHW_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFHW_YMMqq_MEMqq_IMMb_DEFINED

#define XED_IFORM_VPSHUFHW_YMMqq_MEMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFLW_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VPSHUFLW_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPSHUFLW_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPSHUFLW_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFLW_YMMqq_MEMqq_IMMb_DEFINED

#define XED_IFORM_VPSHUFLW_YMMqq_MEMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSIGNB_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSIGNB_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSIGNB_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSIGNB_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSIGNB_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPSIGNB_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPSIGNB_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPSIGNB_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPSIGND_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSIGND_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSIGND_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSIGND_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSIGND_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPSIGND_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPSIGND_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPSIGND_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPSIGNW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSIGNW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSIGNW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSIGNW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSIGNW_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPSIGNW_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPSIGNW_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPSIGNW_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPSLLD_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPSLLD_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPSLLD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSLLD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSLLD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSLLD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPSLLD_YMMqq_YMMqq_MEMdq_DEFINED

#define XED_IFORM_VPSLLD_YMMqq_YMMqq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSLLD_YMMqq_YMMqq_XMMq_DEFINED

#define XED_IFORM_VPSLLD_YMMqq_YMMqq_XMMq_DEFINED   1

◆ XED_IFORM_VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLDQ_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPSLLDQ_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLQ_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPSLLQ_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPSLLQ_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSLLQ_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSLLQ_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSLLQ_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPSLLQ_YMMqq_YMMqq_MEMdq_DEFINED

#define XED_IFORM_VPSLLQ_YMMqq_YMMqq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSLLQ_YMMqq_YMMqq_XMMq_DEFINED

#define XED_IFORM_VPSLLQ_YMMqq_YMMqq_XMMq_DEFINED   1

◆ XED_IFORM_VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLVD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSLLVD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSLLVD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSLLVD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLVD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPSLLVD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPSLLVD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPSLLVD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLVQ_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSLLVQ_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSLLVQ_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSLLVQ_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLVQ_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPSLLVQ_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPSLLVQ_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPSLLVQ_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLW_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPSLLW_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPSLLW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSLLW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSLLW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSLLW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPSLLW_YMMqq_YMMqq_MEMdq_DEFINED

#define XED_IFORM_VPSLLW_YMMqq_YMMqq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSLLW_YMMqq_YMMqq_XMMq_DEFINED

#define XED_IFORM_VPSLLW_YMMqq_YMMqq_XMMq_DEFINED   1

◆ XED_IFORM_VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAD_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPSRAD_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPSRAD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSRAD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSRAD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSRAD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPSRAD_YMMqq_YMMqq_MEMdq_DEFINED

#define XED_IFORM_VPSRAD_YMMqq_YMMqq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSRAD_YMMqq_YMMqq_XMMq_DEFINED

#define XED_IFORM_VPSRAD_YMMqq_YMMqq_XMMq_DEFINED   1

◆ XED_IFORM_VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAVD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSRAVD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSRAVD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSRAVD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAVD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPSRAVD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPSRAVD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPSRAVD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAW_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPSRAW_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPSRAW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSRAW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSRAW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSRAW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPSRAW_YMMqq_YMMqq_MEMdq_DEFINED

#define XED_IFORM_VPSRAW_YMMqq_YMMqq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSRAW_YMMqq_YMMqq_XMMq_DEFINED

#define XED_IFORM_VPSRAW_YMMqq_YMMqq_XMMq_DEFINED   1

◆ XED_IFORM_VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLD_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPSRLD_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPSRLD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSRLD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSRLD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSRLD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPSRLD_YMMqq_YMMqq_MEMdq_DEFINED

#define XED_IFORM_VPSRLD_YMMqq_YMMqq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSRLD_YMMqq_YMMqq_XMMq_DEFINED

#define XED_IFORM_VPSRLD_YMMqq_YMMqq_XMMq_DEFINED   1

◆ XED_IFORM_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLDQ_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPSRLDQ_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLQ_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPSRLQ_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPSRLQ_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSRLQ_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSRLQ_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSRLQ_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPSRLQ_YMMqq_YMMqq_MEMdq_DEFINED

#define XED_IFORM_VPSRLQ_YMMqq_YMMqq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSRLQ_YMMqq_YMMqq_XMMq_DEFINED

#define XED_IFORM_VPSRLQ_YMMqq_YMMqq_XMMq_DEFINED   1

◆ XED_IFORM_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLVD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSRLVD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSRLVD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSRLVD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLVD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPSRLVD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPSRLVD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPSRLVD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLVQ_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSRLVQ_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSRLVQ_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSRLVQ_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLVQ_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPSRLVQ_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPSRLVQ_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPSRLVQ_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLW_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VPSRLW_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VPSRLW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSRLW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSRLW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSRLW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VPSRLW_YMMqq_YMMqq_MEMdq_DEFINED

#define XED_IFORM_VPSRLW_YMMqq_YMMqq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSRLW_YMMqq_YMMqq_XMMq_DEFINED

#define XED_IFORM_VPSRLW_YMMqq_YMMqq_XMMq_DEFINED   1

◆ XED_IFORM_VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED

#define XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBB_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSUBB_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSUBB_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSUBB_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED

#define XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBB_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPSUBB_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPSUBB_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPSUBB_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED

#define XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED

#define XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSUBD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSUBD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSUBD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPSUBD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPSUBD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPSUBD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBQ_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSUBQ_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSUBQ_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSUBQ_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBQ_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPSUBQ_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPSUBQ_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPSUBQ_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBSB_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSUBSB_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSUBSB_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSUBSB_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED

#define XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED

#define XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBSB_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPSUBSB_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPSUBSB_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPSUBSB_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED

#define XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED

#define XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBSW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSUBSW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSUBSW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSUBSW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED

#define XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED

#define XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBSW_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPSUBSW_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPSUBSW_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPSUBSW_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED

#define XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED

#define XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBUSB_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSUBUSB_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSUBUSB_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSUBUSB_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED

#define XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBUSB_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPSUBUSB_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPSUBUSB_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPSUBUSB_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED

#define XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED

#define XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBUSW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSUBUSW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSUBUSW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSUBUSW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBUSW_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPSUBUSW_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPSUBUSW_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPSUBUSW_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPSUBW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPSUBW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPSUBW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBW_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPSUBW_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPSUBW_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPSUBW_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VPTEST_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPTEST_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPTEST_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPTEST_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPTEST_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPTEST_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPTEST_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPTEST_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED

#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED

#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED

#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED

#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED

#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED

#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED

#define XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED

#define XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED

#define XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED

#define XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED

#define XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED

#define XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED

#define XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED

#define XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED

#define XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED

#define XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED

#define XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED   1

◆ XED_IFORM_VPXOR_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VPXOR_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VPXOR_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VPXOR_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VPXOR_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VPXOR_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VPXOR_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VPXOR_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED

#define XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED

#define XED_IFORM_VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER_DEFINED

#define XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER_DEFINED   1

◆ XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER_DEFINED

#define XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER_DEFINED   1

◆ XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER_DEFINED

#define XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER_DEFINED   1

◆ XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER_DEFINED

#define XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER_DEFINED   1

◆ XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER_DEFINED

#define XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER_DEFINED   1

◆ XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER_DEFINED

#define XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER_DEFINED   1

◆ XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER_DEFINED

#define XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER_DEFINED   1

◆ XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER_DEFINED

#define XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER_DEFINED   1

◆ XED_IFORM_VRCPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VRCPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VRCPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512_DEFINED

#define XED_IFORM_VRCPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VRCPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VRCPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VRCPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512_DEFINED

#define XED_IFORM_VRCPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VRCPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VRCPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VRCPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512_DEFINED

#define XED_IFORM_VRCPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED

#define XED_IFORM_VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VRCPPS_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VRCPPS_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VRCPPS_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VRCPPS_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VRCPPS_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VRCPPS_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VRCPPS_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VRCPPS_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VRCPSS_XMMdq_XMMdq_MEMd_DEFINED

#define XED_IFORM_VRCPSS_XMMdq_XMMdq_MEMd_DEFINED   1

◆ XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd_DEFINED

#define XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd_DEFINED   1

◆ XED_IFORM_VREDUCEBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCEBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCEBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCEBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCEBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCEBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCEBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCEBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCEBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCEBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCEBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCEBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALEBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALEBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALEBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALEBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALEBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALEBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALEBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALEBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALEBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALEBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALEBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALEBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb_DEFINED

#define XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb_DEFINED   1

◆ XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VROUNDPS_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VROUNDPS_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VROUNDPS_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VROUNDPS_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VROUNDPS_YMMqq_MEMqq_IMMb_DEFINED

#define XED_IFORM_VROUNDPS_YMMqq_MEMqq_IMMb_DEFINED   1

◆ XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VROUNDSD_XMMdq_XMMdq_MEMq_IMMb_DEFINED

#define XED_IFORM_VROUNDSD_XMMdq_XMMdq_MEMq_IMMb_DEFINED   1

◆ XED_IFORM_VROUNDSD_XMMdq_XMMdq_XMMq_IMMb_DEFINED

#define XED_IFORM_VROUNDSD_XMMdq_XMMdq_XMMq_IMMb_DEFINED   1

◆ XED_IFORM_VROUNDSS_XMMdq_XMMdq_MEMd_IMMb_DEFINED

#define XED_IFORM_VROUNDSS_XMMdq_XMMdq_MEMd_IMMb_DEFINED   1

◆ XED_IFORM_VROUNDSS_XMMdq_XMMdq_XMMd_IMMb_DEFINED

#define XED_IFORM_VROUNDSS_XMMdq_XMMdq_XMMd_IMMb_DEFINED   1

◆ XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED

#define XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED

#define XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER_DEFINED

#define XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER_DEFINED   1

◆ XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER_DEFINED

#define XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER_DEFINED   1

◆ XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER_DEFINED

#define XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER_DEFINED   1

◆ XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER_DEFINED

#define XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER_DEFINED   1

◆ XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER_DEFINED

#define XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER_DEFINED   1

◆ XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER_DEFINED

#define XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER_DEFINED   1

◆ XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER_DEFINED

#define XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER_DEFINED   1

◆ XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER_DEFINED

#define XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER_DEFINED   1

◆ XED_IFORM_VRSQRTBF16_XMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VRSQRTBF16_XMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRTBF16_XMMbf16_MASKmskw_XMMbf16_AVX512_DEFINED

#define XED_IFORM_VRSQRTBF16_XMMbf16_MASKmskw_XMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRTBF16_YMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VRSQRTBF16_YMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRTBF16_YMMbf16_MASKmskw_YMMbf16_AVX512_DEFINED

#define XED_IFORM_VRSQRTBF16_YMMbf16_MASKmskw_YMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRTBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VRSQRTBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRTBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512_DEFINED

#define XED_IFORM_VRSQRTBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED

#define XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRTPS_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VRSQRTPS_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VRSQRTPS_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VRSQRTPS_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VRSQRTPS_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VRSQRTPS_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VRSQRTPS_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VRSQRTPS_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VRSQRTSS_XMMdq_XMMdq_MEMd_DEFINED

#define XED_IFORM_VRSQRTSS_XMMdq_XMMdq_MEMd_DEFINED   1

◆ XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd_DEFINED

#define XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd_DEFINED   1

◆ XED_IFORM_VSCALEFBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VSCALEFBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

#define XED_IFORM_VSCALEFBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VSCALEFBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

#define XED_IFORM_VSCALEFBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VSCALEFBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

#define XED_IFORM_VSCALEFBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128_DEFINED

#define XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256_DEFINED

#define XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512_DEFINED

#define XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128_DEFINED

#define XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256_DEFINED

#define XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512_DEFINED

#define XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED

#define XED_IFORM_VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED   1

◆ XED_IFORM_VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED

#define XED_IFORM_VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED   1

◆ XED_IFORM_VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED

#define XED_IFORM_VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED   1

◆ XED_IFORM_VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED

#define XED_IFORM_VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED   1

◆ XED_IFORM_VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED

#define XED_IFORM_VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED   1

◆ XED_IFORM_VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED

#define XED_IFORM_VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED   1

◆ XED_IFORM_VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED

#define XED_IFORM_VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED   1

◆ XED_IFORM_VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED

#define XED_IFORM_VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED   1

◆ XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128_DEFINED

#define XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256_DEFINED

#define XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512_DEFINED

#define XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128_DEFINED

#define XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128_DEFINED   1

◆ XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256_DEFINED

#define XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256_DEFINED   1

◆ XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512_DEFINED

#define XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512_DEFINED   1

◆ XED_IFORM_VSHA512MSG1_YMMu64_XMMu64_DEFINED

#define XED_IFORM_VSHA512MSG1_YMMu64_XMMu64_DEFINED   1

◆ XED_IFORM_VSHA512MSG2_YMMu64_YMMu64_DEFINED

#define XED_IFORM_VSHA512MSG2_YMMu64_YMMu64_DEFINED   1

◆ XED_IFORM_VSHA512RNDS2_YMMu64_YMMu64_XMMu64_DEFINED

#define XED_IFORM_VSHA512RNDS2_YMMu64_YMMu64_XMMu64_DEFINED   1

◆ XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED

#define XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED

#define XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED

#define XED_IFORM_VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1

◆ XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED

#define XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED

#define XED_IFORM_VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED   1

◆ XED_IFORM_VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED

#define XED_IFORM_VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED   1

◆ XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED

#define XED_IFORM_VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED   1

◆ XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED

#define XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED   1

◆ XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED

#define XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED   1

◆ XED_IFORM_VSM3MSG1_XMMu32_XMMu32_MEMu32_DEFINED

#define XED_IFORM_VSM3MSG1_XMMu32_XMMu32_MEMu32_DEFINED   1

◆ XED_IFORM_VSM3MSG1_XMMu32_XMMu32_XMMu32_DEFINED

#define XED_IFORM_VSM3MSG1_XMMu32_XMMu32_XMMu32_DEFINED   1

◆ XED_IFORM_VSM3MSG2_XMMu32_XMMu32_MEMu32_DEFINED

#define XED_IFORM_VSM3MSG2_XMMu32_XMMu32_MEMu32_DEFINED   1

◆ XED_IFORM_VSM3MSG2_XMMu32_XMMu32_XMMu32_DEFINED

#define XED_IFORM_VSM3MSG2_XMMu32_XMMu32_XMMu32_DEFINED   1

◆ XED_IFORM_VSM3RNDS2_XMMu32_XMMu32_MEMu32_IMM8_DEFINED

#define XED_IFORM_VSM3RNDS2_XMMu32_XMMu32_MEMu32_IMM8_DEFINED   1

◆ XED_IFORM_VSM3RNDS2_XMMu32_XMMu32_XMMu32_IMM8_DEFINED

#define XED_IFORM_VSM3RNDS2_XMMu32_XMMu32_XMMu32_IMM8_DEFINED   1

◆ XED_IFORM_VSM4KEY4_XMMu32_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VSM4KEY4_XMMu32_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VSM4KEY4_XMMu32_XMMu32_MEMu32_DEFINED

#define XED_IFORM_VSM4KEY4_XMMu32_XMMu32_MEMu32_DEFINED   1

◆ XED_IFORM_VSM4KEY4_XMMu32_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VSM4KEY4_XMMu32_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VSM4KEY4_XMMu32_XMMu32_XMMu32_DEFINED

#define XED_IFORM_VSM4KEY4_XMMu32_XMMu32_XMMu32_DEFINED   1

◆ XED_IFORM_VSM4KEY4_YMMu32_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VSM4KEY4_YMMu32_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VSM4KEY4_YMMu32_YMMu32_MEMu32_DEFINED

#define XED_IFORM_VSM4KEY4_YMMu32_YMMu32_MEMu32_DEFINED   1

◆ XED_IFORM_VSM4KEY4_YMMu32_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VSM4KEY4_YMMu32_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VSM4KEY4_YMMu32_YMMu32_YMMu32_DEFINED

#define XED_IFORM_VSM4KEY4_YMMu32_YMMu32_YMMu32_DEFINED   1

◆ XED_IFORM_VSM4KEY4_ZMMu32_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VSM4KEY4_ZMMu32_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VSM4KEY4_ZMMu32_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VSM4KEY4_ZMMu32_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_MEMu32_DEFINED

#define XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_MEMu32_DEFINED   1

◆ XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_XMMu32_DEFINED

#define XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_XMMu32_DEFINED   1

◆ XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_MEMu32_DEFINED

#define XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_MEMu32_DEFINED   1

◆ XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_YMMu32_DEFINED

#define XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_YMMu32_DEFINED   1

◆ XED_IFORM_VSM4RNDS4_ZMMu32_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VSM4RNDS4_ZMMu32_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VSM4RNDS4_ZMMu32_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VSM4RNDS4_ZMMu32_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTBF16_XMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VSQRTBF16_XMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTBF16_XMMbf16_MASKmskw_XMMbf16_AVX512_DEFINED

#define XED_IFORM_VSQRTBF16_XMMbf16_MASKmskw_XMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTBF16_YMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VSQRTBF16_YMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTBF16_YMMbf16_MASKmskw_YMMbf16_AVX512_DEFINED

#define XED_IFORM_VSQRTBF16_YMMbf16_MASKmskw_YMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VSQRTBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512_DEFINED

#define XED_IFORM_VSQRTBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTPD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VSQRTPD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VSQRTPD_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VSQRTPD_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED

#define XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED

#define XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTPD_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VSQRTPD_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VSQRTPD_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VSQRTPD_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED

#define XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED

#define XED_IFORM_VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED

#define XED_IFORM_VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED

#define XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTPS_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VSQRTPS_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VSQRTPS_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VSQRTPS_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED

#define XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED

#define XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTPS_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VSQRTPS_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VSQRTPS_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VSQRTPS_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED

#define XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTSD_XMMdq_XMMdq_MEMq_DEFINED

#define XED_IFORM_VSQRTSD_XMMdq_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_VSQRTSD_XMMdq_XMMdq_XMMq_DEFINED

#define XED_IFORM_VSQRTSD_XMMdq_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd_DEFINED

#define XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd_DEFINED   1

◆ XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd_DEFINED

#define XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd_DEFINED   1

◆ XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VSTMXCSR_MEMd_DEFINED

#define XED_IFORM_VSTMXCSR_MEMd_DEFINED   1

◆ XED_IFORM_VSUBBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VSUBBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VSUBBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED

#define XED_IFORM_VSUBBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VSUBBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VSUBBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VSUBBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED

#define XED_IFORM_VSUBBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VSUBBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED

#define XED_IFORM_VSUBBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VSUBBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED

#define XED_IFORM_VSUBBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512_DEFINED   1

◆ XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED

#define XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED

#define XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VSUBPS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VSUBPS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VSUBPS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VSUBPS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VSUBSD_XMMdq_XMMdq_MEMq_DEFINED

#define XED_IFORM_VSUBSD_XMMdq_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_VSUBSD_XMMdq_XMMdq_XMMq_DEFINED

#define XED_IFORM_VSUBSD_XMMdq_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd_DEFINED

#define XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd_DEFINED   1

◆ XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd_DEFINED

#define XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd_DEFINED   1

◆ XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VTESTPD_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VTESTPD_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VTESTPD_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VTESTPD_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VTESTPD_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VTESTPD_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VTESTPD_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VTESTPD_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VTESTPS_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VTESTPS_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VTESTPS_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VTESTPS_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VTESTPS_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VTESTPS_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VTESTPS_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VTESTPS_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VUCOMISD_XMMdq_MEMq_DEFINED

#define XED_IFORM_VUCOMISD_XMMdq_MEMq_DEFINED   1

◆ XED_IFORM_VUCOMISD_XMMdq_XMMq_DEFINED

#define XED_IFORM_VUCOMISD_XMMdq_XMMq_DEFINED   1

◆ XED_IFORM_VUCOMISD_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VUCOMISD_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VUCOMISH_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VUCOMISH_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VUCOMISS_XMMdq_MEMd_DEFINED

#define XED_IFORM_VUCOMISS_XMMdq_MEMd_DEFINED   1

◆ XED_IFORM_VUCOMISS_XMMdq_XMMd_DEFINED

#define XED_IFORM_VUCOMISS_XMMdq_XMMd_DEFINED   1

◆ XED_IFORM_VUCOMISS_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VUCOMISS_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VUCOMXSD_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VUCOMXSD_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VUCOMXSD_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VUCOMXSD_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VUCOMXSH_XMMf16_MEMf16_AVX512_DEFINED

#define XED_IFORM_VUCOMXSH_XMMf16_MEMf16_AVX512_DEFINED   1

◆ XED_IFORM_VUCOMXSH_XMMf16_XMMf16_AVX512_DEFINED

#define XED_IFORM_VUCOMXSH_XMMf16_XMMf16_AVX512_DEFINED   1

◆ XED_IFORM_VUCOMXSS_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VUCOMXSS_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VUCOMXSS_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VUCOMXSS_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED

#define XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED

#define XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED

#define XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED   1

◆ XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED

#define XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED   1

◆ XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED

#define XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED

#define XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED

#define XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED   1

◆ XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED

#define XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED   1

◆ XED_IFORM_VXORPD_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VXORPD_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VXORPD_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VXORPD_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED

#define XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VXORPD_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VXORPD_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VXORPD_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VXORPD_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED

#define XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED

#define XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED   1

◆ XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED

#define XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED   1

◆ XED_IFORM_VXORPS_XMMdq_XMMdq_MEMdq_DEFINED

#define XED_IFORM_VXORPS_XMMdq_XMMdq_MEMdq_DEFINED   1

◆ XED_IFORM_VXORPS_XMMdq_XMMdq_XMMdq_DEFINED

#define XED_IFORM_VXORPS_XMMdq_XMMdq_XMMdq_DEFINED   1

◆ XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED

#define XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VXORPS_YMMqq_YMMqq_MEMqq_DEFINED

#define XED_IFORM_VXORPS_YMMqq_YMMqq_MEMqq_DEFINED   1

◆ XED_IFORM_VXORPS_YMMqq_YMMqq_YMMqq_DEFINED

#define XED_IFORM_VXORPS_YMMqq_YMMqq_YMMqq_DEFINED   1

◆ XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED

#define XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED

#define XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED   1

◆ XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED

#define XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED   1

◆ XED_IFORM_VZEROALL_DEFINED

#define XED_IFORM_VZEROALL_DEFINED   1

◆ XED_IFORM_VZEROUPPER_DEFINED

#define XED_IFORM_VZEROUPPER_DEFINED   1

◆ XED_IFORM_WBINVD_DEFINED

#define XED_IFORM_WBINVD_DEFINED   1

◆ XED_IFORM_WBNOINVD_DEFINED

#define XED_IFORM_WBNOINVD_DEFINED   1

◆ XED_IFORM_WRFSBASE_GPRy_DEFINED

#define XED_IFORM_WRFSBASE_GPRy_DEFINED   1

◆ XED_IFORM_WRGSBASE_GPRy_DEFINED

#define XED_IFORM_WRGSBASE_GPRy_DEFINED   1

◆ XED_IFORM_WRMSR_DEFINED

#define XED_IFORM_WRMSR_DEFINED   1

◆ XED_IFORM_WRMSRLIST_DEFINED

#define XED_IFORM_WRMSRLIST_DEFINED   1

◆ XED_IFORM_WRMSRNS_DEFINED

#define XED_IFORM_WRMSRNS_DEFINED   1

◆ XED_IFORM_WRMSRNS_IMM32_GPR64u64_APX_DEFINED

#define XED_IFORM_WRMSRNS_IMM32_GPR64u64_APX_DEFINED   1

◆ XED_IFORM_WRMSRNS_IMM32_GPR64u64_DEFINED

#define XED_IFORM_WRMSRNS_IMM32_GPR64u64_DEFINED   1

◆ XED_IFORM_WRPKRU_DEFINED

#define XED_IFORM_WRPKRU_DEFINED   1

◆ XED_IFORM_WRSSD_MEMu32_GPR32u32_APX_DEFINED

#define XED_IFORM_WRSSD_MEMu32_GPR32u32_APX_DEFINED   1

◆ XED_IFORM_WRSSD_MEMu32_GPR32u32_DEFINED

#define XED_IFORM_WRSSD_MEMu32_GPR32u32_DEFINED   1

◆ XED_IFORM_WRSSQ_MEMu64_GPR64u64_APX_DEFINED

#define XED_IFORM_WRSSQ_MEMu64_GPR64u64_APX_DEFINED   1

◆ XED_IFORM_WRSSQ_MEMu64_GPR64u64_DEFINED

#define XED_IFORM_WRSSQ_MEMu64_GPR64u64_DEFINED   1

◆ XED_IFORM_WRUSSD_MEMu32_GPR32u32_APX_DEFINED

#define XED_IFORM_WRUSSD_MEMu32_GPR32u32_APX_DEFINED   1

◆ XED_IFORM_WRUSSD_MEMu32_GPR32u32_DEFINED

#define XED_IFORM_WRUSSD_MEMu32_GPR32u32_DEFINED   1

◆ XED_IFORM_WRUSSQ_MEMu64_GPR64u64_APX_DEFINED

#define XED_IFORM_WRUSSQ_MEMu64_GPR64u64_APX_DEFINED   1

◆ XED_IFORM_WRUSSQ_MEMu64_GPR64u64_DEFINED

#define XED_IFORM_WRUSSQ_MEMu64_GPR64u64_DEFINED   1

◆ XED_IFORM_XABORT_IMMb_DEFINED

#define XED_IFORM_XABORT_IMMb_DEFINED   1

◆ XED_IFORM_XADD_GPR8_GPR8_DEFINED

#define XED_IFORM_XADD_GPR8_GPR8_DEFINED   1

◆ XED_IFORM_XADD_GPRv_GPRv_DEFINED

#define XED_IFORM_XADD_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_XADD_LOCK_MEMb_GPR8_DEFINED

#define XED_IFORM_XADD_LOCK_MEMb_GPR8_DEFINED   1

◆ XED_IFORM_XADD_LOCK_MEMv_GPRv_DEFINED

#define XED_IFORM_XADD_LOCK_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_XADD_MEMb_GPR8_DEFINED

#define XED_IFORM_XADD_MEMb_GPR8_DEFINED   1

◆ XED_IFORM_XADD_MEMv_GPRv_DEFINED

#define XED_IFORM_XADD_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_XBEGIN_RELBRz_DEFINED

#define XED_IFORM_XBEGIN_RELBRz_DEFINED   1

◆ XED_IFORM_XCHG_GPR8_GPR8_DEFINED

#define XED_IFORM_XCHG_GPR8_GPR8_DEFINED   1

◆ XED_IFORM_XCHG_GPRv_GPRv_DEFINED

#define XED_IFORM_XCHG_GPRv_GPRv_DEFINED   1

◆ XED_IFORM_XCHG_GPRv_OrAX_DEFINED

#define XED_IFORM_XCHG_GPRv_OrAX_DEFINED   1

◆ XED_IFORM_XCHG_MEMb_GPR8_DEFINED

#define XED_IFORM_XCHG_MEMb_GPR8_DEFINED   1

◆ XED_IFORM_XCHG_MEMv_GPRv_DEFINED

#define XED_IFORM_XCHG_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_XEND_DEFINED

#define XED_IFORM_XEND_DEFINED   1

◆ XED_IFORM_XGETBV_DEFINED

#define XED_IFORM_XGETBV_DEFINED   1

◆ XED_IFORM_XLAT_DEFINED

#define XED_IFORM_XLAT_DEFINED   1

◆ XED_IFORM_XOR_AL_IMMb_DEFINED

#define XED_IFORM_XOR_AL_IMMb_DEFINED   1

◆ XED_IFORM_XOR_GPR8_GPR8_30_DEFINED

#define XED_IFORM_XOR_GPR8_GPR8_30_DEFINED   1

◆ XED_IFORM_XOR_GPR8_GPR8_32_DEFINED

#define XED_IFORM_XOR_GPR8_GPR8_32_DEFINED   1

◆ XED_IFORM_XOR_GPR8_IMMb_80r6_DEFINED

#define XED_IFORM_XOR_GPR8_IMMb_80r6_DEFINED   1

◆ XED_IFORM_XOR_GPR8_IMMb_82r6_DEFINED

#define XED_IFORM_XOR_GPR8_IMMb_82r6_DEFINED   1

◆ XED_IFORM_XOR_GPR8_MEMb_DEFINED

#define XED_IFORM_XOR_GPR8_MEMb_DEFINED   1

◆ XED_IFORM_XOR_GPR8i8_GPR8i8_APX_DEFINED

#define XED_IFORM_XOR_GPR8i8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_XOR_GPR8i8_GPR8i8_GPR8i8_APX_DEFINED

#define XED_IFORM_XOR_GPR8i8_GPR8i8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_XOR_GPR8i8_GPR8i8_IMM8_APX_DEFINED

#define XED_IFORM_XOR_GPR8i8_GPR8i8_IMM8_APX_DEFINED   1

◆ XED_IFORM_XOR_GPR8i8_GPR8i8_MEMi8_APX_DEFINED

#define XED_IFORM_XOR_GPR8i8_GPR8i8_MEMi8_APX_DEFINED   1

◆ XED_IFORM_XOR_GPR8i8_IMM8_APX_DEFINED

#define XED_IFORM_XOR_GPR8i8_IMM8_APX_DEFINED   1

◆ XED_IFORM_XOR_GPR8i8_MEMi8_APX_DEFINED

#define XED_IFORM_XOR_GPR8i8_MEMi8_APX_DEFINED   1

◆ XED_IFORM_XOR_GPR8i8_MEMi8_GPR8i8_APX_DEFINED

#define XED_IFORM_XOR_GPR8i8_MEMi8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_XOR_GPR8i8_MEMi8_IMM8_APX_DEFINED

#define XED_IFORM_XOR_GPR8i8_MEMi8_IMM8_APX_DEFINED   1

◆ XED_IFORM_XOR_GPRv_GPRv_31_DEFINED

#define XED_IFORM_XOR_GPRv_GPRv_31_DEFINED   1

◆ XED_IFORM_XOR_GPRv_GPRv_33_DEFINED

#define XED_IFORM_XOR_GPRv_GPRv_33_DEFINED   1

◆ XED_IFORM_XOR_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_XOR_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_XOR_GPRv_GPRv_GPRv_APX_DEFINED

#define XED_IFORM_XOR_GPRv_GPRv_GPRv_APX_DEFINED   1

◆ XED_IFORM_XOR_GPRv_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_XOR_GPRv_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_XOR_GPRv_GPRv_IMMz_APX_DEFINED

#define XED_IFORM_XOR_GPRv_GPRv_IMMz_APX_DEFINED   1

◆ XED_IFORM_XOR_GPRv_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_XOR_GPRv_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_XOR_GPRv_IMM8_APX_DEFINED

#define XED_IFORM_XOR_GPRv_IMM8_APX_DEFINED   1

◆ XED_IFORM_XOR_GPRv_IMMb_DEFINED

#define XED_IFORM_XOR_GPRv_IMMb_DEFINED   1

◆ XED_IFORM_XOR_GPRv_IMMz_APX_DEFINED

#define XED_IFORM_XOR_GPRv_IMMz_APX_DEFINED   1

◆ XED_IFORM_XOR_GPRv_IMMz_DEFINED

#define XED_IFORM_XOR_GPRv_IMMz_DEFINED   1

◆ XED_IFORM_XOR_GPRv_MEMv_APX_DEFINED

#define XED_IFORM_XOR_GPRv_MEMv_APX_DEFINED   1

◆ XED_IFORM_XOR_GPRv_MEMv_DEFINED

#define XED_IFORM_XOR_GPRv_MEMv_DEFINED   1

◆ XED_IFORM_XOR_GPRv_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_XOR_GPRv_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_XOR_GPRv_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_XOR_GPRv_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_XOR_GPRv_MEMv_IMMz_APX_DEFINED

#define XED_IFORM_XOR_GPRv_MEMv_IMMz_APX_DEFINED   1

◆ XED_IFORM_XOR_LOCK_MEMb_GPR8_DEFINED

#define XED_IFORM_XOR_LOCK_MEMb_GPR8_DEFINED   1

◆ XED_IFORM_XOR_LOCK_MEMb_IMMb_80r6_DEFINED

#define XED_IFORM_XOR_LOCK_MEMb_IMMb_80r6_DEFINED   1

◆ XED_IFORM_XOR_LOCK_MEMb_IMMb_82r6_DEFINED

#define XED_IFORM_XOR_LOCK_MEMb_IMMb_82r6_DEFINED   1

◆ XED_IFORM_XOR_LOCK_MEMv_GPRv_DEFINED

#define XED_IFORM_XOR_LOCK_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_XOR_LOCK_MEMv_IMMb_DEFINED

#define XED_IFORM_XOR_LOCK_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_XOR_LOCK_MEMv_IMMz_DEFINED

#define XED_IFORM_XOR_LOCK_MEMv_IMMz_DEFINED   1

◆ XED_IFORM_XOR_MEMb_GPR8_DEFINED

#define XED_IFORM_XOR_MEMb_GPR8_DEFINED   1

◆ XED_IFORM_XOR_MEMb_IMMb_80r6_DEFINED

#define XED_IFORM_XOR_MEMb_IMMb_80r6_DEFINED   1

◆ XED_IFORM_XOR_MEMb_IMMb_82r6_DEFINED

#define XED_IFORM_XOR_MEMb_IMMb_82r6_DEFINED   1

◆ XED_IFORM_XOR_MEMi8_GPR8i8_APX_DEFINED

#define XED_IFORM_XOR_MEMi8_GPR8i8_APX_DEFINED   1

◆ XED_IFORM_XOR_MEMi8_IMM8_APX_DEFINED

#define XED_IFORM_XOR_MEMi8_IMM8_APX_DEFINED   1

◆ XED_IFORM_XOR_MEMv_GPRv_APX_DEFINED

#define XED_IFORM_XOR_MEMv_GPRv_APX_DEFINED   1

◆ XED_IFORM_XOR_MEMv_GPRv_DEFINED

#define XED_IFORM_XOR_MEMv_GPRv_DEFINED   1

◆ XED_IFORM_XOR_MEMv_IMM8_APX_DEFINED

#define XED_IFORM_XOR_MEMv_IMM8_APX_DEFINED   1

◆ XED_IFORM_XOR_MEMv_IMMb_DEFINED

#define XED_IFORM_XOR_MEMv_IMMb_DEFINED   1

◆ XED_IFORM_XOR_MEMv_IMMz_APX_DEFINED

#define XED_IFORM_XOR_MEMv_IMMz_APX_DEFINED   1

◆ XED_IFORM_XOR_MEMv_IMMz_DEFINED

#define XED_IFORM_XOR_MEMv_IMMz_DEFINED   1

◆ XED_IFORM_XOR_OrAX_IMMz_DEFINED

#define XED_IFORM_XOR_OrAX_IMMz_DEFINED   1

◆ XED_IFORM_XORPD_XMMxuq_MEMxuq_DEFINED

#define XED_IFORM_XORPD_XMMxuq_MEMxuq_DEFINED   1

◆ XED_IFORM_XORPD_XMMxuq_XMMxuq_DEFINED

#define XED_IFORM_XORPD_XMMxuq_XMMxuq_DEFINED   1

◆ XED_IFORM_XORPS_XMMxud_MEMxud_DEFINED

#define XED_IFORM_XORPS_XMMxud_MEMxud_DEFINED   1

◆ XED_IFORM_XORPS_XMMxud_XMMxud_DEFINED

#define XED_IFORM_XORPS_XMMxud_XMMxud_DEFINED   1

◆ XED_IFORM_XRESLDTRK_DEFINED

#define XED_IFORM_XRESLDTRK_DEFINED   1

◆ XED_IFORM_XRSTOR64_MEMmxsave_DEFINED

#define XED_IFORM_XRSTOR64_MEMmxsave_DEFINED   1

◆ XED_IFORM_XRSTOR_MEMmxsave_DEFINED

#define XED_IFORM_XRSTOR_MEMmxsave_DEFINED   1

◆ XED_IFORM_XRSTORS64_MEMmxsave_DEFINED

#define XED_IFORM_XRSTORS64_MEMmxsave_DEFINED   1

◆ XED_IFORM_XRSTORS_MEMmxsave_DEFINED

#define XED_IFORM_XRSTORS_MEMmxsave_DEFINED   1

◆ XED_IFORM_XSAVE64_MEMmxsave_DEFINED

#define XED_IFORM_XSAVE64_MEMmxsave_DEFINED   1

◆ XED_IFORM_XSAVE_MEMmxsave_DEFINED

#define XED_IFORM_XSAVE_MEMmxsave_DEFINED   1

◆ XED_IFORM_XSAVEC64_MEMmxsave_DEFINED

#define XED_IFORM_XSAVEC64_MEMmxsave_DEFINED   1

◆ XED_IFORM_XSAVEC_MEMmxsave_DEFINED

#define XED_IFORM_XSAVEC_MEMmxsave_DEFINED   1

◆ XED_IFORM_XSAVEOPT64_MEMmxsave_DEFINED

#define XED_IFORM_XSAVEOPT64_MEMmxsave_DEFINED   1

◆ XED_IFORM_XSAVEOPT_MEMmxsave_DEFINED

#define XED_IFORM_XSAVEOPT_MEMmxsave_DEFINED   1

◆ XED_IFORM_XSAVES64_MEMmxsave_DEFINED

#define XED_IFORM_XSAVES64_MEMmxsave_DEFINED   1

◆ XED_IFORM_XSAVES_MEMmxsave_DEFINED

#define XED_IFORM_XSAVES_MEMmxsave_DEFINED   1

◆ XED_IFORM_XSETBV_DEFINED

#define XED_IFORM_XSETBV_DEFINED   1

◆ XED_IFORM_XSTORE_DEFINED

#define XED_IFORM_XSTORE_DEFINED   1

◆ XED_IFORM_XSUSLDTRK_DEFINED

#define XED_IFORM_XSUSLDTRK_DEFINED   1

◆ XED_IFORM_XTEST_DEFINED

#define XED_IFORM_XTEST_DEFINED   1

Enumeration Type Documentation

◆ xed_iform_enum_t

Enumerator
XED_IFORM_INVALID 
XED_IFORM_AAA 
XED_IFORM_AAD_IMMb 
XED_IFORM_AADD_MEM32_GPR32 
XED_IFORM_AADD_MEM64_GPR64 
XED_IFORM_AADD_MEMi32_GPR32i32_APX 
XED_IFORM_AADD_MEMi64_GPR64i64_APX 
XED_IFORM_AAM_IMMb 
XED_IFORM_AAND_MEM32_GPR32 
XED_IFORM_AAND_MEM64_GPR64 
XED_IFORM_AAND_MEMi32_GPR32i32_APX 
XED_IFORM_AAND_MEMi64_GPR64i64_APX 
XED_IFORM_AAS 
XED_IFORM_ADC_AL_IMMb 
XED_IFORM_ADC_GPR8_GPR8_10 
XED_IFORM_ADC_GPR8_GPR8_12 
XED_IFORM_ADC_GPR8_IMMb_80r2 
XED_IFORM_ADC_GPR8_IMMb_82r2 
XED_IFORM_ADC_GPR8_MEMb 
XED_IFORM_ADC_GPR8i8_GPR8i8_APX 
XED_IFORM_ADC_GPR8i8_GPR8i8_GPR8i8_APX 
XED_IFORM_ADC_GPR8i8_GPR8i8_IMM8_APX 
XED_IFORM_ADC_GPR8i8_GPR8i8_MEMi8_APX 
XED_IFORM_ADC_GPR8i8_IMM8_APX 
XED_IFORM_ADC_GPR8i8_MEMi8_APX 
XED_IFORM_ADC_GPR8i8_MEMi8_GPR8i8_APX 
XED_IFORM_ADC_GPR8i8_MEMi8_IMM8_APX 
XED_IFORM_ADC_GPRv_GPRv_11 
XED_IFORM_ADC_GPRv_GPRv_13 
XED_IFORM_ADC_GPRv_GPRv_APX 
XED_IFORM_ADC_GPRv_GPRv_GPRv_APX 
XED_IFORM_ADC_GPRv_GPRv_IMM8_APX 
XED_IFORM_ADC_GPRv_GPRv_IMMz_APX 
XED_IFORM_ADC_GPRv_GPRv_MEMv_APX 
XED_IFORM_ADC_GPRv_IMM8_APX 
XED_IFORM_ADC_GPRv_IMMb 
XED_IFORM_ADC_GPRv_IMMz 
XED_IFORM_ADC_GPRv_IMMz_APX 
XED_IFORM_ADC_GPRv_MEMv 
XED_IFORM_ADC_GPRv_MEMv_APX 
XED_IFORM_ADC_GPRv_MEMv_GPRv_APX 
XED_IFORM_ADC_GPRv_MEMv_IMM8_APX 
XED_IFORM_ADC_GPRv_MEMv_IMMz_APX 
XED_IFORM_ADC_MEMb_GPR8 
XED_IFORM_ADC_MEMb_IMMb_80r2 
XED_IFORM_ADC_MEMb_IMMb_82r2 
XED_IFORM_ADC_MEMi8_GPR8i8_APX 
XED_IFORM_ADC_MEMi8_IMM8_APX 
XED_IFORM_ADC_MEMv_GPRv 
XED_IFORM_ADC_MEMv_GPRv_APX 
XED_IFORM_ADC_MEMv_IMM8_APX 
XED_IFORM_ADC_MEMv_IMMb 
XED_IFORM_ADC_MEMv_IMMz 
XED_IFORM_ADC_MEMv_IMMz_APX 
XED_IFORM_ADC_OrAX_IMMz 
XED_IFORM_ADCX_GPR32d_GPR32d 
XED_IFORM_ADCX_GPR32d_MEMd 
XED_IFORM_ADCX_GPR32i32_GPR32i32_APX 
XED_IFORM_ADCX_GPR32i32_GPR32i32_GPR32i32_APX 
XED_IFORM_ADCX_GPR32i32_GPR32i32_MEMi32_APX 
XED_IFORM_ADCX_GPR32i32_MEMi32_APX 
XED_IFORM_ADCX_GPR64i64_GPR64i64_APX 
XED_IFORM_ADCX_GPR64i64_GPR64i64_GPR64i64_APX 
XED_IFORM_ADCX_GPR64i64_GPR64i64_MEMi64_APX 
XED_IFORM_ADCX_GPR64i64_MEMi64_APX 
XED_IFORM_ADCX_GPR64q_GPR64q 
XED_IFORM_ADCX_GPR64q_MEMq 
XED_IFORM_ADC_LOCK_MEMb_GPR8 
XED_IFORM_ADC_LOCK_MEMb_IMMb_80r2 
XED_IFORM_ADC_LOCK_MEMb_IMMb_82r2 
XED_IFORM_ADC_LOCK_MEMv_GPRv 
XED_IFORM_ADC_LOCK_MEMv_IMMb 
XED_IFORM_ADC_LOCK_MEMv_IMMz 
XED_IFORM_ADD_AL_IMMb 
XED_IFORM_ADD_GPR8_GPR8_00 
XED_IFORM_ADD_GPR8_GPR8_02 
XED_IFORM_ADD_GPR8_IMMb_80r0 
XED_IFORM_ADD_GPR8_IMMb_82r0 
XED_IFORM_ADD_GPR8_MEMb 
XED_IFORM_ADD_GPR8i8_GPR8i8_APX 
XED_IFORM_ADD_GPR8i8_GPR8i8_GPR8i8_APX 
XED_IFORM_ADD_GPR8i8_GPR8i8_IMM8_APX 
XED_IFORM_ADD_GPR8i8_GPR8i8_MEMi8_APX 
XED_IFORM_ADD_GPR8i8_IMM8_APX 
XED_IFORM_ADD_GPR8i8_MEMi8_APX 
XED_IFORM_ADD_GPR8i8_MEMi8_GPR8i8_APX 
XED_IFORM_ADD_GPR8i8_MEMi8_IMM8_APX 
XED_IFORM_ADD_GPRv_GPRv_01 
XED_IFORM_ADD_GPRv_GPRv_03 
XED_IFORM_ADD_GPRv_GPRv_APX 
XED_IFORM_ADD_GPRv_GPRv_GPRv_APX 
XED_IFORM_ADD_GPRv_GPRv_IMM8_APX 
XED_IFORM_ADD_GPRv_GPRv_IMMz_APX 
XED_IFORM_ADD_GPRv_GPRv_MEMv_APX 
XED_IFORM_ADD_GPRv_IMM8_APX 
XED_IFORM_ADD_GPRv_IMMb 
XED_IFORM_ADD_GPRv_IMMz 
XED_IFORM_ADD_GPRv_IMMz_APX 
XED_IFORM_ADD_GPRv_MEMv 
XED_IFORM_ADD_GPRv_MEMv_APX 
XED_IFORM_ADD_GPRv_MEMv_GPRv_APX 
XED_IFORM_ADD_GPRv_MEMv_IMM8_APX 
XED_IFORM_ADD_GPRv_MEMv_IMMz_APX 
XED_IFORM_ADD_MEMb_GPR8 
XED_IFORM_ADD_MEMb_IMMb_80r0 
XED_IFORM_ADD_MEMb_IMMb_82r0 
XED_IFORM_ADD_MEMi8_GPR8i8_APX 
XED_IFORM_ADD_MEMi8_IMM8_APX 
XED_IFORM_ADD_MEMv_GPRv 
XED_IFORM_ADD_MEMv_GPRv_APX 
XED_IFORM_ADD_MEMv_IMM8_APX 
XED_IFORM_ADD_MEMv_IMMb 
XED_IFORM_ADD_MEMv_IMMz 
XED_IFORM_ADD_MEMv_IMMz_APX 
XED_IFORM_ADD_OrAX_IMMz 
XED_IFORM_ADDPD_XMMpd_MEMpd 
XED_IFORM_ADDPD_XMMpd_XMMpd 
XED_IFORM_ADDPS_XMMps_MEMps 
XED_IFORM_ADDPS_XMMps_XMMps 
XED_IFORM_ADDSD_XMMsd_MEMsd 
XED_IFORM_ADDSD_XMMsd_XMMsd 
XED_IFORM_ADDSS_XMMss_MEMss 
XED_IFORM_ADDSS_XMMss_XMMss 
XED_IFORM_ADDSUBPD_XMMpd_MEMpd 
XED_IFORM_ADDSUBPD_XMMpd_XMMpd 
XED_IFORM_ADDSUBPS_XMMps_MEMps 
XED_IFORM_ADDSUBPS_XMMps_XMMps 
XED_IFORM_ADD_LOCK_MEMb_GPR8 
XED_IFORM_ADD_LOCK_MEMb_IMMb_80r0 
XED_IFORM_ADD_LOCK_MEMb_IMMb_82r0 
XED_IFORM_ADD_LOCK_MEMv_GPRv 
XED_IFORM_ADD_LOCK_MEMv_IMMb 
XED_IFORM_ADD_LOCK_MEMv_IMMz 
XED_IFORM_ADOX_GPR32d_GPR32d 
XED_IFORM_ADOX_GPR32d_MEMd 
XED_IFORM_ADOX_GPR32i32_GPR32i32_APX 
XED_IFORM_ADOX_GPR32i32_GPR32i32_GPR32i32_APX 
XED_IFORM_ADOX_GPR32i32_GPR32i32_MEMi32_APX 
XED_IFORM_ADOX_GPR32i32_MEMi32_APX 
XED_IFORM_ADOX_GPR64i64_GPR64i64_APX 
XED_IFORM_ADOX_GPR64i64_GPR64i64_GPR64i64_APX 
XED_IFORM_ADOX_GPR64i64_GPR64i64_MEMi64_APX 
XED_IFORM_ADOX_GPR64i64_MEMi64_APX 
XED_IFORM_ADOX_GPR64q_GPR64q 
XED_IFORM_ADOX_GPR64q_MEMq 
XED_IFORM_AESDEC_XMMdq_MEMdq 
XED_IFORM_AESDEC_XMMdq_XMMdq 
XED_IFORM_AESDEC128KL_XMMu8_MEMu8 
XED_IFORM_AESDEC256KL_XMMu8_MEMu8 
XED_IFORM_AESDECLAST_XMMdq_MEMdq 
XED_IFORM_AESDECLAST_XMMdq_XMMdq 
XED_IFORM_AESDECWIDE128KL_MEMu8 
XED_IFORM_AESDECWIDE256KL_MEMu8 
XED_IFORM_AESENC_XMMdq_MEMdq 
XED_IFORM_AESENC_XMMdq_XMMdq 
XED_IFORM_AESENC128KL_XMMu8_MEMu8 
XED_IFORM_AESENC256KL_XMMu8_MEMu8 
XED_IFORM_AESENCLAST_XMMdq_MEMdq 
XED_IFORM_AESENCLAST_XMMdq_XMMdq 
XED_IFORM_AESENCWIDE128KL_MEMu8 
XED_IFORM_AESENCWIDE256KL_MEMu8 
XED_IFORM_AESIMC_XMMdq_MEMdq 
XED_IFORM_AESIMC_XMMdq_XMMdq 
XED_IFORM_AESKEYGENASSIST_XMMdq_MEMdq_IMMb 
XED_IFORM_AESKEYGENASSIST_XMMdq_XMMdq_IMMb 
XED_IFORM_AND_AL_IMMb 
XED_IFORM_AND_GPR8_GPR8_20 
XED_IFORM_AND_GPR8_GPR8_22 
XED_IFORM_AND_GPR8_IMMb_80r4 
XED_IFORM_AND_GPR8_IMMb_82r4 
XED_IFORM_AND_GPR8_MEMb 
XED_IFORM_AND_GPR8i8_GPR8i8_APX 
XED_IFORM_AND_GPR8i8_GPR8i8_GPR8i8_APX 
XED_IFORM_AND_GPR8i8_GPR8i8_IMM8_APX 
XED_IFORM_AND_GPR8i8_GPR8i8_MEMi8_APX 
XED_IFORM_AND_GPR8i8_IMM8_APX 
XED_IFORM_AND_GPR8i8_MEMi8_APX 
XED_IFORM_AND_GPR8i8_MEMi8_GPR8i8_APX 
XED_IFORM_AND_GPR8i8_MEMi8_IMM8_APX 
XED_IFORM_AND_GPRv_GPRv_21 
XED_IFORM_AND_GPRv_GPRv_23 
XED_IFORM_AND_GPRv_GPRv_APX 
XED_IFORM_AND_GPRv_GPRv_GPRv_APX 
XED_IFORM_AND_GPRv_GPRv_IMM8_APX 
XED_IFORM_AND_GPRv_GPRv_IMMz_APX 
XED_IFORM_AND_GPRv_GPRv_MEMv_APX 
XED_IFORM_AND_GPRv_IMM8_APX 
XED_IFORM_AND_GPRv_IMMb 
XED_IFORM_AND_GPRv_IMMz 
XED_IFORM_AND_GPRv_IMMz_APX 
XED_IFORM_AND_GPRv_MEMv 
XED_IFORM_AND_GPRv_MEMv_APX 
XED_IFORM_AND_GPRv_MEMv_GPRv_APX 
XED_IFORM_AND_GPRv_MEMv_IMM8_APX 
XED_IFORM_AND_GPRv_MEMv_IMMz_APX 
XED_IFORM_AND_MEMb_GPR8 
XED_IFORM_AND_MEMb_IMMb_80r4 
XED_IFORM_AND_MEMb_IMMb_82r4 
XED_IFORM_AND_MEMi8_GPR8i8_APX 
XED_IFORM_AND_MEMi8_IMM8_APX 
XED_IFORM_AND_MEMv_GPRv 
XED_IFORM_AND_MEMv_GPRv_APX 
XED_IFORM_AND_MEMv_IMM8_APX 
XED_IFORM_AND_MEMv_IMMb 
XED_IFORM_AND_MEMv_IMMz 
XED_IFORM_AND_MEMv_IMMz_APX 
XED_IFORM_AND_OrAX_IMMz 
XED_IFORM_ANDN_GPR32d_GPR32d_GPR32d 
XED_IFORM_ANDN_GPR32d_GPR32d_MEMd 
XED_IFORM_ANDN_GPR32i32_GPR32i32_GPR32i32_APX 
XED_IFORM_ANDN_GPR32i32_GPR32i32_MEMi32_APX 
XED_IFORM_ANDN_GPR64i64_GPR64i64_GPR64i64_APX 
XED_IFORM_ANDN_GPR64i64_GPR64i64_MEMi64_APX 
XED_IFORM_ANDN_GPR64q_GPR64q_GPR64q 
XED_IFORM_ANDN_GPR64q_GPR64q_MEMq 
XED_IFORM_ANDNPD_XMMxuq_MEMxuq 
XED_IFORM_ANDNPD_XMMxuq_XMMxuq 
XED_IFORM_ANDNPS_XMMxud_MEMxud 
XED_IFORM_ANDNPS_XMMxud_XMMxud 
XED_IFORM_ANDPD_XMMxuq_MEMxuq 
XED_IFORM_ANDPD_XMMxuq_XMMxuq 
XED_IFORM_ANDPS_XMMxud_MEMxud 
XED_IFORM_ANDPS_XMMxud_XMMxud 
XED_IFORM_AND_LOCK_MEMb_GPR8 
XED_IFORM_AND_LOCK_MEMb_IMMb_80r4 
XED_IFORM_AND_LOCK_MEMb_IMMb_82r4 
XED_IFORM_AND_LOCK_MEMv_GPRv 
XED_IFORM_AND_LOCK_MEMv_IMMb 
XED_IFORM_AND_LOCK_MEMv_IMMz 
XED_IFORM_AOR_MEM32_GPR32 
XED_IFORM_AOR_MEM64_GPR64 
XED_IFORM_AOR_MEMi32_GPR32i32_APX 
XED_IFORM_AOR_MEMi64_GPR64i64_APX 
XED_IFORM_ARPL_GPR16_GPR16 
XED_IFORM_ARPL_MEMw_GPR16 
XED_IFORM_AXOR_MEM32_GPR32 
XED_IFORM_AXOR_MEM64_GPR64 
XED_IFORM_AXOR_MEMi32_GPR32i32_APX 
XED_IFORM_AXOR_MEMi64_GPR64i64_APX 
XED_IFORM_BEXTR_GPR32d_GPR32d_GPR32d 
XED_IFORM_BEXTR_GPR32d_MEMd_GPR32d 
XED_IFORM_BEXTR_GPR32i32_GPR32i32_GPR32i32_APX 
XED_IFORM_BEXTR_GPR32i32_MEMi32_GPR32i32_APX 
XED_IFORM_BEXTR_GPR64i64_GPR64i64_GPR64i64_APX 
XED_IFORM_BEXTR_GPR64i64_MEMi64_GPR64i64_APX 
XED_IFORM_BEXTR_GPR64q_GPR64q_GPR64q 
XED_IFORM_BEXTR_GPR64q_MEMq_GPR64q 
XED_IFORM_BEXTR_XOP_GPR32d_GPR32d_IMMd 
XED_IFORM_BEXTR_XOP_GPR32d_MEMd_IMMd 
XED_IFORM_BEXTR_XOP_GPRyy_GPRyy_IMMd 
XED_IFORM_BEXTR_XOP_GPRyy_MEMy_IMMd 
XED_IFORM_BLCFILL_GPR32d_GPR32d 
XED_IFORM_BLCFILL_GPR32d_MEMd 
XED_IFORM_BLCFILL_GPRyy_GPRyy 
XED_IFORM_BLCFILL_GPRyy_MEMy 
XED_IFORM_BLCI_GPR32d_GPR32d 
XED_IFORM_BLCI_GPR32d_MEMd 
XED_IFORM_BLCI_GPRyy_GPRyy 
XED_IFORM_BLCI_GPRyy_MEMy 
XED_IFORM_BLCIC_GPR32d_GPR32d 
XED_IFORM_BLCIC_GPR32d_MEMd 
XED_IFORM_BLCIC_GPRyy_GPRyy 
XED_IFORM_BLCIC_GPRyy_MEMy 
XED_IFORM_BLCMSK_GPR32d_GPR32d 
XED_IFORM_BLCMSK_GPR32d_MEMd 
XED_IFORM_BLCMSK_GPRyy_GPRyy 
XED_IFORM_BLCMSK_GPRyy_MEMy 
XED_IFORM_BLCS_GPR32d_GPR32d 
XED_IFORM_BLCS_GPR32d_MEMd 
XED_IFORM_BLCS_GPRyy_GPRyy 
XED_IFORM_BLCS_GPRyy_MEMy 
XED_IFORM_BLENDPD_XMMdq_MEMdq_IMMb 
XED_IFORM_BLENDPD_XMMdq_XMMdq_IMMb 
XED_IFORM_BLENDPS_XMMdq_MEMdq_IMMb 
XED_IFORM_BLENDPS_XMMdq_XMMdq_IMMb 
XED_IFORM_BLENDVPD_XMMdq_MEMdq 
XED_IFORM_BLENDVPD_XMMdq_XMMdq 
XED_IFORM_BLENDVPS_XMMdq_MEMdq 
XED_IFORM_BLENDVPS_XMMdq_XMMdq 
XED_IFORM_BLSFILL_GPR32d_GPR32d 
XED_IFORM_BLSFILL_GPR32d_MEMd 
XED_IFORM_BLSFILL_GPRyy_GPRyy 
XED_IFORM_BLSFILL_GPRyy_MEMy 
XED_IFORM_BLSI_GPR32d_GPR32d 
XED_IFORM_BLSI_GPR32d_MEMd 
XED_IFORM_BLSI_GPR32i32_GPR32i32_APX 
XED_IFORM_BLSI_GPR32i32_MEMi32_APX 
XED_IFORM_BLSI_GPR64i64_GPR64i64_APX 
XED_IFORM_BLSI_GPR64i64_MEMi64_APX 
XED_IFORM_BLSI_GPR64q_GPR64q 
XED_IFORM_BLSI_GPR64q_MEMq 
XED_IFORM_BLSIC_GPR32d_GPR32d 
XED_IFORM_BLSIC_GPR32d_MEMd 
XED_IFORM_BLSIC_GPRyy_GPRyy 
XED_IFORM_BLSIC_GPRyy_MEMy 
XED_IFORM_BLSMSK_GPR32d_GPR32d 
XED_IFORM_BLSMSK_GPR32d_MEMd 
XED_IFORM_BLSMSK_GPR32i32_GPR32i32_APX 
XED_IFORM_BLSMSK_GPR32i32_MEMi32_APX 
XED_IFORM_BLSMSK_GPR64i64_GPR64i64_APX 
XED_IFORM_BLSMSK_GPR64i64_MEMi64_APX 
XED_IFORM_BLSMSK_GPR64q_GPR64q 
XED_IFORM_BLSMSK_GPR64q_MEMq 
XED_IFORM_BLSR_GPR32d_GPR32d 
XED_IFORM_BLSR_GPR32d_MEMd 
XED_IFORM_BLSR_GPR32i32_GPR32i32_APX 
XED_IFORM_BLSR_GPR32i32_MEMi32_APX 
XED_IFORM_BLSR_GPR64i64_GPR64i64_APX 
XED_IFORM_BLSR_GPR64i64_MEMi64_APX 
XED_IFORM_BLSR_GPR64q_GPR64q 
XED_IFORM_BLSR_GPR64q_MEMq 
XED_IFORM_BNDCL_BND_AGEN 
XED_IFORM_BNDCL_BND_GPR32 
XED_IFORM_BNDCL_BND_GPR64 
XED_IFORM_BNDCN_BND_AGEN 
XED_IFORM_BNDCN_BND_GPR32 
XED_IFORM_BNDCN_BND_GPR64 
XED_IFORM_BNDCU_BND_AGEN 
XED_IFORM_BNDCU_BND_GPR32 
XED_IFORM_BNDCU_BND_GPR64 
XED_IFORM_BNDLDX_BND_MEMbnd32 
XED_IFORM_BNDLDX_BND_MEMbnd64 
XED_IFORM_BNDMK_BND_AGEN 
XED_IFORM_BNDMOV_BND_BND 
XED_IFORM_BNDMOV_BND_MEMdq 
XED_IFORM_BNDMOV_BND_MEMq 
XED_IFORM_BNDMOV_MEMdq_BND 
XED_IFORM_BNDMOV_MEMq_BND 
XED_IFORM_BNDSTX_MEMbnd32_BND 
XED_IFORM_BNDSTX_MEMbnd64_BND 
XED_IFORM_BOUND_GPR16_MEMa16 
XED_IFORM_BOUND_GPR32_MEMa32 
XED_IFORM_BSF_GPRv_GPRv 
XED_IFORM_BSF_GPRv_MEMv 
XED_IFORM_BSR_GPRv_GPRv 
XED_IFORM_BSR_GPRv_MEMv 
XED_IFORM_BSWAP_GPRv 
XED_IFORM_BT_GPRv_GPRv 
XED_IFORM_BT_GPRv_IMMb 
XED_IFORM_BT_MEMv_GPRv 
XED_IFORM_BT_MEMv_IMMb 
XED_IFORM_BTC_GPRv_GPRv 
XED_IFORM_BTC_GPRv_IMMb 
XED_IFORM_BTC_MEMv_GPRv 
XED_IFORM_BTC_MEMv_IMMb 
XED_IFORM_BTC_LOCK_MEMv_GPRv 
XED_IFORM_BTC_LOCK_MEMv_IMMb 
XED_IFORM_BTR_GPRv_GPRv 
XED_IFORM_BTR_GPRv_IMMb 
XED_IFORM_BTR_MEMv_GPRv 
XED_IFORM_BTR_MEMv_IMMb 
XED_IFORM_BTR_LOCK_MEMv_GPRv 
XED_IFORM_BTR_LOCK_MEMv_IMMb 
XED_IFORM_BTS_GPRv_GPRv 
XED_IFORM_BTS_GPRv_IMMb 
XED_IFORM_BTS_MEMv_GPRv 
XED_IFORM_BTS_MEMv_IMMb 
XED_IFORM_BTS_LOCK_MEMv_GPRv 
XED_IFORM_BTS_LOCK_MEMv_IMMb 
XED_IFORM_BZHI_GPR32d_GPR32d_GPR32d 
XED_IFORM_BZHI_GPR32d_MEMd_GPR32d 
XED_IFORM_BZHI_GPR32i32_GPR32i32_GPR32i32_APX 
XED_IFORM_BZHI_GPR32i32_MEMi32_GPR32i32_APX 
XED_IFORM_BZHI_GPR64i64_GPR64i64_GPR64i64_APX 
XED_IFORM_BZHI_GPR64i64_MEMi64_GPR64i64_APX 
XED_IFORM_BZHI_GPR64q_GPR64q_GPR64q 
XED_IFORM_BZHI_GPR64q_MEMq_GPR64q 
XED_IFORM_CALL_FAR_MEMp2 
XED_IFORM_CALL_FAR_PTRp_IMMw 
XED_IFORM_CALL_NEAR_GPRv 
XED_IFORM_CALL_NEAR_MEMv 
XED_IFORM_CALL_NEAR_RELBRd 
XED_IFORM_CALL_NEAR_RELBRz 
XED_IFORM_CBW 
XED_IFORM_CCMPB_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CCMPB_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CCMPB_GPR8i8_MEMi8_DFV_APX 
XED_IFORM_CCMPB_GPRv_GPRv_DFV_APX 
XED_IFORM_CCMPB_GPRv_IMM8_DFV_APX 
XED_IFORM_CCMPB_GPRv_IMMz_DFV_APX 
XED_IFORM_CCMPB_GPRv_MEMv_DFV_APX 
XED_IFORM_CCMPB_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CCMPB_MEMi8_IMM8_DFV_APX 
XED_IFORM_CCMPB_MEMv_GPRv_DFV_APX 
XED_IFORM_CCMPB_MEMv_IMM8_DFV_APX 
XED_IFORM_CCMPB_MEMv_IMMz_DFV_APX 
XED_IFORM_CCMPBE_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CCMPBE_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CCMPBE_GPR8i8_MEMi8_DFV_APX 
XED_IFORM_CCMPBE_GPRv_GPRv_DFV_APX 
XED_IFORM_CCMPBE_GPRv_IMM8_DFV_APX 
XED_IFORM_CCMPBE_GPRv_IMMz_DFV_APX 
XED_IFORM_CCMPBE_GPRv_MEMv_DFV_APX 
XED_IFORM_CCMPBE_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CCMPBE_MEMi8_IMM8_DFV_APX 
XED_IFORM_CCMPBE_MEMv_GPRv_DFV_APX 
XED_IFORM_CCMPBE_MEMv_IMM8_DFV_APX 
XED_IFORM_CCMPBE_MEMv_IMMz_DFV_APX 
XED_IFORM_CCMPF_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CCMPF_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CCMPF_GPR8i8_MEMi8_DFV_APX 
XED_IFORM_CCMPF_GPRv_GPRv_DFV_APX 
XED_IFORM_CCMPF_GPRv_IMM8_DFV_APX 
XED_IFORM_CCMPF_GPRv_IMMz_DFV_APX 
XED_IFORM_CCMPF_GPRv_MEMv_DFV_APX 
XED_IFORM_CCMPF_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CCMPF_MEMi8_IMM8_DFV_APX 
XED_IFORM_CCMPF_MEMv_GPRv_DFV_APX 
XED_IFORM_CCMPF_MEMv_IMM8_DFV_APX 
XED_IFORM_CCMPF_MEMv_IMMz_DFV_APX 
XED_IFORM_CCMPL_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CCMPL_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CCMPL_GPR8i8_MEMi8_DFV_APX 
XED_IFORM_CCMPL_GPRv_GPRv_DFV_APX 
XED_IFORM_CCMPL_GPRv_IMM8_DFV_APX 
XED_IFORM_CCMPL_GPRv_IMMz_DFV_APX 
XED_IFORM_CCMPL_GPRv_MEMv_DFV_APX 
XED_IFORM_CCMPL_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CCMPL_MEMi8_IMM8_DFV_APX 
XED_IFORM_CCMPL_MEMv_GPRv_DFV_APX 
XED_IFORM_CCMPL_MEMv_IMM8_DFV_APX 
XED_IFORM_CCMPL_MEMv_IMMz_DFV_APX 
XED_IFORM_CCMPLE_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CCMPLE_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CCMPLE_GPR8i8_MEMi8_DFV_APX 
XED_IFORM_CCMPLE_GPRv_GPRv_DFV_APX 
XED_IFORM_CCMPLE_GPRv_IMM8_DFV_APX 
XED_IFORM_CCMPLE_GPRv_IMMz_DFV_APX 
XED_IFORM_CCMPLE_GPRv_MEMv_DFV_APX 
XED_IFORM_CCMPLE_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CCMPLE_MEMi8_IMM8_DFV_APX 
XED_IFORM_CCMPLE_MEMv_GPRv_DFV_APX 
XED_IFORM_CCMPLE_MEMv_IMM8_DFV_APX 
XED_IFORM_CCMPLE_MEMv_IMMz_DFV_APX 
XED_IFORM_CCMPNB_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CCMPNB_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CCMPNB_GPR8i8_MEMi8_DFV_APX 
XED_IFORM_CCMPNB_GPRv_GPRv_DFV_APX 
XED_IFORM_CCMPNB_GPRv_IMM8_DFV_APX 
XED_IFORM_CCMPNB_GPRv_IMMz_DFV_APX 
XED_IFORM_CCMPNB_GPRv_MEMv_DFV_APX 
XED_IFORM_CCMPNB_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CCMPNB_MEMi8_IMM8_DFV_APX 
XED_IFORM_CCMPNB_MEMv_GPRv_DFV_APX 
XED_IFORM_CCMPNB_MEMv_IMM8_DFV_APX 
XED_IFORM_CCMPNB_MEMv_IMMz_DFV_APX 
XED_IFORM_CCMPNBE_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CCMPNBE_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CCMPNBE_GPR8i8_MEMi8_DFV_APX 
XED_IFORM_CCMPNBE_GPRv_GPRv_DFV_APX 
XED_IFORM_CCMPNBE_GPRv_IMM8_DFV_APX 
XED_IFORM_CCMPNBE_GPRv_IMMz_DFV_APX 
XED_IFORM_CCMPNBE_GPRv_MEMv_DFV_APX 
XED_IFORM_CCMPNBE_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CCMPNBE_MEMi8_IMM8_DFV_APX 
XED_IFORM_CCMPNBE_MEMv_GPRv_DFV_APX 
XED_IFORM_CCMPNBE_MEMv_IMM8_DFV_APX 
XED_IFORM_CCMPNBE_MEMv_IMMz_DFV_APX 
XED_IFORM_CCMPNL_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CCMPNL_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CCMPNL_GPR8i8_MEMi8_DFV_APX 
XED_IFORM_CCMPNL_GPRv_GPRv_DFV_APX 
XED_IFORM_CCMPNL_GPRv_IMM8_DFV_APX 
XED_IFORM_CCMPNL_GPRv_IMMz_DFV_APX 
XED_IFORM_CCMPNL_GPRv_MEMv_DFV_APX 
XED_IFORM_CCMPNL_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CCMPNL_MEMi8_IMM8_DFV_APX 
XED_IFORM_CCMPNL_MEMv_GPRv_DFV_APX 
XED_IFORM_CCMPNL_MEMv_IMM8_DFV_APX 
XED_IFORM_CCMPNL_MEMv_IMMz_DFV_APX 
XED_IFORM_CCMPNLE_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CCMPNLE_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CCMPNLE_GPR8i8_MEMi8_DFV_APX 
XED_IFORM_CCMPNLE_GPRv_GPRv_DFV_APX 
XED_IFORM_CCMPNLE_GPRv_IMM8_DFV_APX 
XED_IFORM_CCMPNLE_GPRv_IMMz_DFV_APX 
XED_IFORM_CCMPNLE_GPRv_MEMv_DFV_APX 
XED_IFORM_CCMPNLE_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CCMPNLE_MEMi8_IMM8_DFV_APX 
XED_IFORM_CCMPNLE_MEMv_GPRv_DFV_APX 
XED_IFORM_CCMPNLE_MEMv_IMM8_DFV_APX 
XED_IFORM_CCMPNLE_MEMv_IMMz_DFV_APX 
XED_IFORM_CCMPNO_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CCMPNO_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CCMPNO_GPR8i8_MEMi8_DFV_APX 
XED_IFORM_CCMPNO_GPRv_GPRv_DFV_APX 
XED_IFORM_CCMPNO_GPRv_IMM8_DFV_APX 
XED_IFORM_CCMPNO_GPRv_IMMz_DFV_APX 
XED_IFORM_CCMPNO_GPRv_MEMv_DFV_APX 
XED_IFORM_CCMPNO_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CCMPNO_MEMi8_IMM8_DFV_APX 
XED_IFORM_CCMPNO_MEMv_GPRv_DFV_APX 
XED_IFORM_CCMPNO_MEMv_IMM8_DFV_APX 
XED_IFORM_CCMPNO_MEMv_IMMz_DFV_APX 
XED_IFORM_CCMPNS_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CCMPNS_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CCMPNS_GPR8i8_MEMi8_DFV_APX 
XED_IFORM_CCMPNS_GPRv_GPRv_DFV_APX 
XED_IFORM_CCMPNS_GPRv_IMM8_DFV_APX 
XED_IFORM_CCMPNS_GPRv_IMMz_DFV_APX 
XED_IFORM_CCMPNS_GPRv_MEMv_DFV_APX 
XED_IFORM_CCMPNS_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CCMPNS_MEMi8_IMM8_DFV_APX 
XED_IFORM_CCMPNS_MEMv_GPRv_DFV_APX 
XED_IFORM_CCMPNS_MEMv_IMM8_DFV_APX 
XED_IFORM_CCMPNS_MEMv_IMMz_DFV_APX 
XED_IFORM_CCMPNZ_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CCMPNZ_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CCMPNZ_GPR8i8_MEMi8_DFV_APX 
XED_IFORM_CCMPNZ_GPRv_GPRv_DFV_APX 
XED_IFORM_CCMPNZ_GPRv_IMM8_DFV_APX 
XED_IFORM_CCMPNZ_GPRv_IMMz_DFV_APX 
XED_IFORM_CCMPNZ_GPRv_MEMv_DFV_APX 
XED_IFORM_CCMPNZ_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CCMPNZ_MEMi8_IMM8_DFV_APX 
XED_IFORM_CCMPNZ_MEMv_GPRv_DFV_APX 
XED_IFORM_CCMPNZ_MEMv_IMM8_DFV_APX 
XED_IFORM_CCMPNZ_MEMv_IMMz_DFV_APX 
XED_IFORM_CCMPO_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CCMPO_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CCMPO_GPR8i8_MEMi8_DFV_APX 
XED_IFORM_CCMPO_GPRv_GPRv_DFV_APX 
XED_IFORM_CCMPO_GPRv_IMM8_DFV_APX 
XED_IFORM_CCMPO_GPRv_IMMz_DFV_APX 
XED_IFORM_CCMPO_GPRv_MEMv_DFV_APX 
XED_IFORM_CCMPO_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CCMPO_MEMi8_IMM8_DFV_APX 
XED_IFORM_CCMPO_MEMv_GPRv_DFV_APX 
XED_IFORM_CCMPO_MEMv_IMM8_DFV_APX 
XED_IFORM_CCMPO_MEMv_IMMz_DFV_APX 
XED_IFORM_CCMPS_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CCMPS_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CCMPS_GPR8i8_MEMi8_DFV_APX 
XED_IFORM_CCMPS_GPRv_GPRv_DFV_APX 
XED_IFORM_CCMPS_GPRv_IMM8_DFV_APX 
XED_IFORM_CCMPS_GPRv_IMMz_DFV_APX 
XED_IFORM_CCMPS_GPRv_MEMv_DFV_APX 
XED_IFORM_CCMPS_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CCMPS_MEMi8_IMM8_DFV_APX 
XED_IFORM_CCMPS_MEMv_GPRv_DFV_APX 
XED_IFORM_CCMPS_MEMv_IMM8_DFV_APX 
XED_IFORM_CCMPS_MEMv_IMMz_DFV_APX 
XED_IFORM_CCMPT_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CCMPT_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CCMPT_GPR8i8_MEMi8_DFV_APX 
XED_IFORM_CCMPT_GPRv_GPRv_DFV_APX 
XED_IFORM_CCMPT_GPRv_IMM8_DFV_APX 
XED_IFORM_CCMPT_GPRv_IMMz_DFV_APX 
XED_IFORM_CCMPT_GPRv_MEMv_DFV_APX 
XED_IFORM_CCMPT_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CCMPT_MEMi8_IMM8_DFV_APX 
XED_IFORM_CCMPT_MEMv_GPRv_DFV_APX 
XED_IFORM_CCMPT_MEMv_IMM8_DFV_APX 
XED_IFORM_CCMPT_MEMv_IMMz_DFV_APX 
XED_IFORM_CCMPZ_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CCMPZ_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CCMPZ_GPR8i8_MEMi8_DFV_APX 
XED_IFORM_CCMPZ_GPRv_GPRv_DFV_APX 
XED_IFORM_CCMPZ_GPRv_IMM8_DFV_APX 
XED_IFORM_CCMPZ_GPRv_IMMz_DFV_APX 
XED_IFORM_CCMPZ_GPRv_MEMv_DFV_APX 
XED_IFORM_CCMPZ_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CCMPZ_MEMi8_IMM8_DFV_APX 
XED_IFORM_CCMPZ_MEMv_GPRv_DFV_APX 
XED_IFORM_CCMPZ_MEMv_IMM8_DFV_APX 
XED_IFORM_CCMPZ_MEMv_IMMz_DFV_APX 
XED_IFORM_CDQ 
XED_IFORM_CDQE 
XED_IFORM_CFCMOVB_GPRv_GPRv_APX 
XED_IFORM_CFCMOVB_GPRv_GPRv_GPRv_APX 
XED_IFORM_CFCMOVB_GPRv_GPRv_MEMv_APX 
XED_IFORM_CFCMOVB_GPRv_MEMv_APX 
XED_IFORM_CFCMOVB_MEMv_GPRv_APX 
XED_IFORM_CFCMOVBE_GPRv_GPRv_APX 
XED_IFORM_CFCMOVBE_GPRv_GPRv_GPRv_APX 
XED_IFORM_CFCMOVBE_GPRv_GPRv_MEMv_APX 
XED_IFORM_CFCMOVBE_GPRv_MEMv_APX 
XED_IFORM_CFCMOVBE_MEMv_GPRv_APX 
XED_IFORM_CFCMOVL_GPRv_GPRv_APX 
XED_IFORM_CFCMOVL_GPRv_GPRv_GPRv_APX 
XED_IFORM_CFCMOVL_GPRv_GPRv_MEMv_APX 
XED_IFORM_CFCMOVL_GPRv_MEMv_APX 
XED_IFORM_CFCMOVL_MEMv_GPRv_APX 
XED_IFORM_CFCMOVLE_GPRv_GPRv_APX 
XED_IFORM_CFCMOVLE_GPRv_GPRv_GPRv_APX 
XED_IFORM_CFCMOVLE_GPRv_GPRv_MEMv_APX 
XED_IFORM_CFCMOVLE_GPRv_MEMv_APX 
XED_IFORM_CFCMOVLE_MEMv_GPRv_APX 
XED_IFORM_CFCMOVNB_GPRv_GPRv_APX 
XED_IFORM_CFCMOVNB_GPRv_GPRv_GPRv_APX 
XED_IFORM_CFCMOVNB_GPRv_GPRv_MEMv_APX 
XED_IFORM_CFCMOVNB_GPRv_MEMv_APX 
XED_IFORM_CFCMOVNB_MEMv_GPRv_APX 
XED_IFORM_CFCMOVNBE_GPRv_GPRv_APX 
XED_IFORM_CFCMOVNBE_GPRv_GPRv_GPRv_APX 
XED_IFORM_CFCMOVNBE_GPRv_GPRv_MEMv_APX 
XED_IFORM_CFCMOVNBE_GPRv_MEMv_APX 
XED_IFORM_CFCMOVNBE_MEMv_GPRv_APX 
XED_IFORM_CFCMOVNL_GPRv_GPRv_APX 
XED_IFORM_CFCMOVNL_GPRv_GPRv_GPRv_APX 
XED_IFORM_CFCMOVNL_GPRv_GPRv_MEMv_APX 
XED_IFORM_CFCMOVNL_GPRv_MEMv_APX 
XED_IFORM_CFCMOVNL_MEMv_GPRv_APX 
XED_IFORM_CFCMOVNLE_GPRv_GPRv_APX 
XED_IFORM_CFCMOVNLE_GPRv_GPRv_GPRv_APX 
XED_IFORM_CFCMOVNLE_GPRv_GPRv_MEMv_APX 
XED_IFORM_CFCMOVNLE_GPRv_MEMv_APX 
XED_IFORM_CFCMOVNLE_MEMv_GPRv_APX 
XED_IFORM_CFCMOVNO_GPRv_GPRv_APX 
XED_IFORM_CFCMOVNO_GPRv_GPRv_GPRv_APX 
XED_IFORM_CFCMOVNO_GPRv_GPRv_MEMv_APX 
XED_IFORM_CFCMOVNO_GPRv_MEMv_APX 
XED_IFORM_CFCMOVNO_MEMv_GPRv_APX 
XED_IFORM_CFCMOVNP_GPRv_GPRv_APX 
XED_IFORM_CFCMOVNP_GPRv_GPRv_GPRv_APX 
XED_IFORM_CFCMOVNP_GPRv_GPRv_MEMv_APX 
XED_IFORM_CFCMOVNP_GPRv_MEMv_APX 
XED_IFORM_CFCMOVNP_MEMv_GPRv_APX 
XED_IFORM_CFCMOVNS_GPRv_GPRv_APX 
XED_IFORM_CFCMOVNS_GPRv_GPRv_GPRv_APX 
XED_IFORM_CFCMOVNS_GPRv_GPRv_MEMv_APX 
XED_IFORM_CFCMOVNS_GPRv_MEMv_APX 
XED_IFORM_CFCMOVNS_MEMv_GPRv_APX 
XED_IFORM_CFCMOVNZ_GPRv_GPRv_APX 
XED_IFORM_CFCMOVNZ_GPRv_GPRv_GPRv_APX 
XED_IFORM_CFCMOVNZ_GPRv_GPRv_MEMv_APX 
XED_IFORM_CFCMOVNZ_GPRv_MEMv_APX 
XED_IFORM_CFCMOVNZ_MEMv_GPRv_APX 
XED_IFORM_CFCMOVO_GPRv_GPRv_APX 
XED_IFORM_CFCMOVO_GPRv_GPRv_GPRv_APX 
XED_IFORM_CFCMOVO_GPRv_GPRv_MEMv_APX 
XED_IFORM_CFCMOVO_GPRv_MEMv_APX 
XED_IFORM_CFCMOVO_MEMv_GPRv_APX 
XED_IFORM_CFCMOVP_GPRv_GPRv_APX 
XED_IFORM_CFCMOVP_GPRv_GPRv_GPRv_APX 
XED_IFORM_CFCMOVP_GPRv_GPRv_MEMv_APX 
XED_IFORM_CFCMOVP_GPRv_MEMv_APX 
XED_IFORM_CFCMOVP_MEMv_GPRv_APX 
XED_IFORM_CFCMOVS_GPRv_GPRv_APX 
XED_IFORM_CFCMOVS_GPRv_GPRv_GPRv_APX 
XED_IFORM_CFCMOVS_GPRv_GPRv_MEMv_APX 
XED_IFORM_CFCMOVS_GPRv_MEMv_APX 
XED_IFORM_CFCMOVS_MEMv_GPRv_APX 
XED_IFORM_CFCMOVZ_GPRv_GPRv_APX 
XED_IFORM_CFCMOVZ_GPRv_GPRv_GPRv_APX 
XED_IFORM_CFCMOVZ_GPRv_GPRv_MEMv_APX 
XED_IFORM_CFCMOVZ_GPRv_MEMv_APX 
XED_IFORM_CFCMOVZ_MEMv_GPRv_APX 
XED_IFORM_CLAC 
XED_IFORM_CLC 
XED_IFORM_CLD 
XED_IFORM_CLDEMOTE_MEMu8 
XED_IFORM_CLFLUSH_MEMmprefetch 
XED_IFORM_CLFLUSHOPT_MEMmprefetch 
XED_IFORM_CLGI 
XED_IFORM_CLI 
XED_IFORM_CLRSSBSY_MEMu64 
XED_IFORM_CLTS 
XED_IFORM_CLUI 
XED_IFORM_CLWB_MEMmprefetch 
XED_IFORM_CLZERO 
XED_IFORM_CMC 
XED_IFORM_CMOVB_GPRv_GPRv 
XED_IFORM_CMOVB_GPRv_GPRv_GPRv_APX 
XED_IFORM_CMOVB_GPRv_GPRv_MEMv_APX 
XED_IFORM_CMOVB_GPRv_MEMv 
XED_IFORM_CMOVBE_GPRv_GPRv 
XED_IFORM_CMOVBE_GPRv_GPRv_GPRv_APX 
XED_IFORM_CMOVBE_GPRv_GPRv_MEMv_APX 
XED_IFORM_CMOVBE_GPRv_MEMv 
XED_IFORM_CMOVL_GPRv_GPRv 
XED_IFORM_CMOVL_GPRv_GPRv_GPRv_APX 
XED_IFORM_CMOVL_GPRv_GPRv_MEMv_APX 
XED_IFORM_CMOVL_GPRv_MEMv 
XED_IFORM_CMOVLE_GPRv_GPRv 
XED_IFORM_CMOVLE_GPRv_GPRv_GPRv_APX 
XED_IFORM_CMOVLE_GPRv_GPRv_MEMv_APX 
XED_IFORM_CMOVLE_GPRv_MEMv 
XED_IFORM_CMOVNB_GPRv_GPRv 
XED_IFORM_CMOVNB_GPRv_GPRv_GPRv_APX 
XED_IFORM_CMOVNB_GPRv_GPRv_MEMv_APX 
XED_IFORM_CMOVNB_GPRv_MEMv 
XED_IFORM_CMOVNBE_GPRv_GPRv 
XED_IFORM_CMOVNBE_GPRv_GPRv_GPRv_APX 
XED_IFORM_CMOVNBE_GPRv_GPRv_MEMv_APX 
XED_IFORM_CMOVNBE_GPRv_MEMv 
XED_IFORM_CMOVNL_GPRv_GPRv 
XED_IFORM_CMOVNL_GPRv_GPRv_GPRv_APX 
XED_IFORM_CMOVNL_GPRv_GPRv_MEMv_APX 
XED_IFORM_CMOVNL_GPRv_MEMv 
XED_IFORM_CMOVNLE_GPRv_GPRv 
XED_IFORM_CMOVNLE_GPRv_GPRv_GPRv_APX 
XED_IFORM_CMOVNLE_GPRv_GPRv_MEMv_APX 
XED_IFORM_CMOVNLE_GPRv_MEMv 
XED_IFORM_CMOVNO_GPRv_GPRv 
XED_IFORM_CMOVNO_GPRv_GPRv_GPRv_APX 
XED_IFORM_CMOVNO_GPRv_GPRv_MEMv_APX 
XED_IFORM_CMOVNO_GPRv_MEMv 
XED_IFORM_CMOVNP_GPRv_GPRv 
XED_IFORM_CMOVNP_GPRv_GPRv_GPRv_APX 
XED_IFORM_CMOVNP_GPRv_GPRv_MEMv_APX 
XED_IFORM_CMOVNP_GPRv_MEMv 
XED_IFORM_CMOVNS_GPRv_GPRv 
XED_IFORM_CMOVNS_GPRv_GPRv_GPRv_APX 
XED_IFORM_CMOVNS_GPRv_GPRv_MEMv_APX 
XED_IFORM_CMOVNS_GPRv_MEMv 
XED_IFORM_CMOVNZ_GPRv_GPRv 
XED_IFORM_CMOVNZ_GPRv_GPRv_GPRv_APX 
XED_IFORM_CMOVNZ_GPRv_GPRv_MEMv_APX 
XED_IFORM_CMOVNZ_GPRv_MEMv 
XED_IFORM_CMOVO_GPRv_GPRv 
XED_IFORM_CMOVO_GPRv_GPRv_GPRv_APX 
XED_IFORM_CMOVO_GPRv_GPRv_MEMv_APX 
XED_IFORM_CMOVO_GPRv_MEMv 
XED_IFORM_CMOVP_GPRv_GPRv 
XED_IFORM_CMOVP_GPRv_GPRv_GPRv_APX 
XED_IFORM_CMOVP_GPRv_GPRv_MEMv_APX 
XED_IFORM_CMOVP_GPRv_MEMv 
XED_IFORM_CMOVS_GPRv_GPRv 
XED_IFORM_CMOVS_GPRv_GPRv_GPRv_APX 
XED_IFORM_CMOVS_GPRv_GPRv_MEMv_APX 
XED_IFORM_CMOVS_GPRv_MEMv 
XED_IFORM_CMOVZ_GPRv_GPRv 
XED_IFORM_CMOVZ_GPRv_GPRv_GPRv_APX 
XED_IFORM_CMOVZ_GPRv_GPRv_MEMv_APX 
XED_IFORM_CMOVZ_GPRv_MEMv 
XED_IFORM_CMP_AL_IMMb 
XED_IFORM_CMP_GPR8_GPR8_38 
XED_IFORM_CMP_GPR8_GPR8_3A 
XED_IFORM_CMP_GPR8_IMMb_80r7 
XED_IFORM_CMP_GPR8_IMMb_82r7 
XED_IFORM_CMP_GPR8_MEMb 
XED_IFORM_CMP_GPRv_GPRv_39 
XED_IFORM_CMP_GPRv_GPRv_3B 
XED_IFORM_CMP_GPRv_IMMb 
XED_IFORM_CMP_GPRv_IMMz 
XED_IFORM_CMP_GPRv_MEMv 
XED_IFORM_CMP_MEMb_GPR8 
XED_IFORM_CMP_MEMb_IMMb_80r7 
XED_IFORM_CMP_MEMb_IMMb_82r7 
XED_IFORM_CMP_MEMv_GPRv 
XED_IFORM_CMP_MEMv_IMMb 
XED_IFORM_CMP_MEMv_IMMz 
XED_IFORM_CMP_OrAX_IMMz 
XED_IFORM_CMPBEXADD_MEMu32_GPR32u32_GPR32u32 
XED_IFORM_CMPBEXADD_MEMu32_GPR32u32_GPR32u32_APX 
XED_IFORM_CMPBEXADD_MEMu64_GPR64u64_GPR64u64 
XED_IFORM_CMPBEXADD_MEMu64_GPR64u64_GPR64u64_APX 
XED_IFORM_CMPBXADD_MEMu32_GPR32u32_GPR32u32 
XED_IFORM_CMPBXADD_MEMu32_GPR32u32_GPR32u32_APX 
XED_IFORM_CMPBXADD_MEMu64_GPR64u64_GPR64u64 
XED_IFORM_CMPBXADD_MEMu64_GPR64u64_GPR64u64_APX 
XED_IFORM_CMPLEXADD_MEMu32_GPR32u32_GPR32u32 
XED_IFORM_CMPLEXADD_MEMu32_GPR32u32_GPR32u32_APX 
XED_IFORM_CMPLEXADD_MEMu64_GPR64u64_GPR64u64 
XED_IFORM_CMPLEXADD_MEMu64_GPR64u64_GPR64u64_APX 
XED_IFORM_CMPLXADD_MEMu32_GPR32u32_GPR32u32 
XED_IFORM_CMPLXADD_MEMu32_GPR32u32_GPR32u32_APX 
XED_IFORM_CMPLXADD_MEMu64_GPR64u64_GPR64u64 
XED_IFORM_CMPLXADD_MEMu64_GPR64u64_GPR64u64_APX 
XED_IFORM_CMPNBEXADD_MEMu32_GPR32u32_GPR32u32 
XED_IFORM_CMPNBEXADD_MEMu32_GPR32u32_GPR32u32_APX 
XED_IFORM_CMPNBEXADD_MEMu64_GPR64u64_GPR64u64 
XED_IFORM_CMPNBEXADD_MEMu64_GPR64u64_GPR64u64_APX 
XED_IFORM_CMPNBXADD_MEMu32_GPR32u32_GPR32u32 
XED_IFORM_CMPNBXADD_MEMu32_GPR32u32_GPR32u32_APX 
XED_IFORM_CMPNBXADD_MEMu64_GPR64u64_GPR64u64 
XED_IFORM_CMPNBXADD_MEMu64_GPR64u64_GPR64u64_APX 
XED_IFORM_CMPNLEXADD_MEMu32_GPR32u32_GPR32u32 
XED_IFORM_CMPNLEXADD_MEMu32_GPR32u32_GPR32u32_APX 
XED_IFORM_CMPNLEXADD_MEMu64_GPR64u64_GPR64u64 
XED_IFORM_CMPNLEXADD_MEMu64_GPR64u64_GPR64u64_APX 
XED_IFORM_CMPNLXADD_MEMu32_GPR32u32_GPR32u32 
XED_IFORM_CMPNLXADD_MEMu32_GPR32u32_GPR32u32_APX 
XED_IFORM_CMPNLXADD_MEMu64_GPR64u64_GPR64u64 
XED_IFORM_CMPNLXADD_MEMu64_GPR64u64_GPR64u64_APX 
XED_IFORM_CMPNOXADD_MEMu32_GPR32u32_GPR32u32 
XED_IFORM_CMPNOXADD_MEMu32_GPR32u32_GPR32u32_APX 
XED_IFORM_CMPNOXADD_MEMu64_GPR64u64_GPR64u64 
XED_IFORM_CMPNOXADD_MEMu64_GPR64u64_GPR64u64_APX 
XED_IFORM_CMPNPXADD_MEMu32_GPR32u32_GPR32u32 
XED_IFORM_CMPNPXADD_MEMu32_GPR32u32_GPR32u32_APX 
XED_IFORM_CMPNPXADD_MEMu64_GPR64u64_GPR64u64 
XED_IFORM_CMPNPXADD_MEMu64_GPR64u64_GPR64u64_APX 
XED_IFORM_CMPNSXADD_MEMu32_GPR32u32_GPR32u32 
XED_IFORM_CMPNSXADD_MEMu32_GPR32u32_GPR32u32_APX 
XED_IFORM_CMPNSXADD_MEMu64_GPR64u64_GPR64u64 
XED_IFORM_CMPNSXADD_MEMu64_GPR64u64_GPR64u64_APX 
XED_IFORM_CMPNZXADD_MEMu32_GPR32u32_GPR32u32 
XED_IFORM_CMPNZXADD_MEMu32_GPR32u32_GPR32u32_APX 
XED_IFORM_CMPNZXADD_MEMu64_GPR64u64_GPR64u64 
XED_IFORM_CMPNZXADD_MEMu64_GPR64u64_GPR64u64_APX 
XED_IFORM_CMPOXADD_MEMu32_GPR32u32_GPR32u32 
XED_IFORM_CMPOXADD_MEMu32_GPR32u32_GPR32u32_APX 
XED_IFORM_CMPOXADD_MEMu64_GPR64u64_GPR64u64 
XED_IFORM_CMPOXADD_MEMu64_GPR64u64_GPR64u64_APX 
XED_IFORM_CMPPD_XMMpd_MEMpd_IMMb 
XED_IFORM_CMPPD_XMMpd_XMMpd_IMMb 
XED_IFORM_CMPPS_XMMps_MEMps_IMMb 
XED_IFORM_CMPPS_XMMps_XMMps_IMMb 
XED_IFORM_CMPPXADD_MEMu32_GPR32u32_GPR32u32 
XED_IFORM_CMPPXADD_MEMu32_GPR32u32_GPR32u32_APX 
XED_IFORM_CMPPXADD_MEMu64_GPR64u64_GPR64u64 
XED_IFORM_CMPPXADD_MEMu64_GPR64u64_GPR64u64_APX 
XED_IFORM_CMPSB 
XED_IFORM_CMPSD 
XED_IFORM_CMPSD_XMM_XMMsd_MEMsd_IMMb 
XED_IFORM_CMPSD_XMM_XMMsd_XMMsd_IMMb 
XED_IFORM_CMPSQ 
XED_IFORM_CMPSS_XMMss_MEMss_IMMb 
XED_IFORM_CMPSS_XMMss_XMMss_IMMb 
XED_IFORM_CMPSW 
XED_IFORM_CMPSXADD_MEMu32_GPR32u32_GPR32u32 
XED_IFORM_CMPSXADD_MEMu32_GPR32u32_GPR32u32_APX 
XED_IFORM_CMPSXADD_MEMu64_GPR64u64_GPR64u64 
XED_IFORM_CMPSXADD_MEMu64_GPR64u64_GPR64u64_APX 
XED_IFORM_CMPXCHG_GPR8_GPR8 
XED_IFORM_CMPXCHG_GPRv_GPRv 
XED_IFORM_CMPXCHG_MEMb_GPR8 
XED_IFORM_CMPXCHG_MEMv_GPRv 
XED_IFORM_CMPXCHG16B_MEMdq 
XED_IFORM_CMPXCHG16B_LOCK_MEMdq 
XED_IFORM_CMPXCHG8B_MEMq 
XED_IFORM_CMPXCHG8B_LOCK_MEMq 
XED_IFORM_CMPXCHG_LOCK_MEMb_GPR8 
XED_IFORM_CMPXCHG_LOCK_MEMv_GPRv 
XED_IFORM_CMPZXADD_MEMu32_GPR32u32_GPR32u32 
XED_IFORM_CMPZXADD_MEMu32_GPR32u32_GPR32u32_APX 
XED_IFORM_CMPZXADD_MEMu64_GPR64u64_GPR64u64 
XED_IFORM_CMPZXADD_MEMu64_GPR64u64_GPR64u64_APX 
XED_IFORM_COMISD_XMMsd_MEMsd 
XED_IFORM_COMISD_XMMsd_XMMsd 
XED_IFORM_COMISS_XMMss_MEMss 
XED_IFORM_COMISS_XMMss_XMMss 
XED_IFORM_CPUID 
XED_IFORM_CQO 
XED_IFORM_CRC32_GPRy_GPR8i8_APX 
XED_IFORM_CRC32_GPRy_GPRv_APX 
XED_IFORM_CRC32_GPRy_MEMi8_APX 
XED_IFORM_CRC32_GPRy_MEMv_APX 
XED_IFORM_CRC32_GPRyy_GPR8b 
XED_IFORM_CRC32_GPRyy_GPRv 
XED_IFORM_CRC32_GPRyy_MEMb 
XED_IFORM_CRC32_GPRyy_MEMv 
XED_IFORM_CTESTB_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CTESTB_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CTESTB_GPRv_GPRv_DFV_APX 
XED_IFORM_CTESTB_GPRv_IMMz_DFV_APX 
XED_IFORM_CTESTB_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CTESTB_MEMi8_IMM8_DFV_APX 
XED_IFORM_CTESTB_MEMv_GPRv_DFV_APX 
XED_IFORM_CTESTB_MEMv_IMMz_DFV_APX 
XED_IFORM_CTESTBE_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CTESTBE_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CTESTBE_GPRv_GPRv_DFV_APX 
XED_IFORM_CTESTBE_GPRv_IMMz_DFV_APX 
XED_IFORM_CTESTBE_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CTESTBE_MEMi8_IMM8_DFV_APX 
XED_IFORM_CTESTBE_MEMv_GPRv_DFV_APX 
XED_IFORM_CTESTBE_MEMv_IMMz_DFV_APX 
XED_IFORM_CTESTF_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CTESTF_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CTESTF_GPRv_GPRv_DFV_APX 
XED_IFORM_CTESTF_GPRv_IMMz_DFV_APX 
XED_IFORM_CTESTF_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CTESTF_MEMi8_IMM8_DFV_APX 
XED_IFORM_CTESTF_MEMv_GPRv_DFV_APX 
XED_IFORM_CTESTF_MEMv_IMMz_DFV_APX 
XED_IFORM_CTESTL_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CTESTL_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CTESTL_GPRv_GPRv_DFV_APX 
XED_IFORM_CTESTL_GPRv_IMMz_DFV_APX 
XED_IFORM_CTESTL_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CTESTL_MEMi8_IMM8_DFV_APX 
XED_IFORM_CTESTL_MEMv_GPRv_DFV_APX 
XED_IFORM_CTESTL_MEMv_IMMz_DFV_APX 
XED_IFORM_CTESTLE_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CTESTLE_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CTESTLE_GPRv_GPRv_DFV_APX 
XED_IFORM_CTESTLE_GPRv_IMMz_DFV_APX 
XED_IFORM_CTESTLE_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CTESTLE_MEMi8_IMM8_DFV_APX 
XED_IFORM_CTESTLE_MEMv_GPRv_DFV_APX 
XED_IFORM_CTESTLE_MEMv_IMMz_DFV_APX 
XED_IFORM_CTESTNB_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CTESTNB_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CTESTNB_GPRv_GPRv_DFV_APX 
XED_IFORM_CTESTNB_GPRv_IMMz_DFV_APX 
XED_IFORM_CTESTNB_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CTESTNB_MEMi8_IMM8_DFV_APX 
XED_IFORM_CTESTNB_MEMv_GPRv_DFV_APX 
XED_IFORM_CTESTNB_MEMv_IMMz_DFV_APX 
XED_IFORM_CTESTNBE_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CTESTNBE_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CTESTNBE_GPRv_GPRv_DFV_APX 
XED_IFORM_CTESTNBE_GPRv_IMMz_DFV_APX 
XED_IFORM_CTESTNBE_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CTESTNBE_MEMi8_IMM8_DFV_APX 
XED_IFORM_CTESTNBE_MEMv_GPRv_DFV_APX 
XED_IFORM_CTESTNBE_MEMv_IMMz_DFV_APX 
XED_IFORM_CTESTNL_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CTESTNL_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CTESTNL_GPRv_GPRv_DFV_APX 
XED_IFORM_CTESTNL_GPRv_IMMz_DFV_APX 
XED_IFORM_CTESTNL_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CTESTNL_MEMi8_IMM8_DFV_APX 
XED_IFORM_CTESTNL_MEMv_GPRv_DFV_APX 
XED_IFORM_CTESTNL_MEMv_IMMz_DFV_APX 
XED_IFORM_CTESTNLE_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CTESTNLE_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CTESTNLE_GPRv_GPRv_DFV_APX 
XED_IFORM_CTESTNLE_GPRv_IMMz_DFV_APX 
XED_IFORM_CTESTNLE_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CTESTNLE_MEMi8_IMM8_DFV_APX 
XED_IFORM_CTESTNLE_MEMv_GPRv_DFV_APX 
XED_IFORM_CTESTNLE_MEMv_IMMz_DFV_APX 
XED_IFORM_CTESTNO_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CTESTNO_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CTESTNO_GPRv_GPRv_DFV_APX 
XED_IFORM_CTESTNO_GPRv_IMMz_DFV_APX 
XED_IFORM_CTESTNO_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CTESTNO_MEMi8_IMM8_DFV_APX 
XED_IFORM_CTESTNO_MEMv_GPRv_DFV_APX 
XED_IFORM_CTESTNO_MEMv_IMMz_DFV_APX 
XED_IFORM_CTESTNS_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CTESTNS_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CTESTNS_GPRv_GPRv_DFV_APX 
XED_IFORM_CTESTNS_GPRv_IMMz_DFV_APX 
XED_IFORM_CTESTNS_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CTESTNS_MEMi8_IMM8_DFV_APX 
XED_IFORM_CTESTNS_MEMv_GPRv_DFV_APX 
XED_IFORM_CTESTNS_MEMv_IMMz_DFV_APX 
XED_IFORM_CTESTNZ_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CTESTNZ_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CTESTNZ_GPRv_GPRv_DFV_APX 
XED_IFORM_CTESTNZ_GPRv_IMMz_DFV_APX 
XED_IFORM_CTESTNZ_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CTESTNZ_MEMi8_IMM8_DFV_APX 
XED_IFORM_CTESTNZ_MEMv_GPRv_DFV_APX 
XED_IFORM_CTESTNZ_MEMv_IMMz_DFV_APX 
XED_IFORM_CTESTO_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CTESTO_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CTESTO_GPRv_GPRv_DFV_APX 
XED_IFORM_CTESTO_GPRv_IMMz_DFV_APX 
XED_IFORM_CTESTO_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CTESTO_MEMi8_IMM8_DFV_APX 
XED_IFORM_CTESTO_MEMv_GPRv_DFV_APX 
XED_IFORM_CTESTO_MEMv_IMMz_DFV_APX 
XED_IFORM_CTESTS_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CTESTS_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CTESTS_GPRv_GPRv_DFV_APX 
XED_IFORM_CTESTS_GPRv_IMMz_DFV_APX 
XED_IFORM_CTESTS_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CTESTS_MEMi8_IMM8_DFV_APX 
XED_IFORM_CTESTS_MEMv_GPRv_DFV_APX 
XED_IFORM_CTESTS_MEMv_IMMz_DFV_APX 
XED_IFORM_CTESTT_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CTESTT_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CTESTT_GPRv_GPRv_DFV_APX 
XED_IFORM_CTESTT_GPRv_IMMz_DFV_APX 
XED_IFORM_CTESTT_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CTESTT_MEMi8_IMM8_DFV_APX 
XED_IFORM_CTESTT_MEMv_GPRv_DFV_APX 
XED_IFORM_CTESTT_MEMv_IMMz_DFV_APX 
XED_IFORM_CTESTZ_GPR8i8_GPR8i8_DFV_APX 
XED_IFORM_CTESTZ_GPR8i8_IMM8_DFV_APX 
XED_IFORM_CTESTZ_GPRv_GPRv_DFV_APX 
XED_IFORM_CTESTZ_GPRv_IMMz_DFV_APX 
XED_IFORM_CTESTZ_MEMi8_GPR8i8_DFV_APX 
XED_IFORM_CTESTZ_MEMi8_IMM8_DFV_APX 
XED_IFORM_CTESTZ_MEMv_GPRv_DFV_APX 
XED_IFORM_CTESTZ_MEMv_IMMz_DFV_APX 
XED_IFORM_CVTDQ2PD_XMMpd_MEMq 
XED_IFORM_CVTDQ2PD_XMMpd_XMMq 
XED_IFORM_CVTDQ2PS_XMMps_MEMdq 
XED_IFORM_CVTDQ2PS_XMMps_XMMdq 
XED_IFORM_CVTPD2DQ_XMMdq_MEMpd 
XED_IFORM_CVTPD2DQ_XMMdq_XMMpd 
XED_IFORM_CVTPD2PI_MMXq_MEMpd 
XED_IFORM_CVTPD2PI_MMXq_XMMpd 
XED_IFORM_CVTPD2PS_XMMps_MEMpd 
XED_IFORM_CVTPD2PS_XMMps_XMMpd 
XED_IFORM_CVTPI2PD_XMMpd_MEMq 
XED_IFORM_CVTPI2PD_XMMpd_MMXq 
XED_IFORM_CVTPI2PS_XMMq_MEMq 
XED_IFORM_CVTPI2PS_XMMq_MMXq 
XED_IFORM_CVTPS2DQ_XMMdq_MEMps 
XED_IFORM_CVTPS2DQ_XMMdq_XMMps 
XED_IFORM_CVTPS2PD_XMMpd_MEMq 
XED_IFORM_CVTPS2PD_XMMpd_XMMq 
XED_IFORM_CVTPS2PI_MMXq_MEMq 
XED_IFORM_CVTPS2PI_MMXq_XMMq 
XED_IFORM_CVTSD2SI_GPR32d_MEMsd 
XED_IFORM_CVTSD2SI_GPR32d_XMMsd 
XED_IFORM_CVTSD2SI_GPR64q_MEMsd 
XED_IFORM_CVTSD2SI_GPR64q_XMMsd 
XED_IFORM_CVTSD2SS_XMMss_MEMsd 
XED_IFORM_CVTSD2SS_XMMss_XMMsd 
XED_IFORM_CVTSI2SD_XMMsd_GPR32d 
XED_IFORM_CVTSI2SD_XMMsd_GPR64q 
XED_IFORM_CVTSI2SD_XMMsd_MEMd 
XED_IFORM_CVTSI2SD_XMMsd_MEMq 
XED_IFORM_CVTSI2SS_XMMss_GPR32d 
XED_IFORM_CVTSI2SS_XMMss_GPR64q 
XED_IFORM_CVTSI2SS_XMMss_MEMd 
XED_IFORM_CVTSI2SS_XMMss_MEMq 
XED_IFORM_CVTSS2SD_XMMsd_MEMss 
XED_IFORM_CVTSS2SD_XMMsd_XMMss 
XED_IFORM_CVTSS2SI_GPR32d_MEMss 
XED_IFORM_CVTSS2SI_GPR32d_XMMss 
XED_IFORM_CVTSS2SI_GPR64q_MEMss 
XED_IFORM_CVTSS2SI_GPR64q_XMMss 
XED_IFORM_CVTTPD2DQ_XMMdq_MEMpd 
XED_IFORM_CVTTPD2DQ_XMMdq_XMMpd 
XED_IFORM_CVTTPD2PI_MMXq_MEMpd 
XED_IFORM_CVTTPD2PI_MMXq_XMMpd 
XED_IFORM_CVTTPS2DQ_XMMdq_MEMps 
XED_IFORM_CVTTPS2DQ_XMMdq_XMMps 
XED_IFORM_CVTTPS2PI_MMXq_MEMq 
XED_IFORM_CVTTPS2PI_MMXq_XMMq 
XED_IFORM_CVTTSD2SI_GPR32d_MEMsd 
XED_IFORM_CVTTSD2SI_GPR32d_XMMsd 
XED_IFORM_CVTTSD2SI_GPR64q_MEMsd 
XED_IFORM_CVTTSD2SI_GPR64q_XMMsd 
XED_IFORM_CVTTSS2SI_GPR32d_MEMss 
XED_IFORM_CVTTSS2SI_GPR32d_XMMss 
XED_IFORM_CVTTSS2SI_GPR64q_MEMss 
XED_IFORM_CVTTSS2SI_GPR64q_XMMss 
XED_IFORM_CWD 
XED_IFORM_CWDE 
XED_IFORM_DAA 
XED_IFORM_DAS 
XED_IFORM_DEC_GPR8 
XED_IFORM_DEC_GPR8i8_APX 
XED_IFORM_DEC_GPR8i8_GPR8i8_APX 
XED_IFORM_DEC_GPR8i8_MEMi8_APX 
XED_IFORM_DEC_GPRv_48 
XED_IFORM_DEC_GPRv_APX 
XED_IFORM_DEC_GPRv_FFr1 
XED_IFORM_DEC_GPRv_GPRv_APX 
XED_IFORM_DEC_GPRv_MEMv_APX 
XED_IFORM_DEC_MEMb 
XED_IFORM_DEC_MEMi8_APX 
XED_IFORM_DEC_MEMv 
XED_IFORM_DEC_MEMv_APX 
XED_IFORM_DEC_LOCK_MEMb 
XED_IFORM_DEC_LOCK_MEMv 
XED_IFORM_DIV_GPR8 
XED_IFORM_DIV_GPR8i8_APX 
XED_IFORM_DIV_GPRv 
XED_IFORM_DIV_GPRv_APX 
XED_IFORM_DIV_MEMb 
XED_IFORM_DIV_MEMi8_APX 
XED_IFORM_DIV_MEMv 
XED_IFORM_DIV_MEMv_APX 
XED_IFORM_DIVPD_XMMpd_MEMpd 
XED_IFORM_DIVPD_XMMpd_XMMpd 
XED_IFORM_DIVPS_XMMps_MEMps 
XED_IFORM_DIVPS_XMMps_XMMps 
XED_IFORM_DIVSD_XMMsd_MEMsd 
XED_IFORM_DIVSD_XMMsd_XMMsd 
XED_IFORM_DIVSS_XMMss_MEMss 
XED_IFORM_DIVSS_XMMss_XMMss 
XED_IFORM_DPPD_XMMdq_MEMdq_IMMb 
XED_IFORM_DPPD_XMMdq_XMMdq_IMMb 
XED_IFORM_DPPS_XMMdq_MEMdq_IMMb 
XED_IFORM_DPPS_XMMdq_XMMdq_IMMb 
XED_IFORM_EMMS 
XED_IFORM_ENCLS 
XED_IFORM_ENCLU 
XED_IFORM_ENCLV 
XED_IFORM_ENCODEKEY128_GPR32u8_GPR32u8 
XED_IFORM_ENCODEKEY256_GPR32u8_GPR32u8 
XED_IFORM_ENDBR32 
XED_IFORM_ENDBR64 
XED_IFORM_ENQCMD_GPRa_MEMu32 
XED_IFORM_ENQCMD_GPRav_MEMu32_APX 
XED_IFORM_ENQCMDS_GPRa_MEMu32 
XED_IFORM_ENQCMDS_GPRav_MEMu32_APX 
XED_IFORM_ENTER_IMMw_IMMb 
XED_IFORM_ERETS 
XED_IFORM_ERETU 
XED_IFORM_EXTRACTPS_GPR32d_XMMdq_IMMb 
XED_IFORM_EXTRACTPS_MEMd_XMMps_IMMb 
XED_IFORM_EXTRQ_XMMq_IMMb_IMMb 
XED_IFORM_EXTRQ_XMMq_XMMdq 
XED_IFORM_F2XM1 
XED_IFORM_FABS 
XED_IFORM_FADD_MEMm64real 
XED_IFORM_FADD_MEMmem32real 
XED_IFORM_FADD_ST0_X87 
XED_IFORM_FADD_X87_ST0 
XED_IFORM_FADDP_X87_ST0 
XED_IFORM_FBLD_ST0_MEMmem80dec 
XED_IFORM_FBSTP_MEMmem80dec_ST0 
XED_IFORM_FCHS 
XED_IFORM_FCMOVB_ST0_X87 
XED_IFORM_FCMOVBE_ST0_X87 
XED_IFORM_FCMOVE_ST0_X87 
XED_IFORM_FCMOVNB_ST0_X87 
XED_IFORM_FCMOVNBE_ST0_X87 
XED_IFORM_FCMOVNE_ST0_X87 
XED_IFORM_FCMOVNU_ST0_X87 
XED_IFORM_FCMOVU_ST0_X87 
XED_IFORM_FCOM_ST0_MEMm64real 
XED_IFORM_FCOM_ST0_MEMmem32real 
XED_IFORM_FCOM_ST0_X87 
XED_IFORM_FCOM_ST0_X87_DCD0 
XED_IFORM_FCOMI_ST0_X87 
XED_IFORM_FCOMIP_ST0_X87 
XED_IFORM_FCOMP_ST0_MEMm64real 
XED_IFORM_FCOMP_ST0_MEMmem32real 
XED_IFORM_FCOMP_ST0_X87 
XED_IFORM_FCOMP_ST0_X87_DCD1 
XED_IFORM_FCOMP_ST0_X87_DED0 
XED_IFORM_FCOMPP 
XED_IFORM_FCOS 
XED_IFORM_FDECSTP 
XED_IFORM_FDISI8087_NOP 
XED_IFORM_FDIV_ST0_MEMm64real 
XED_IFORM_FDIV_ST0_MEMmem32real 
XED_IFORM_FDIV_ST0_X87 
XED_IFORM_FDIV_X87_ST0 
XED_IFORM_FDIVP_X87_ST0 
XED_IFORM_FDIVR_ST0_MEMm64real 
XED_IFORM_FDIVR_ST0_MEMmem32real 
XED_IFORM_FDIVR_ST0_X87 
XED_IFORM_FDIVR_X87_ST0 
XED_IFORM_FDIVRP_X87_ST0 
XED_IFORM_FEMMS 
XED_IFORM_FENI8087_NOP 
XED_IFORM_FFREE_X87 
XED_IFORM_FFREEP_X87 
XED_IFORM_FIADD_ST0_MEMmem16int 
XED_IFORM_FIADD_ST0_MEMmem32int 
XED_IFORM_FICOM_ST0_MEMmem16int 
XED_IFORM_FICOM_ST0_MEMmem32int 
XED_IFORM_FICOMP_ST0_MEMmem16int 
XED_IFORM_FICOMP_ST0_MEMmem32int 
XED_IFORM_FIDIV_ST0_MEMmem16int 
XED_IFORM_FIDIV_ST0_MEMmem32int 
XED_IFORM_FIDIVR_ST0_MEMmem16int 
XED_IFORM_FIDIVR_ST0_MEMmem32int 
XED_IFORM_FILD_ST0_MEMm64int 
XED_IFORM_FILD_ST0_MEMmem16int 
XED_IFORM_FILD_ST0_MEMmem32int 
XED_IFORM_FIMUL_ST0_MEMmem16int 
XED_IFORM_FIMUL_ST0_MEMmem32int 
XED_IFORM_FINCSTP 
XED_IFORM_FIST_MEMmem16int_ST0 
XED_IFORM_FIST_MEMmem32int_ST0 
XED_IFORM_FISTP_MEMm64int_ST0 
XED_IFORM_FISTP_MEMmem16int_ST0 
XED_IFORM_FISTP_MEMmem32int_ST0 
XED_IFORM_FISTTP_MEMm64int_ST0 
XED_IFORM_FISTTP_MEMmem16int_ST0 
XED_IFORM_FISTTP_MEMmem32int_ST0 
XED_IFORM_FISUB_ST0_MEMmem16int 
XED_IFORM_FISUB_ST0_MEMmem32int 
XED_IFORM_FISUBR_ST0_MEMmem16int 
XED_IFORM_FISUBR_ST0_MEMmem32int 
XED_IFORM_FLD_ST0_MEMm64real 
XED_IFORM_FLD_ST0_MEMmem32real 
XED_IFORM_FLD_ST0_MEMmem80real 
XED_IFORM_FLD_ST0_X87 
XED_IFORM_FLD1 
XED_IFORM_FLDCW_MEMmem16 
XED_IFORM_FLDENV_MEMmem14 
XED_IFORM_FLDENV_MEMmem28 
XED_IFORM_FLDL2E 
XED_IFORM_FLDL2T 
XED_IFORM_FLDLG2 
XED_IFORM_FLDLN2 
XED_IFORM_FLDPI 
XED_IFORM_FLDZ 
XED_IFORM_FMUL_ST0_MEMm64real 
XED_IFORM_FMUL_ST0_MEMmem32real 
XED_IFORM_FMUL_ST0_X87 
XED_IFORM_FMUL_X87_ST0 
XED_IFORM_FMULP_X87_ST0 
XED_IFORM_FNCLEX 
XED_IFORM_FNINIT 
XED_IFORM_FNOP 
XED_IFORM_FNSAVE_MEMmem108 
XED_IFORM_FNSAVE_MEMmem94 
XED_IFORM_FNSTCW_MEMmem16 
XED_IFORM_FNSTENV_MEMmem14 
XED_IFORM_FNSTENV_MEMmem28 
XED_IFORM_FNSTSW_AX 
XED_IFORM_FNSTSW_MEMmem16 
XED_IFORM_FPATAN 
XED_IFORM_FPREM 
XED_IFORM_FPREM1 
XED_IFORM_FPTAN 
XED_IFORM_FRNDINT 
XED_IFORM_FRSTOR_MEMmem108 
XED_IFORM_FRSTOR_MEMmem94 
XED_IFORM_FSCALE 
XED_IFORM_FSETPM287_NOP 
XED_IFORM_FSIN 
XED_IFORM_FSINCOS 
XED_IFORM_FSQRT 
XED_IFORM_FST_MEMm64real_ST0 
XED_IFORM_FST_MEMmem32real_ST0 
XED_IFORM_FST_X87_ST0 
XED_IFORM_FSTP_MEMm64real_ST0 
XED_IFORM_FSTP_MEMmem32real_ST0 
XED_IFORM_FSTP_MEMmem80real_ST0 
XED_IFORM_FSTP_X87_ST0 
XED_IFORM_FSTP_X87_ST0_DFD0 
XED_IFORM_FSTP_X87_ST0_DFD1 
XED_IFORM_FSTPNCE_X87_ST0 
XED_IFORM_FSUB_ST0_MEMm64real 
XED_IFORM_FSUB_ST0_MEMmem32real 
XED_IFORM_FSUB_ST0_X87 
XED_IFORM_FSUB_X87_ST0 
XED_IFORM_FSUBP_X87_ST0 
XED_IFORM_FSUBR_ST0_MEMm64real 
XED_IFORM_FSUBR_ST0_MEMmem32real 
XED_IFORM_FSUBR_ST0_X87 
XED_IFORM_FSUBR_X87_ST0 
XED_IFORM_FSUBRP_X87_ST0 
XED_IFORM_FTST 
XED_IFORM_FUCOM_ST0_X87 
XED_IFORM_FUCOMI_ST0_X87 
XED_IFORM_FUCOMIP_ST0_X87 
XED_IFORM_FUCOMP_ST0_X87 
XED_IFORM_FUCOMPP 
XED_IFORM_FWAIT 
XED_IFORM_FXAM 
XED_IFORM_FXCH_ST0_X87 
XED_IFORM_FXCH_ST0_X87_DDC1 
XED_IFORM_FXCH_ST0_X87_DFC1 
XED_IFORM_FXRSTOR_MEMmfpxenv 
XED_IFORM_FXRSTOR64_MEMmfpxenv 
XED_IFORM_FXSAVE_MEMmfpxenv 
XED_IFORM_FXSAVE64_MEMmfpxenv 
XED_IFORM_FXTRACT 
XED_IFORM_FYL2X 
XED_IFORM_FYL2XP1 
XED_IFORM_GETSEC 
XED_IFORM_GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8 
XED_IFORM_GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8 
XED_IFORM_GF2P8AFFINEQB_XMMu8_MEMu64_IMM8 
XED_IFORM_GF2P8AFFINEQB_XMMu8_XMMu64_IMM8 
XED_IFORM_GF2P8MULB_XMMu8_MEMu8 
XED_IFORM_GF2P8MULB_XMMu8_XMMu8 
XED_IFORM_HADDPD_XMMpd_MEMpd 
XED_IFORM_HADDPD_XMMpd_XMMpd 
XED_IFORM_HADDPS_XMMps_MEMps 
XED_IFORM_HADDPS_XMMps_XMMps 
XED_IFORM_HLT 
XED_IFORM_HRESET_IMM8 
XED_IFORM_HSUBPD_XMMpd_MEMpd 
XED_IFORM_HSUBPD_XMMpd_XMMpd 
XED_IFORM_HSUBPS_XMMps_MEMps 
XED_IFORM_HSUBPS_XMMps_XMMps 
XED_IFORM_IDIV_GPR8 
XED_IFORM_IDIV_GPR8i8_APX 
XED_IFORM_IDIV_GPRv 
XED_IFORM_IDIV_GPRv_APX 
XED_IFORM_IDIV_MEMb 
XED_IFORM_IDIV_MEMi8_APX 
XED_IFORM_IDIV_MEMv 
XED_IFORM_IDIV_MEMv_APX 
XED_IFORM_IMUL_GPR8 
XED_IFORM_IMUL_GPR8i8_APX 
XED_IFORM_IMUL_GPRv 
XED_IFORM_IMUL_GPRv_APX 
XED_IFORM_IMUL_GPRv_GPRv 
XED_IFORM_IMUL_GPRv_GPRv_APX 
XED_IFORM_IMUL_GPRv_GPRv_GPRv_APX 
XED_IFORM_IMUL_GPRv_GPRv_IMM8_APX 
XED_IFORM_IMUL_GPRv_GPRv_IMM8_APX_ZU 
XED_IFORM_IMUL_GPRv_GPRv_IMMb 
XED_IFORM_IMUL_GPRv_GPRv_IMMz 
XED_IFORM_IMUL_GPRv_GPRv_IMMz_APX 
XED_IFORM_IMUL_GPRv_GPRv_IMMz_APX_ZU 
XED_IFORM_IMUL_GPRv_GPRv_MEMv_APX 
XED_IFORM_IMUL_GPRv_MEMv 
XED_IFORM_IMUL_GPRv_MEMv_APX 
XED_IFORM_IMUL_GPRv_MEMv_IMM8_APX 
XED_IFORM_IMUL_GPRv_MEMv_IMM8_APX_ZU 
XED_IFORM_IMUL_GPRv_MEMv_IMMb 
XED_IFORM_IMUL_GPRv_MEMv_IMMz 
XED_IFORM_IMUL_GPRv_MEMv_IMMz_APX 
XED_IFORM_IMUL_GPRv_MEMv_IMMz_APX_ZU 
XED_IFORM_IMUL_MEMb 
XED_IFORM_IMUL_MEMi8_APX 
XED_IFORM_IMUL_MEMv 
XED_IFORM_IMUL_MEMv_APX 
XED_IFORM_IN_AL_DX 
XED_IFORM_IN_AL_IMMb 
XED_IFORM_IN_OeAX_DX 
XED_IFORM_IN_OeAX_IMMb 
XED_IFORM_INC_GPR8 
XED_IFORM_INC_GPR8i8_APX 
XED_IFORM_INC_GPR8i8_GPR8i8_APX 
XED_IFORM_INC_GPR8i8_MEMi8_APX 
XED_IFORM_INC_GPRv_40 
XED_IFORM_INC_GPRv_APX 
XED_IFORM_INC_GPRv_FFr0 
XED_IFORM_INC_GPRv_GPRv_APX 
XED_IFORM_INC_GPRv_MEMv_APX 
XED_IFORM_INC_MEMb 
XED_IFORM_INC_MEMi8_APX 
XED_IFORM_INC_MEMv 
XED_IFORM_INC_MEMv_APX 
XED_IFORM_INCSSPD_GPR32u8 
XED_IFORM_INCSSPQ_GPR64u8 
XED_IFORM_INC_LOCK_MEMb 
XED_IFORM_INC_LOCK_MEMv 
XED_IFORM_INSB 
XED_IFORM_INSD 
XED_IFORM_INSERTPS_XMMps_MEMd_IMMb 
XED_IFORM_INSERTPS_XMMps_XMMps_IMMb 
XED_IFORM_INSERTQ_XMMq_XMMdq 
XED_IFORM_INSERTQ_XMMq_XMMq_IMMb_IMMb 
XED_IFORM_INSW 
XED_IFORM_INT_IMMb 
XED_IFORM_INT1 
XED_IFORM_INT3 
XED_IFORM_INTO 
XED_IFORM_INVD 
XED_IFORM_INVEPT_GPR32_MEMdq 
XED_IFORM_INVEPT_GPR64_MEMdq 
XED_IFORM_INVEPT_GPR64i64_MEMi128_APX 
XED_IFORM_INVLPG_MEMb 
XED_IFORM_INVLPGA_ArAX_ECX 
XED_IFORM_INVLPGB 
XED_IFORM_INVPCID_GPR32_MEMdq 
XED_IFORM_INVPCID_GPR64_MEMdq 
XED_IFORM_INVPCID_GPR64i64_MEMi128_APX 
XED_IFORM_INVVPID_GPR32_MEMdq 
XED_IFORM_INVVPID_GPR64_MEMdq 
XED_IFORM_INVVPID_GPR64i64_MEMi128_APX 
XED_IFORM_IRET 
XED_IFORM_IRETD 
XED_IFORM_IRETQ 
XED_IFORM_JB_RELBRb 
XED_IFORM_JB_RELBRd 
XED_IFORM_JB_RELBRz 
XED_IFORM_JBE_RELBRb 
XED_IFORM_JBE_RELBRd 
XED_IFORM_JBE_RELBRz 
XED_IFORM_JCXZ_RELBRb 
XED_IFORM_JECXZ_RELBRb 
XED_IFORM_JL_RELBRb 
XED_IFORM_JL_RELBRd 
XED_IFORM_JL_RELBRz 
XED_IFORM_JLE_RELBRb 
XED_IFORM_JLE_RELBRd 
XED_IFORM_JLE_RELBRz 
XED_IFORM_JMP_GPRv 
XED_IFORM_JMP_MEMv 
XED_IFORM_JMP_RELBRb 
XED_IFORM_JMP_RELBRd 
XED_IFORM_JMP_RELBRz 
XED_IFORM_JMPABS_ABSBRu64_APX 
XED_IFORM_JMP_FAR_MEMp2 
XED_IFORM_JMP_FAR_PTRp_IMMw 
XED_IFORM_JNB_RELBRb 
XED_IFORM_JNB_RELBRd 
XED_IFORM_JNB_RELBRz 
XED_IFORM_JNBE_RELBRb 
XED_IFORM_JNBE_RELBRd 
XED_IFORM_JNBE_RELBRz 
XED_IFORM_JNL_RELBRb 
XED_IFORM_JNL_RELBRd 
XED_IFORM_JNL_RELBRz 
XED_IFORM_JNLE_RELBRb 
XED_IFORM_JNLE_RELBRd 
XED_IFORM_JNLE_RELBRz 
XED_IFORM_JNO_RELBRb 
XED_IFORM_JNO_RELBRd 
XED_IFORM_JNO_RELBRz 
XED_IFORM_JNP_RELBRb 
XED_IFORM_JNP_RELBRd 
XED_IFORM_JNP_RELBRz 
XED_IFORM_JNS_RELBRb 
XED_IFORM_JNS_RELBRd 
XED_IFORM_JNS_RELBRz 
XED_IFORM_JNZ_RELBRb 
XED_IFORM_JNZ_RELBRd 
XED_IFORM_JNZ_RELBRz 
XED_IFORM_JO_RELBRb 
XED_IFORM_JO_RELBRd 
XED_IFORM_JO_RELBRz 
XED_IFORM_JP_RELBRb 
XED_IFORM_JP_RELBRd 
XED_IFORM_JP_RELBRz 
XED_IFORM_JRCXZ_RELBRb 
XED_IFORM_JS_RELBRb 
XED_IFORM_JS_RELBRd 
XED_IFORM_JS_RELBRz 
XED_IFORM_JZ_RELBRb 
XED_IFORM_JZ_RELBRd 
XED_IFORM_JZ_RELBRz 
XED_IFORM_KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KMOVB_GPR32u32_MASKmskw_APX 
XED_IFORM_KMOVB_GPR32u32_MASKmskw_AVX512 
XED_IFORM_KMOVB_MASKmskw_GPR32u32_APX 
XED_IFORM_KMOVB_MASKmskw_GPR32u32_AVX512 
XED_IFORM_KMOVB_MASKmskw_MASKu8_APX 
XED_IFORM_KMOVB_MASKmskw_MASKu8_AVX512 
XED_IFORM_KMOVB_MASKmskw_MEMu8_APX 
XED_IFORM_KMOVB_MASKmskw_MEMu8_AVX512 
XED_IFORM_KMOVB_MEMu8_MASKmskw_APX 
XED_IFORM_KMOVB_MEMu8_MASKmskw_AVX512 
XED_IFORM_KMOVD_GPR32u32_MASKmskw_APX 
XED_IFORM_KMOVD_GPR32u32_MASKmskw_AVX512 
XED_IFORM_KMOVD_MASKmskw_GPR32u32_APX 
XED_IFORM_KMOVD_MASKmskw_GPR32u32_AVX512 
XED_IFORM_KMOVD_MASKmskw_MASKu32_APX 
XED_IFORM_KMOVD_MASKmskw_MASKu32_AVX512 
XED_IFORM_KMOVD_MASKmskw_MEMu32_APX 
XED_IFORM_KMOVD_MASKmskw_MEMu32_AVX512 
XED_IFORM_KMOVD_MEMu32_MASKmskw_APX 
XED_IFORM_KMOVD_MEMu32_MASKmskw_AVX512 
XED_IFORM_KMOVQ_GPR64u64_MASKmskw_APX 
XED_IFORM_KMOVQ_GPR64u64_MASKmskw_AVX512 
XED_IFORM_KMOVQ_MASKmskw_GPR64u64_APX 
XED_IFORM_KMOVQ_MASKmskw_GPR64u64_AVX512 
XED_IFORM_KMOVQ_MASKmskw_MASKu64_APX 
XED_IFORM_KMOVQ_MASKmskw_MASKu64_AVX512 
XED_IFORM_KMOVQ_MASKmskw_MEMu64_APX 
XED_IFORM_KMOVQ_MASKmskw_MEMu64_AVX512 
XED_IFORM_KMOVQ_MEMu64_MASKmskw_APX 
XED_IFORM_KMOVQ_MEMu64_MASKmskw_AVX512 
XED_IFORM_KMOVW_GPR32u32_MASKmskw_APX 
XED_IFORM_KMOVW_GPR32u32_MASKmskw_AVX512 
XED_IFORM_KMOVW_MASKmskw_GPR32u32_APX 
XED_IFORM_KMOVW_MASKmskw_GPR32u32_AVX512 
XED_IFORM_KMOVW_MASKmskw_MASKu16_APX 
XED_IFORM_KMOVW_MASKmskw_MASKu16_AVX512 
XED_IFORM_KMOVW_MASKmskw_MEMu16_APX 
XED_IFORM_KMOVW_MASKmskw_MEMu16_AVX512 
XED_IFORM_KMOVW_MEMu16_MASKmskw_APX 
XED_IFORM_KMOVW_MEMu16_MASKmskw_AVX512 
XED_IFORM_KNOTB_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KNOTD_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KNOTQ_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KNOTW_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KORB_MASKmskw_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KORD_MASKmskw_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KORTESTB_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KORTESTD_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KORTESTQ_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KORTESTW_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KORW_MASKmskw_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512 
XED_IFORM_KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512 
XED_IFORM_KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512 
XED_IFORM_KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512 
XED_IFORM_KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512 
XED_IFORM_KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512 
XED_IFORM_KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512 
XED_IFORM_KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512 
XED_IFORM_KTESTB_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KTESTD_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KTESTQ_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KTESTW_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 
XED_IFORM_KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512 
XED_IFORM_LAHF 
XED_IFORM_LAR_GPRv_GPRv 
XED_IFORM_LAR_GPRv_MEMw 
XED_IFORM_LDDQU_XMMpd_MEMdq 
XED_IFORM_LDMXCSR_MEMd 
XED_IFORM_LDS_GPRz_MEMp 
XED_IFORM_LDTILECFG_MEM 
XED_IFORM_LDTILECFG_MEM_APX 
XED_IFORM_LEA_GPRv_AGEN 
XED_IFORM_LEAVE 
XED_IFORM_LES_GPRz_MEMp 
XED_IFORM_LFENCE 
XED_IFORM_LFS_GPRv_MEMp2 
XED_IFORM_LGDT_MEMs 
XED_IFORM_LGDT_MEMs64 
XED_IFORM_LGS_GPRv_MEMp2 
XED_IFORM_LIDT_MEMs 
XED_IFORM_LIDT_MEMs64 
XED_IFORM_LKGS_GPR16u16 
XED_IFORM_LKGS_MEMu16 
XED_IFORM_LLDT_GPR16 
XED_IFORM_LLDT_MEMw 
XED_IFORM_LLWPCB_GPRyy 
XED_IFORM_LMSW_GPR16 
XED_IFORM_LMSW_MEMw 
XED_IFORM_LOADIWKEY_XMMu8_XMMu8 
XED_IFORM_LODSB 
XED_IFORM_LODSD 
XED_IFORM_LODSQ 
XED_IFORM_LODSW 
XED_IFORM_LOOP_RELBRb 
XED_IFORM_LOOPE_RELBRb 
XED_IFORM_LOOPNE_RELBRb 
XED_IFORM_LSL_GPRv_GPRz 
XED_IFORM_LSL_GPRv_MEMw 
XED_IFORM_LSS_GPRv_MEMp2 
XED_IFORM_LTR_GPR16 
XED_IFORM_LTR_MEMw 
XED_IFORM_LWPINS_GPRyy_GPR32d_IMMd 
XED_IFORM_LWPINS_GPRyy_MEMd_IMMd 
XED_IFORM_LWPVAL_GPRyy_GPR32d_IMMd 
XED_IFORM_LWPVAL_GPRyy_MEMd_IMMd 
XED_IFORM_LZCNT_GPRv_GPRv 
XED_IFORM_LZCNT_GPRv_GPRv_APX 
XED_IFORM_LZCNT_GPRv_MEMv 
XED_IFORM_LZCNT_GPRv_MEMv_APX 
XED_IFORM_MASKMOVDQU_XMMxub_XMMxub 
XED_IFORM_MASKMOVQ_MMXq_MMXq 
XED_IFORM_MAXPD_XMMpd_MEMpd 
XED_IFORM_MAXPD_XMMpd_XMMpd 
XED_IFORM_MAXPS_XMMps_MEMps 
XED_IFORM_MAXPS_XMMps_XMMps 
XED_IFORM_MAXSD_XMMsd_MEMsd 
XED_IFORM_MAXSD_XMMsd_XMMsd 
XED_IFORM_MAXSS_XMMss_MEMss 
XED_IFORM_MAXSS_XMMss_XMMss 
XED_IFORM_MCOMMIT 
XED_IFORM_MFENCE 
XED_IFORM_MINPD_XMMpd_MEMpd 
XED_IFORM_MINPD_XMMpd_XMMpd 
XED_IFORM_MINPS_XMMps_MEMps 
XED_IFORM_MINPS_XMMps_XMMps 
XED_IFORM_MINSD_XMMsd_MEMsd 
XED_IFORM_MINSD_XMMsd_XMMsd 
XED_IFORM_MINSS_XMMss_MEMss 
XED_IFORM_MINSS_XMMss_XMMss 
XED_IFORM_MONITOR 
XED_IFORM_MONITORX 
XED_IFORM_MOV_AL_MEMb 
XED_IFORM_MOV_GPR8_GPR8_88 
XED_IFORM_MOV_GPR8_GPR8_8A 
XED_IFORM_MOV_GPR8_IMMb_B0 
XED_IFORM_MOV_GPR8_IMMb_C6r0 
XED_IFORM_MOV_GPR8_MEMb 
XED_IFORM_MOV_GPRv_GPRv_89 
XED_IFORM_MOV_GPRv_GPRv_8B 
XED_IFORM_MOV_GPRv_IMMv 
XED_IFORM_MOV_GPRv_IMMz 
XED_IFORM_MOV_GPRv_MEMv 
XED_IFORM_MOV_GPRv_SEG 
XED_IFORM_MOV_MEMb_AL 
XED_IFORM_MOV_MEMb_GPR8 
XED_IFORM_MOV_MEMb_IMMb 
XED_IFORM_MOV_MEMv_GPRv 
XED_IFORM_MOV_MEMv_IMMz 
XED_IFORM_MOV_MEMv_OrAX 
XED_IFORM_MOV_MEMw_SEG 
XED_IFORM_MOV_OrAX_MEMv 
XED_IFORM_MOV_SEG_GPR16 
XED_IFORM_MOV_SEG_MEMw 
XED_IFORM_MOVAPD_MEMpd_XMMpd 
XED_IFORM_MOVAPD_XMMpd_MEMpd 
XED_IFORM_MOVAPD_XMMpd_XMMpd_0F28 
XED_IFORM_MOVAPD_XMMpd_XMMpd_0F29 
XED_IFORM_MOVAPS_MEMps_XMMps 
XED_IFORM_MOVAPS_XMMps_MEMps 
XED_IFORM_MOVAPS_XMMps_XMMps_0F28 
XED_IFORM_MOVAPS_XMMps_XMMps_0F29 
XED_IFORM_MOVBE_GPRv_GPRv_APX 
XED_IFORM_MOVBE_GPRv_MEMv 
XED_IFORM_MOVBE_GPRv_MEMv_APX 
XED_IFORM_MOVBE_MEMv_GPRv 
XED_IFORM_MOVBE_MEMv_GPRv_APX 
XED_IFORM_MOVD_GPR32_MMXd 
XED_IFORM_MOVD_GPR32_XMMd 
XED_IFORM_MOVD_MEMd_MMXd 
XED_IFORM_MOVD_MEMd_XMMd 
XED_IFORM_MOVD_MMXq_GPR32 
XED_IFORM_MOVD_MMXq_MEMd 
XED_IFORM_MOVD_XMMdq_GPR32 
XED_IFORM_MOVD_XMMdq_MEMd 
XED_IFORM_MOVDDUP_XMMdq_MEMq 
XED_IFORM_MOVDDUP_XMMdq_XMMq 
XED_IFORM_MOVDIR64B_GPRa_MEM 
XED_IFORM_MOVDIR64B_GPRav_MEMu32_APX 
XED_IFORM_MOVDIRI_MEMu32_GPR32u32 
XED_IFORM_MOVDIRI_MEMu64_GPR64u64 
XED_IFORM_MOVDIRI_MEMyu_GPRyu_APX 
XED_IFORM_MOVDQ2Q_MMXq_XMMq 
XED_IFORM_MOVDQA_MEMdq_XMMdq 
XED_IFORM_MOVDQA_XMMdq_MEMdq 
XED_IFORM_MOVDQA_XMMdq_XMMdq_0F6F 
XED_IFORM_MOVDQA_XMMdq_XMMdq_0F7F 
XED_IFORM_MOVDQU_MEMdq_XMMdq 
XED_IFORM_MOVDQU_XMMdq_MEMdq 
XED_IFORM_MOVDQU_XMMdq_XMMdq_0F6F 
XED_IFORM_MOVDQU_XMMdq_XMMdq_0F7F 
XED_IFORM_MOVHLPS_XMMq_XMMq 
XED_IFORM_MOVHPD_MEMq_XMMsd 
XED_IFORM_MOVHPD_XMMsd_MEMq 
XED_IFORM_MOVHPS_MEMq_XMMps 
XED_IFORM_MOVHPS_XMMq_MEMq 
XED_IFORM_MOVLHPS_XMMq_XMMq 
XED_IFORM_MOVLPD_MEMq_XMMsd 
XED_IFORM_MOVLPD_XMMsd_MEMq 
XED_IFORM_MOVLPS_MEMq_XMMq 
XED_IFORM_MOVLPS_XMMq_MEMq 
XED_IFORM_MOVMSKPD_GPR32_XMMpd 
XED_IFORM_MOVMSKPS_GPR32_XMMps 
XED_IFORM_MOVNTDQ_MEMdq_XMMdq 
XED_IFORM_MOVNTDQA_XMMdq_MEMdq 
XED_IFORM_MOVNTI_MEMd_GPR32 
XED_IFORM_MOVNTI_MEMq_GPR64 
XED_IFORM_MOVNTPD_MEMdq_XMMpd 
XED_IFORM_MOVNTPS_MEMdq_XMMps 
XED_IFORM_MOVNTQ_MEMq_MMXq 
XED_IFORM_MOVNTSD_MEMq_XMMq 
XED_IFORM_MOVNTSS_MEMd_XMMd 
XED_IFORM_MOVQ_GPR64_MMXq 
XED_IFORM_MOVQ_GPR64_XMMq 
XED_IFORM_MOVQ_MEMq_MMXq_0F7E 
XED_IFORM_MOVQ_MEMq_MMXq_0F7F 
XED_IFORM_MOVQ_MEMq_XMMq_0F7E 
XED_IFORM_MOVQ_MEMq_XMMq_0FD6 
XED_IFORM_MOVQ_MMXq_GPR64 
XED_IFORM_MOVQ_MMXq_MEMq_0F6E 
XED_IFORM_MOVQ_MMXq_MEMq_0F6F 
XED_IFORM_MOVQ_MMXq_MMXq_0F6F 
XED_IFORM_MOVQ_MMXq_MMXq_0F7F 
XED_IFORM_MOVQ_XMMdq_GPR64 
XED_IFORM_MOVQ_XMMdq_MEMq_0F6E 
XED_IFORM_MOVQ_XMMdq_MEMq_0F7E 
XED_IFORM_MOVQ_XMMdq_XMMq_0F7E 
XED_IFORM_MOVQ_XMMdq_XMMq_0FD6 
XED_IFORM_MOVQ2DQ_XMMdq_MMXq 
XED_IFORM_MOVRS_GPR8i8_MEMi8 
XED_IFORM_MOVRS_GPR8i8_MEMi8_APX 
XED_IFORM_MOVRS_GPRv_MEMv 
XED_IFORM_MOVRS_GPRv_MEMv_APX 
XED_IFORM_MOVSB 
XED_IFORM_MOVSD 
XED_IFORM_MOVSD_XMM_MEMsd_XMMsd 
XED_IFORM_MOVSD_XMM_XMMdq_MEMsd 
XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F10 
XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F11 
XED_IFORM_MOVSHDUP_XMMps_MEMps 
XED_IFORM_MOVSHDUP_XMMps_XMMps 
XED_IFORM_MOVSLDUP_XMMps_MEMps 
XED_IFORM_MOVSLDUP_XMMps_XMMps 
XED_IFORM_MOVSQ 
XED_IFORM_MOVSS_MEMss_XMMss 
XED_IFORM_MOVSS_XMMdq_MEMss 
XED_IFORM_MOVSS_XMMss_XMMss_0F10 
XED_IFORM_MOVSS_XMMss_XMMss_0F11 
XED_IFORM_MOVSW 
XED_IFORM_MOVSX_GPR16_MEMw 
XED_IFORM_MOVSX_GPR32_MEMw 
XED_IFORM_MOVSX_GPR64_MEMw 
XED_IFORM_MOVSX_GPRv_GPR16 
XED_IFORM_MOVSX_GPRv_GPR8 
XED_IFORM_MOVSX_GPRv_MEMb 
XED_IFORM_MOVSX_GPRv_MEMw 
XED_IFORM_MOVSXD_GPR64_MEMd 
XED_IFORM_MOVSXD_GPRv_GPRz 
XED_IFORM_MOVSXD_GPRz_MEMz 
XED_IFORM_MOVUPD_MEMpd_XMMpd 
XED_IFORM_MOVUPD_XMMpd_MEMpd 
XED_IFORM_MOVUPD_XMMpd_XMMpd_0F10 
XED_IFORM_MOVUPD_XMMpd_XMMpd_0F11 
XED_IFORM_MOVUPS_MEMps_XMMps 
XED_IFORM_MOVUPS_XMMps_MEMps 
XED_IFORM_MOVUPS_XMMps_XMMps_0F10 
XED_IFORM_MOVUPS_XMMps_XMMps_0F11 
XED_IFORM_MOVZX_GPR16_MEMw 
XED_IFORM_MOVZX_GPR32_MEMw 
XED_IFORM_MOVZX_GPR64_MEMw 
XED_IFORM_MOVZX_GPRv_GPR16 
XED_IFORM_MOVZX_GPRv_GPR8 
XED_IFORM_MOVZX_GPRv_MEMb 
XED_IFORM_MOVZX_GPRv_MEMw 
XED_IFORM_MOV_CR_CR_GPR32 
XED_IFORM_MOV_CR_CR_GPR64 
XED_IFORM_MOV_CR_GPR32_CR 
XED_IFORM_MOV_CR_GPR64_CR 
XED_IFORM_MOV_DR_DR_GPR32 
XED_IFORM_MOV_DR_DR_GPR64 
XED_IFORM_MOV_DR_GPR32_DR 
XED_IFORM_MOV_DR_GPR64_DR 
XED_IFORM_MPSADBW_XMMdq_MEMdq_IMMb 
XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb 
XED_IFORM_MUL_GPR8 
XED_IFORM_MUL_GPR8i8_APX 
XED_IFORM_MUL_GPRv 
XED_IFORM_MUL_GPRv_APX 
XED_IFORM_MUL_MEMb 
XED_IFORM_MUL_MEMi8_APX 
XED_IFORM_MUL_MEMv 
XED_IFORM_MUL_MEMv_APX 
XED_IFORM_MULPD_XMMpd_MEMpd 
XED_IFORM_MULPD_XMMpd_XMMpd 
XED_IFORM_MULPS_XMMps_MEMps 
XED_IFORM_MULPS_XMMps_XMMps 
XED_IFORM_MULSD_XMMsd_MEMsd 
XED_IFORM_MULSD_XMMsd_XMMsd 
XED_IFORM_MULSS_XMMss_MEMss 
XED_IFORM_MULSS_XMMss_XMMss 
XED_IFORM_MULX_GPR32d_GPR32d_GPR32d 
XED_IFORM_MULX_GPR32d_GPR32d_MEMd 
XED_IFORM_MULX_GPR32i32_GPR32i32_GPR32i32_APX 
XED_IFORM_MULX_GPR32i32_GPR32i32_MEMi32_APX 
XED_IFORM_MULX_GPR64i64_GPR64i64_GPR64i64_APX 
XED_IFORM_MULX_GPR64i64_GPR64i64_MEMi64_APX 
XED_IFORM_MULX_GPR64q_GPR64q_GPR64q 
XED_IFORM_MULX_GPR64q_GPR64q_MEMq 
XED_IFORM_MWAIT 
XED_IFORM_MWAITX 
XED_IFORM_NEG_GPR8 
XED_IFORM_NEG_GPR8i8_APX 
XED_IFORM_NEG_GPR8i8_GPR8i8_APX 
XED_IFORM_NEG_GPR8i8_MEMi8_APX 
XED_IFORM_NEG_GPRv 
XED_IFORM_NEG_GPRv_APX 
XED_IFORM_NEG_GPRv_GPRv_APX 
XED_IFORM_NEG_GPRv_MEMv_APX 
XED_IFORM_NEG_MEMb 
XED_IFORM_NEG_MEMi8_APX 
XED_IFORM_NEG_MEMv 
XED_IFORM_NEG_MEMv_APX 
XED_IFORM_NEG_LOCK_MEMb 
XED_IFORM_NEG_LOCK_MEMv 
XED_IFORM_NOP_90 
XED_IFORM_NOP_GPRv_0F18r0 
XED_IFORM_NOP_GPRv_0F18r1 
XED_IFORM_NOP_GPRv_0F18r2 
XED_IFORM_NOP_GPRv_0F18r3 
XED_IFORM_NOP_GPRv_0F18r4 
XED_IFORM_NOP_GPRv_0F18r5 
XED_IFORM_NOP_GPRv_0F18r6 
XED_IFORM_NOP_GPRv_0F18r7 
XED_IFORM_NOP_GPRv_0F1F 
XED_IFORM_NOP_GPRv_GPRv_0F0D 
XED_IFORM_NOP_GPRv_GPRv_0F19 
XED_IFORM_NOP_GPRv_GPRv_0F1A 
XED_IFORM_NOP_GPRv_GPRv_0F1B 
XED_IFORM_NOP_GPRv_GPRv_0F1C 
XED_IFORM_NOP_GPRv_GPRv_0F1D 
XED_IFORM_NOP_GPRv_GPRv_0F1E 
XED_IFORM_NOP_GPRv_MEM_0F1B 
XED_IFORM_NOP_GPRv_MEMv_0F1A 
XED_IFORM_NOP_MEMv_0F18r4 
XED_IFORM_NOP_MEMv_0F18r5 
XED_IFORM_NOP_MEMv_0F18r6 
XED_IFORM_NOP_MEMv_0F18r7 
XED_IFORM_NOP_MEMv_0F1F 
XED_IFORM_NOP_MEMv_GPRv_0F19 
XED_IFORM_NOP_MEMv_GPRv_0F1C 
XED_IFORM_NOP_MEMv_GPRv_0F1D 
XED_IFORM_NOP_MEMv_GPRv_0F1E 
XED_IFORM_NOT_GPR8 
XED_IFORM_NOT_GPR8i8_APX 
XED_IFORM_NOT_GPR8i8_GPR8i8_APX 
XED_IFORM_NOT_GPR8i8_MEMi8_APX 
XED_IFORM_NOT_GPRv 
XED_IFORM_NOT_GPRv_APX 
XED_IFORM_NOT_GPRv_GPRv_APX 
XED_IFORM_NOT_GPRv_MEMv_APX 
XED_IFORM_NOT_MEMb 
XED_IFORM_NOT_MEMi8_APX 
XED_IFORM_NOT_MEMv 
XED_IFORM_NOT_MEMv_APX 
XED_IFORM_NOT_LOCK_MEMb 
XED_IFORM_NOT_LOCK_MEMv 
XED_IFORM_OR_AL_IMMb 
XED_IFORM_OR_GPR8_GPR8_08 
XED_IFORM_OR_GPR8_GPR8_0A 
XED_IFORM_OR_GPR8_IMMb_80r1 
XED_IFORM_OR_GPR8_IMMb_82r1 
XED_IFORM_OR_GPR8_MEMb 
XED_IFORM_OR_GPR8i8_GPR8i8_APX 
XED_IFORM_OR_GPR8i8_GPR8i8_GPR8i8_APX 
XED_IFORM_OR_GPR8i8_GPR8i8_IMM8_APX 
XED_IFORM_OR_GPR8i8_GPR8i8_MEMi8_APX 
XED_IFORM_OR_GPR8i8_IMM8_APX 
XED_IFORM_OR_GPR8i8_MEMi8_APX 
XED_IFORM_OR_GPR8i8_MEMi8_GPR8i8_APX 
XED_IFORM_OR_GPR8i8_MEMi8_IMM8_APX 
XED_IFORM_OR_GPRv_GPRv_09 
XED_IFORM_OR_GPRv_GPRv_0B 
XED_IFORM_OR_GPRv_GPRv_APX 
XED_IFORM_OR_GPRv_GPRv_GPRv_APX 
XED_IFORM_OR_GPRv_GPRv_IMM8_APX 
XED_IFORM_OR_GPRv_GPRv_IMMz_APX 
XED_IFORM_OR_GPRv_GPRv_MEMv_APX 
XED_IFORM_OR_GPRv_IMM8_APX 
XED_IFORM_OR_GPRv_IMMb 
XED_IFORM_OR_GPRv_IMMz 
XED_IFORM_OR_GPRv_IMMz_APX 
XED_IFORM_OR_GPRv_MEMv 
XED_IFORM_OR_GPRv_MEMv_APX 
XED_IFORM_OR_GPRv_MEMv_GPRv_APX 
XED_IFORM_OR_GPRv_MEMv_IMM8_APX 
XED_IFORM_OR_GPRv_MEMv_IMMz_APX 
XED_IFORM_OR_MEMb_GPR8 
XED_IFORM_OR_MEMb_IMMb_80r1 
XED_IFORM_OR_MEMb_IMMb_82r1 
XED_IFORM_OR_MEMi8_GPR8i8_APX 
XED_IFORM_OR_MEMi8_IMM8_APX 
XED_IFORM_OR_MEMv_GPRv 
XED_IFORM_OR_MEMv_GPRv_APX 
XED_IFORM_OR_MEMv_IMM8_APX 
XED_IFORM_OR_MEMv_IMMb 
XED_IFORM_OR_MEMv_IMMz 
XED_IFORM_OR_MEMv_IMMz_APX 
XED_IFORM_OR_OrAX_IMMz 
XED_IFORM_ORPD_XMMxuq_MEMxuq 
XED_IFORM_ORPD_XMMxuq_XMMxuq 
XED_IFORM_ORPS_XMMxud_MEMxud 
XED_IFORM_ORPS_XMMxud_XMMxud 
XED_IFORM_OR_LOCK_MEMb_GPR8 
XED_IFORM_OR_LOCK_MEMb_IMMb_80r1 
XED_IFORM_OR_LOCK_MEMb_IMMb_82r1 
XED_IFORM_OR_LOCK_MEMv_GPRv 
XED_IFORM_OR_LOCK_MEMv_IMMb 
XED_IFORM_OR_LOCK_MEMv_IMMz 
XED_IFORM_OUT_DX_AL 
XED_IFORM_OUT_DX_OeAX 
XED_IFORM_OUT_IMMb_AL 
XED_IFORM_OUT_IMMb_OeAX 
XED_IFORM_OUTSB 
XED_IFORM_OUTSD 
XED_IFORM_OUTSW 
XED_IFORM_PABSB_MMXq_MEMq 
XED_IFORM_PABSB_MMXq_MMXq 
XED_IFORM_PABSB_XMMdq_MEMdq 
XED_IFORM_PABSB_XMMdq_XMMdq 
XED_IFORM_PABSD_MMXq_MEMq 
XED_IFORM_PABSD_MMXq_MMXq 
XED_IFORM_PABSD_XMMdq_MEMdq 
XED_IFORM_PABSD_XMMdq_XMMdq 
XED_IFORM_PABSW_MMXq_MEMq 
XED_IFORM_PABSW_MMXq_MMXq 
XED_IFORM_PABSW_XMMdq_MEMdq 
XED_IFORM_PABSW_XMMdq_XMMdq 
XED_IFORM_PACKSSDW_MMXq_MEMq 
XED_IFORM_PACKSSDW_MMXq_MMXq 
XED_IFORM_PACKSSDW_XMMdq_MEMdq 
XED_IFORM_PACKSSDW_XMMdq_XMMdq 
XED_IFORM_PACKSSWB_MMXq_MEMq 
XED_IFORM_PACKSSWB_MMXq_MMXq 
XED_IFORM_PACKSSWB_XMMdq_MEMdq 
XED_IFORM_PACKSSWB_XMMdq_XMMdq 
XED_IFORM_PACKUSDW_XMMdq_MEMdq 
XED_IFORM_PACKUSDW_XMMdq_XMMdq 
XED_IFORM_PACKUSWB_MMXq_MEMq 
XED_IFORM_PACKUSWB_MMXq_MMXq 
XED_IFORM_PACKUSWB_XMMdq_MEMdq 
XED_IFORM_PACKUSWB_XMMdq_XMMdq 
XED_IFORM_PADDB_MMXq_MEMq 
XED_IFORM_PADDB_MMXq_MMXq 
XED_IFORM_PADDB_XMMdq_MEMdq 
XED_IFORM_PADDB_XMMdq_XMMdq 
XED_IFORM_PADDD_MMXq_MEMq 
XED_IFORM_PADDD_MMXq_MMXq 
XED_IFORM_PADDD_XMMdq_MEMdq 
XED_IFORM_PADDD_XMMdq_XMMdq 
XED_IFORM_PADDQ_MMXq_MEMq 
XED_IFORM_PADDQ_MMXq_MMXq 
XED_IFORM_PADDQ_XMMdq_MEMdq 
XED_IFORM_PADDQ_XMMdq_XMMdq 
XED_IFORM_PADDSB_MMXq_MEMq 
XED_IFORM_PADDSB_MMXq_MMXq 
XED_IFORM_PADDSB_XMMdq_MEMdq 
XED_IFORM_PADDSB_XMMdq_XMMdq 
XED_IFORM_PADDSW_MMXq_MEMq 
XED_IFORM_PADDSW_MMXq_MMXq 
XED_IFORM_PADDSW_XMMdq_MEMdq 
XED_IFORM_PADDSW_XMMdq_XMMdq 
XED_IFORM_PADDUSB_MMXq_MEMq 
XED_IFORM_PADDUSB_MMXq_MMXq 
XED_IFORM_PADDUSB_XMMdq_MEMdq 
XED_IFORM_PADDUSB_XMMdq_XMMdq 
XED_IFORM_PADDUSW_MMXq_MEMq 
XED_IFORM_PADDUSW_MMXq_MMXq 
XED_IFORM_PADDUSW_XMMdq_MEMdq 
XED_IFORM_PADDUSW_XMMdq_XMMdq 
XED_IFORM_PADDW_MMXq_MEMq 
XED_IFORM_PADDW_MMXq_MMXq 
XED_IFORM_PADDW_XMMdq_MEMdq 
XED_IFORM_PADDW_XMMdq_XMMdq 
XED_IFORM_PALIGNR_MMXq_MEMq_IMMb 
XED_IFORM_PALIGNR_MMXq_MMXq_IMMb 
XED_IFORM_PALIGNR_XMMdq_MEMdq_IMMb 
XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb 
XED_IFORM_PAND_MMXq_MEMq 
XED_IFORM_PAND_MMXq_MMXq 
XED_IFORM_PAND_XMMdq_MEMdq 
XED_IFORM_PAND_XMMdq_XMMdq 
XED_IFORM_PANDN_MMXq_MEMq 
XED_IFORM_PANDN_MMXq_MMXq 
XED_IFORM_PANDN_XMMdq_MEMdq 
XED_IFORM_PANDN_XMMdq_XMMdq 
XED_IFORM_PAUSE 
XED_IFORM_PAVGB_MMXq_MEMq 
XED_IFORM_PAVGB_MMXq_MMXq 
XED_IFORM_PAVGB_XMMdq_MEMdq 
XED_IFORM_PAVGB_XMMdq_XMMdq 
XED_IFORM_PAVGUSB_MMXq_MEMq 
XED_IFORM_PAVGUSB_MMXq_MMXq 
XED_IFORM_PAVGW_MMXq_MEMq 
XED_IFORM_PAVGW_MMXq_MMXq 
XED_IFORM_PAVGW_XMMdq_MEMdq 
XED_IFORM_PAVGW_XMMdq_XMMdq 
XED_IFORM_PBLENDVB_XMMdq_MEMdq 
XED_IFORM_PBLENDVB_XMMdq_XMMdq 
XED_IFORM_PBLENDW_XMMdq_MEMdq_IMMb 
XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb 
XED_IFORM_PBNDKB 
XED_IFORM_PCLMULQDQ_XMMdq_MEMdq_IMMb 
XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb 
XED_IFORM_PCMPEQB_MMXq_MEMq 
XED_IFORM_PCMPEQB_MMXq_MMXq 
XED_IFORM_PCMPEQB_XMMdq_MEMdq 
XED_IFORM_PCMPEQB_XMMdq_XMMdq 
XED_IFORM_PCMPEQD_MMXq_MEMq 
XED_IFORM_PCMPEQD_MMXq_MMXq 
XED_IFORM_PCMPEQD_XMMdq_MEMdq 
XED_IFORM_PCMPEQD_XMMdq_XMMdq 
XED_IFORM_PCMPEQQ_XMMdq_MEMdq 
XED_IFORM_PCMPEQQ_XMMdq_XMMdq 
XED_IFORM_PCMPEQW_MMXq_MEMq 
XED_IFORM_PCMPEQW_MMXq_MMXq 
XED_IFORM_PCMPEQW_XMMdq_MEMdq 
XED_IFORM_PCMPEQW_XMMdq_XMMdq 
XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb 
XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb 
XED_IFORM_PCMPESTRI64_XMMdq_MEMdq_IMMb 
XED_IFORM_PCMPESTRI64_XMMdq_XMMdq_IMMb 
XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb 
XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb 
XED_IFORM_PCMPESTRM64_XMMdq_MEMdq_IMMb 
XED_IFORM_PCMPESTRM64_XMMdq_XMMdq_IMMb 
XED_IFORM_PCMPGTB_MMXq_MEMq 
XED_IFORM_PCMPGTB_MMXq_MMXq 
XED_IFORM_PCMPGTB_XMMdq_MEMdq 
XED_IFORM_PCMPGTB_XMMdq_XMMdq 
XED_IFORM_PCMPGTD_MMXq_MEMq 
XED_IFORM_PCMPGTD_MMXq_MMXq 
XED_IFORM_PCMPGTD_XMMdq_MEMdq 
XED_IFORM_PCMPGTD_XMMdq_XMMdq 
XED_IFORM_PCMPGTQ_XMMdq_MEMdq 
XED_IFORM_PCMPGTQ_XMMdq_XMMdq 
XED_IFORM_PCMPGTW_MMXq_MEMq 
XED_IFORM_PCMPGTW_MMXq_MMXq 
XED_IFORM_PCMPGTW_XMMdq_MEMdq 
XED_IFORM_PCMPGTW_XMMdq_XMMdq 
XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb 
XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb 
XED_IFORM_PCMPISTRI64_XMMdq_MEMdq_IMMb 
XED_IFORM_PCMPISTRI64_XMMdq_XMMdq_IMMb 
XED_IFORM_PCMPISTRM_XMMdq_MEMdq_IMMb 
XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb 
XED_IFORM_PCONFIG 
XED_IFORM_PCONFIG64 
XED_IFORM_PDEP_GPR32d_GPR32d_GPR32d 
XED_IFORM_PDEP_GPR32d_GPR32d_MEMd 
XED_IFORM_PDEP_GPR32i32_GPR32i32_GPR32i32_APX 
XED_IFORM_PDEP_GPR32i32_GPR32i32_MEMi32_APX 
XED_IFORM_PDEP_GPR64i64_GPR64i64_GPR64i64_APX 
XED_IFORM_PDEP_GPR64i64_GPR64i64_MEMi64_APX 
XED_IFORM_PDEP_GPR64q_GPR64q_GPR64q 
XED_IFORM_PDEP_GPR64q_GPR64q_MEMq 
XED_IFORM_PEXT_GPR32d_GPR32d_GPR32d 
XED_IFORM_PEXT_GPR32d_GPR32d_MEMd 
XED_IFORM_PEXT_GPR32i32_GPR32i32_GPR32i32_APX 
XED_IFORM_PEXT_GPR32i32_GPR32i32_MEMi32_APX 
XED_IFORM_PEXT_GPR64i64_GPR64i64_GPR64i64_APX 
XED_IFORM_PEXT_GPR64i64_GPR64i64_MEMi64_APX 
XED_IFORM_PEXT_GPR64q_GPR64q_GPR64q 
XED_IFORM_PEXT_GPR64q_GPR64q_MEMq 
XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb 
XED_IFORM_PEXTRB_MEMb_XMMdq_IMMb 
XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb 
XED_IFORM_PEXTRD_MEMd_XMMdq_IMMb 
XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb 
XED_IFORM_PEXTRQ_MEMq_XMMdq_IMMb 
XED_IFORM_PEXTRW_GPR32_MMXq_IMMb 
XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb 
XED_IFORM_PEXTRW_SSE4_GPR32_XMMdq_IMMb 
XED_IFORM_PEXTRW_SSE4_MEMw_XMMdq_IMMb 
XED_IFORM_PF2ID_MMXq_MEMq 
XED_IFORM_PF2ID_MMXq_MMXq 
XED_IFORM_PF2IW_MMXq_MEMq 
XED_IFORM_PF2IW_MMXq_MMXq 
XED_IFORM_PFACC_MMXq_MEMq 
XED_IFORM_PFACC_MMXq_MMXq 
XED_IFORM_PFADD_MMXq_MEMq 
XED_IFORM_PFADD_MMXq_MMXq 
XED_IFORM_PFCMPEQ_MMXq_MEMq 
XED_IFORM_PFCMPEQ_MMXq_MMXq 
XED_IFORM_PFCMPGE_MMXq_MEMq 
XED_IFORM_PFCMPGE_MMXq_MMXq 
XED_IFORM_PFCMPGT_MMXq_MEMq 
XED_IFORM_PFCMPGT_MMXq_MMXq 
XED_IFORM_PFMAX_MMXq_MEMq 
XED_IFORM_PFMAX_MMXq_MMXq 
XED_IFORM_PFMIN_MMXq_MEMq 
XED_IFORM_PFMIN_MMXq_MMXq 
XED_IFORM_PFMUL_MMXq_MEMq 
XED_IFORM_PFMUL_MMXq_MMXq 
XED_IFORM_PFNACC_MMXq_MEMq 
XED_IFORM_PFNACC_MMXq_MMXq 
XED_IFORM_PFPNACC_MMXq_MEMq 
XED_IFORM_PFPNACC_MMXq_MMXq 
XED_IFORM_PFRCP_MMXq_MEMq 
XED_IFORM_PFRCP_MMXq_MMXq 
XED_IFORM_PFRCPIT1_MMXq_MEMq 
XED_IFORM_PFRCPIT1_MMXq_MMXq 
XED_IFORM_PFRCPIT2_MMXq_MEMq 
XED_IFORM_PFRCPIT2_MMXq_MMXq 
XED_IFORM_PFRSQIT1_MMXq_MEMq 
XED_IFORM_PFRSQIT1_MMXq_MMXq 
XED_IFORM_PFRSQRT_MMXq_MEMq 
XED_IFORM_PFRSQRT_MMXq_MMXq 
XED_IFORM_PFSUB_MMXq_MEMq 
XED_IFORM_PFSUB_MMXq_MMXq 
XED_IFORM_PFSUBR_MMXq_MEMq 
XED_IFORM_PFSUBR_MMXq_MMXq 
XED_IFORM_PHADDD_MMXq_MEMq 
XED_IFORM_PHADDD_MMXq_MMXq 
XED_IFORM_PHADDD_XMMdq_MEMdq 
XED_IFORM_PHADDD_XMMdq_XMMdq 
XED_IFORM_PHADDSW_MMXq_MEMq 
XED_IFORM_PHADDSW_MMXq_MMXq 
XED_IFORM_PHADDSW_XMMdq_MEMdq 
XED_IFORM_PHADDSW_XMMdq_XMMdq 
XED_IFORM_PHADDW_MMXq_MEMq 
XED_IFORM_PHADDW_MMXq_MMXq 
XED_IFORM_PHADDW_XMMdq_MEMdq 
XED_IFORM_PHADDW_XMMdq_XMMdq 
XED_IFORM_PHMINPOSUW_XMMdq_MEMdq 
XED_IFORM_PHMINPOSUW_XMMdq_XMMdq 
XED_IFORM_PHSUBD_MMXq_MEMq 
XED_IFORM_PHSUBD_MMXq_MMXq 
XED_IFORM_PHSUBD_XMMdq_MEMdq 
XED_IFORM_PHSUBD_XMMdq_XMMdq 
XED_IFORM_PHSUBSW_MMXq_MEMq 
XED_IFORM_PHSUBSW_MMXq_MMXq 
XED_IFORM_PHSUBSW_XMMdq_MEMdq 
XED_IFORM_PHSUBSW_XMMdq_XMMdq 
XED_IFORM_PHSUBW_MMXq_MEMq 
XED_IFORM_PHSUBW_MMXq_MMXq 
XED_IFORM_PHSUBW_XMMdq_MEMdq 
XED_IFORM_PHSUBW_XMMdq_XMMdq 
XED_IFORM_PI2FD_MMXq_MEMq 
XED_IFORM_PI2FD_MMXq_MMXq 
XED_IFORM_PI2FW_MMXq_MEMq 
XED_IFORM_PI2FW_MMXq_MMXq 
XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb 
XED_IFORM_PINSRB_XMMdq_MEMb_IMMb 
XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb 
XED_IFORM_PINSRD_XMMdq_MEMd_IMMb 
XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb 
XED_IFORM_PINSRQ_XMMdq_MEMq_IMMb 
XED_IFORM_PINSRW_MMXq_GPR32_IMMb 
XED_IFORM_PINSRW_MMXq_MEMw_IMMb 
XED_IFORM_PINSRW_XMMdq_GPR32_IMMb 
XED_IFORM_PINSRW_XMMdq_MEMw_IMMb 
XED_IFORM_PMADDUBSW_MMXq_MEMq 
XED_IFORM_PMADDUBSW_MMXq_MMXq 
XED_IFORM_PMADDUBSW_XMMdq_MEMdq 
XED_IFORM_PMADDUBSW_XMMdq_XMMdq 
XED_IFORM_PMADDWD_MMXq_MEMq 
XED_IFORM_PMADDWD_MMXq_MMXq 
XED_IFORM_PMADDWD_XMMdq_MEMdq 
XED_IFORM_PMADDWD_XMMdq_XMMdq 
XED_IFORM_PMAXSB_XMMdq_MEMdq 
XED_IFORM_PMAXSB_XMMdq_XMMdq 
XED_IFORM_PMAXSD_XMMdq_MEMdq 
XED_IFORM_PMAXSD_XMMdq_XMMdq 
XED_IFORM_PMAXSW_MMXq_MEMq 
XED_IFORM_PMAXSW_MMXq_MMXq 
XED_IFORM_PMAXSW_XMMdq_MEMdq 
XED_IFORM_PMAXSW_XMMdq_XMMdq 
XED_IFORM_PMAXUB_MMXq_MEMq 
XED_IFORM_PMAXUB_MMXq_MMXq 
XED_IFORM_PMAXUB_XMMdq_MEMdq 
XED_IFORM_PMAXUB_XMMdq_XMMdq 
XED_IFORM_PMAXUD_XMMdq_MEMdq 
XED_IFORM_PMAXUD_XMMdq_XMMdq 
XED_IFORM_PMAXUW_XMMdq_MEMdq 
XED_IFORM_PMAXUW_XMMdq_XMMdq 
XED_IFORM_PMINSB_XMMdq_MEMdq 
XED_IFORM_PMINSB_XMMdq_XMMdq 
XED_IFORM_PMINSD_XMMdq_MEMdq 
XED_IFORM_PMINSD_XMMdq_XMMdq 
XED_IFORM_PMINSW_MMXq_MEMq 
XED_IFORM_PMINSW_MMXq_MMXq 
XED_IFORM_PMINSW_XMMdq_MEMdq 
XED_IFORM_PMINSW_XMMdq_XMMdq 
XED_IFORM_PMINUB_MMXq_MEMq 
XED_IFORM_PMINUB_MMXq_MMXq 
XED_IFORM_PMINUB_XMMdq_MEMdq 
XED_IFORM_PMINUB_XMMdq_XMMdq 
XED_IFORM_PMINUD_XMMdq_MEMdq 
XED_IFORM_PMINUD_XMMdq_XMMdq 
XED_IFORM_PMINUW_XMMdq_MEMdq 
XED_IFORM_PMINUW_XMMdq_XMMdq 
XED_IFORM_PMOVMSKB_GPR32_MMXq 
XED_IFORM_PMOVMSKB_GPR32_XMMdq 
XED_IFORM_PMOVSXBD_XMMdq_MEMd 
XED_IFORM_PMOVSXBD_XMMdq_XMMd 
XED_IFORM_PMOVSXBQ_XMMdq_MEMw 
XED_IFORM_PMOVSXBQ_XMMdq_XMMw 
XED_IFORM_PMOVSXBW_XMMdq_MEMq 
XED_IFORM_PMOVSXBW_XMMdq_XMMq 
XED_IFORM_PMOVSXDQ_XMMdq_MEMq 
XED_IFORM_PMOVSXDQ_XMMdq_XMMq 
XED_IFORM_PMOVSXWD_XMMdq_MEMq 
XED_IFORM_PMOVSXWD_XMMdq_XMMq 
XED_IFORM_PMOVSXWQ_XMMdq_MEMd 
XED_IFORM_PMOVSXWQ_XMMdq_XMMd 
XED_IFORM_PMOVZXBD_XMMdq_MEMd 
XED_IFORM_PMOVZXBD_XMMdq_XMMd 
XED_IFORM_PMOVZXBQ_XMMdq_MEMw 
XED_IFORM_PMOVZXBQ_XMMdq_XMMw 
XED_IFORM_PMOVZXBW_XMMdq_MEMq 
XED_IFORM_PMOVZXBW_XMMdq_XMMq 
XED_IFORM_PMOVZXDQ_XMMdq_MEMq 
XED_IFORM_PMOVZXDQ_XMMdq_XMMq 
XED_IFORM_PMOVZXWD_XMMdq_MEMq 
XED_IFORM_PMOVZXWD_XMMdq_XMMq 
XED_IFORM_PMOVZXWQ_XMMdq_MEMd 
XED_IFORM_PMOVZXWQ_XMMdq_XMMd 
XED_IFORM_PMULDQ_XMMdq_MEMdq 
XED_IFORM_PMULDQ_XMMdq_XMMdq 
XED_IFORM_PMULHRSW_MMXq_MEMq 
XED_IFORM_PMULHRSW_MMXq_MMXq 
XED_IFORM_PMULHRSW_XMMdq_MEMdq 
XED_IFORM_PMULHRSW_XMMdq_XMMdq 
XED_IFORM_PMULHRW_MMXq_MEMq 
XED_IFORM_PMULHRW_MMXq_MMXq 
XED_IFORM_PMULHUW_MMXq_MEMq 
XED_IFORM_PMULHUW_MMXq_MMXq 
XED_IFORM_PMULHUW_XMMdq_MEMdq 
XED_IFORM_PMULHUW_XMMdq_XMMdq 
XED_IFORM_PMULHW_MMXq_MEMq 
XED_IFORM_PMULHW_MMXq_MMXq 
XED_IFORM_PMULHW_XMMdq_MEMdq 
XED_IFORM_PMULHW_XMMdq_XMMdq 
XED_IFORM_PMULLD_XMMdq_MEMdq 
XED_IFORM_PMULLD_XMMdq_XMMdq 
XED_IFORM_PMULLW_MMXq_MEMq 
XED_IFORM_PMULLW_MMXq_MMXq 
XED_IFORM_PMULLW_XMMdq_MEMdq 
XED_IFORM_PMULLW_XMMdq_XMMdq 
XED_IFORM_PMULUDQ_MMXq_MEMq 
XED_IFORM_PMULUDQ_MMXq_MMXq 
XED_IFORM_PMULUDQ_XMMdq_MEMdq 
XED_IFORM_PMULUDQ_XMMdq_XMMdq 
XED_IFORM_POP_DS 
XED_IFORM_POP_ES 
XED_IFORM_POP_FS 
XED_IFORM_POP_GPRv_58 
XED_IFORM_POP_GPRv_8F 
XED_IFORM_POP_GS 
XED_IFORM_POP_MEMv 
XED_IFORM_POP_SS 
XED_IFORM_POP2_GPR64u64_GPR64u64_APX 
XED_IFORM_POP2P_GPR64u64_GPR64u64_APX 
XED_IFORM_POPA 
XED_IFORM_POPAD 
XED_IFORM_POPCNT_GPRv_GPRv 
XED_IFORM_POPCNT_GPRv_GPRv_APX 
XED_IFORM_POPCNT_GPRv_MEMv 
XED_IFORM_POPCNT_GPRv_MEMv_APX 
XED_IFORM_POPF 
XED_IFORM_POPFD 
XED_IFORM_POPFQ 
XED_IFORM_POPP_GPR64 
XED_IFORM_POR_MMXq_MEMq 
XED_IFORM_POR_MMXq_MMXq 
XED_IFORM_POR_XMMdq_MEMdq 
XED_IFORM_POR_XMMdq_XMMdq 
XED_IFORM_PREFETCHIT0_MEMu8 
XED_IFORM_PREFETCHIT1_MEMu8 
XED_IFORM_PREFETCHNTA_MEMmprefetch 
XED_IFORM_PREFETCHRST2_MEMu8 
XED_IFORM_PREFETCHT0_MEMmprefetch 
XED_IFORM_PREFETCHT1_MEMmprefetch 
XED_IFORM_PREFETCHT2_MEMmprefetch 
XED_IFORM_PREFETCHW_0F0Dr1 
XED_IFORM_PREFETCHW_0F0Dr3 
XED_IFORM_PREFETCHWT1_MEMu8 
XED_IFORM_PREFETCH_EXCLUSIVE_MEMmprefetch 
XED_IFORM_PREFETCH_RESERVED_0F0Dr4 
XED_IFORM_PREFETCH_RESERVED_0F0Dr5 
XED_IFORM_PREFETCH_RESERVED_0F0Dr6 
XED_IFORM_PREFETCH_RESERVED_0F0Dr7 
XED_IFORM_PSADBW_MMXq_MEMq 
XED_IFORM_PSADBW_MMXq_MMXq 
XED_IFORM_PSADBW_XMMdq_MEMdq 
XED_IFORM_PSADBW_XMMdq_XMMdq 
XED_IFORM_PSHUFB_MMXq_MEMq 
XED_IFORM_PSHUFB_MMXq_MMXq 
XED_IFORM_PSHUFB_XMMdq_MEMdq 
XED_IFORM_PSHUFB_XMMdq_XMMdq 
XED_IFORM_PSHUFD_XMMdq_MEMdq_IMMb 
XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb 
XED_IFORM_PSHUFHW_XMMdq_MEMdq_IMMb 
XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb 
XED_IFORM_PSHUFLW_XMMdq_MEMdq_IMMb 
XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb 
XED_IFORM_PSHUFW_MMXq_MEMq_IMMb 
XED_IFORM_PSHUFW_MMXq_MMXq_IMMb 
XED_IFORM_PSIGNB_MMXq_MEMq 
XED_IFORM_PSIGNB_MMXq_MMXq 
XED_IFORM_PSIGNB_XMMdq_MEMdq 
XED_IFORM_PSIGNB_XMMdq_XMMdq 
XED_IFORM_PSIGND_MMXq_MEMq 
XED_IFORM_PSIGND_MMXq_MMXq 
XED_IFORM_PSIGND_XMMdq_MEMdq 
XED_IFORM_PSIGND_XMMdq_XMMdq 
XED_IFORM_PSIGNW_MMXq_MEMq 
XED_IFORM_PSIGNW_MMXq_MMXq 
XED_IFORM_PSIGNW_XMMdq_MEMdq 
XED_IFORM_PSIGNW_XMMdq_XMMdq 
XED_IFORM_PSLLD_MMXq_IMMb 
XED_IFORM_PSLLD_MMXq_MEMq 
XED_IFORM_PSLLD_MMXq_MMXq 
XED_IFORM_PSLLD_XMMdq_IMMb 
XED_IFORM_PSLLD_XMMdq_MEMdq 
XED_IFORM_PSLLD_XMMdq_XMMdq 
XED_IFORM_PSLLDQ_XMMdq_IMMb 
XED_IFORM_PSLLQ_MMXq_IMMb 
XED_IFORM_PSLLQ_MMXq_MEMq 
XED_IFORM_PSLLQ_MMXq_MMXq 
XED_IFORM_PSLLQ_XMMdq_IMMb 
XED_IFORM_PSLLQ_XMMdq_MEMdq 
XED_IFORM_PSLLQ_XMMdq_XMMdq 
XED_IFORM_PSLLW_MMXq_IMMb 
XED_IFORM_PSLLW_MMXq_MEMq 
XED_IFORM_PSLLW_MMXq_MMXq 
XED_IFORM_PSLLW_XMMdq_IMMb 
XED_IFORM_PSLLW_XMMdq_MEMdq 
XED_IFORM_PSLLW_XMMdq_XMMdq 
XED_IFORM_PSMASH_RAX 
XED_IFORM_PSRAD_MMXq_IMMb 
XED_IFORM_PSRAD_MMXq_MEMq 
XED_IFORM_PSRAD_MMXq_MMXq 
XED_IFORM_PSRAD_XMMdq_IMMb 
XED_IFORM_PSRAD_XMMdq_MEMdq 
XED_IFORM_PSRAD_XMMdq_XMMdq 
XED_IFORM_PSRAW_MMXq_IMMb 
XED_IFORM_PSRAW_MMXq_MEMq 
XED_IFORM_PSRAW_MMXq_MMXq 
XED_IFORM_PSRAW_XMMdq_IMMb 
XED_IFORM_PSRAW_XMMdq_MEMdq 
XED_IFORM_PSRAW_XMMdq_XMMdq 
XED_IFORM_PSRLD_MMXq_IMMb 
XED_IFORM_PSRLD_MMXq_MEMq 
XED_IFORM_PSRLD_MMXq_MMXq 
XED_IFORM_PSRLD_XMMdq_IMMb 
XED_IFORM_PSRLD_XMMdq_MEMdq 
XED_IFORM_PSRLD_XMMdq_XMMdq 
XED_IFORM_PSRLDQ_XMMdq_IMMb 
XED_IFORM_PSRLQ_MMXq_IMMb 
XED_IFORM_PSRLQ_MMXq_MEMq 
XED_IFORM_PSRLQ_MMXq_MMXq 
XED_IFORM_PSRLQ_XMMdq_IMMb 
XED_IFORM_PSRLQ_XMMdq_MEMdq 
XED_IFORM_PSRLQ_XMMdq_XMMdq 
XED_IFORM_PSRLW_MMXq_IMMb 
XED_IFORM_PSRLW_MMXq_MEMq 
XED_IFORM_PSRLW_MMXq_MMXq 
XED_IFORM_PSRLW_XMMdq_IMMb 
XED_IFORM_PSRLW_XMMdq_MEMdq 
XED_IFORM_PSRLW_XMMdq_XMMdq 
XED_IFORM_PSUBB_MMXq_MEMq 
XED_IFORM_PSUBB_MMXq_MMXq 
XED_IFORM_PSUBB_XMMdq_MEMdq 
XED_IFORM_PSUBB_XMMdq_XMMdq 
XED_IFORM_PSUBD_MMXq_MEMq 
XED_IFORM_PSUBD_MMXq_MMXq 
XED_IFORM_PSUBD_XMMdq_MEMdq 
XED_IFORM_PSUBD_XMMdq_XMMdq 
XED_IFORM_PSUBQ_MMXq_MEMq 
XED_IFORM_PSUBQ_MMXq_MMXq 
XED_IFORM_PSUBQ_XMMdq_MEMdq 
XED_IFORM_PSUBQ_XMMdq_XMMdq 
XED_IFORM_PSUBSB_MMXq_MEMq 
XED_IFORM_PSUBSB_MMXq_MMXq 
XED_IFORM_PSUBSB_XMMdq_MEMdq 
XED_IFORM_PSUBSB_XMMdq_XMMdq 
XED_IFORM_PSUBSW_MMXq_MEMq 
XED_IFORM_PSUBSW_MMXq_MMXq 
XED_IFORM_PSUBSW_XMMdq_MEMdq 
XED_IFORM_PSUBSW_XMMdq_XMMdq 
XED_IFORM_PSUBUSB_MMXq_MEMq 
XED_IFORM_PSUBUSB_MMXq_MMXq 
XED_IFORM_PSUBUSB_XMMdq_MEMdq 
XED_IFORM_PSUBUSB_XMMdq_XMMdq 
XED_IFORM_PSUBUSW_MMXq_MEMq 
XED_IFORM_PSUBUSW_MMXq_MMXq 
XED_IFORM_PSUBUSW_XMMdq_MEMdq 
XED_IFORM_PSUBUSW_XMMdq_XMMdq 
XED_IFORM_PSUBW_MMXq_MEMq 
XED_IFORM_PSUBW_MMXq_MMXq 
XED_IFORM_PSUBW_XMMdq_MEMdq 
XED_IFORM_PSUBW_XMMdq_XMMdq 
XED_IFORM_PSWAPD_MMXq_MEMq 
XED_IFORM_PSWAPD_MMXq_MMXq 
XED_IFORM_PTEST_XMMdq_MEMdq 
XED_IFORM_PTEST_XMMdq_XMMdq 
XED_IFORM_PTWRITE_GPRy 
XED_IFORM_PTWRITE_MEMy 
XED_IFORM_PUNPCKHBW_MMXq_MEMq 
XED_IFORM_PUNPCKHBW_MMXq_MMXd 
XED_IFORM_PUNPCKHBW_XMMdq_MEMdq 
XED_IFORM_PUNPCKHBW_XMMdq_XMMq 
XED_IFORM_PUNPCKHDQ_MMXq_MEMq 
XED_IFORM_PUNPCKHDQ_MMXq_MMXd 
XED_IFORM_PUNPCKHDQ_XMMdq_MEMdq 
XED_IFORM_PUNPCKHDQ_XMMdq_XMMq 
XED_IFORM_PUNPCKHQDQ_XMMdq_MEMdq 
XED_IFORM_PUNPCKHQDQ_XMMdq_XMMq 
XED_IFORM_PUNPCKHWD_MMXq_MEMq 
XED_IFORM_PUNPCKHWD_MMXq_MMXd 
XED_IFORM_PUNPCKHWD_XMMdq_MEMdq 
XED_IFORM_PUNPCKHWD_XMMdq_XMMq 
XED_IFORM_PUNPCKLBW_MMXq_MEMd 
XED_IFORM_PUNPCKLBW_MMXq_MMXd 
XED_IFORM_PUNPCKLBW_XMMdq_MEMdq 
XED_IFORM_PUNPCKLBW_XMMdq_XMMq 
XED_IFORM_PUNPCKLDQ_MMXq_MEMd 
XED_IFORM_PUNPCKLDQ_MMXq_MMXd 
XED_IFORM_PUNPCKLDQ_XMMdq_MEMdq 
XED_IFORM_PUNPCKLDQ_XMMdq_XMMq 
XED_IFORM_PUNPCKLQDQ_XMMdq_MEMdq 
XED_IFORM_PUNPCKLQDQ_XMMdq_XMMq 
XED_IFORM_PUNPCKLWD_MMXq_MEMd 
XED_IFORM_PUNPCKLWD_MMXq_MMXd 
XED_IFORM_PUNPCKLWD_XMMdq_MEMdq 
XED_IFORM_PUNPCKLWD_XMMdq_XMMq 
XED_IFORM_PUSH_CS 
XED_IFORM_PUSH_DS 
XED_IFORM_PUSH_ES 
XED_IFORM_PUSH_FS 
XED_IFORM_PUSH_GPRv_50 
XED_IFORM_PUSH_GPRv_FFr6 
XED_IFORM_PUSH_GS 
XED_IFORM_PUSH_IMMb 
XED_IFORM_PUSH_IMMz 
XED_IFORM_PUSH_MEMv 
XED_IFORM_PUSH_SS 
XED_IFORM_PUSH2_GPR64u64_GPR64u64_APX 
XED_IFORM_PUSH2P_GPR64u64_GPR64u64_APX 
XED_IFORM_PUSHA 
XED_IFORM_PUSHAD 
XED_IFORM_PUSHF 
XED_IFORM_PUSHFD 
XED_IFORM_PUSHFQ 
XED_IFORM_PUSHP_GPR64 
XED_IFORM_PVALIDATE_RAX_ECX_EDX 
XED_IFORM_PXOR_MMXq_MEMq 
XED_IFORM_PXOR_MMXq_MMXq 
XED_IFORM_PXOR_XMMdq_MEMdq 
XED_IFORM_PXOR_XMMdq_XMMdq 
XED_IFORM_RCL_GPR8_CL 
XED_IFORM_RCL_GPR8_IMMb 
XED_IFORM_RCL_GPR8_ONE 
XED_IFORM_RCL_GPR8i8_CL_APX 
XED_IFORM_RCL_GPR8i8_GPR8i8_CL_APX 
XED_IFORM_RCL_GPR8i8_GPR8i8_IMM8_APX 
XED_IFORM_RCL_GPR8i8_GPR8i8_ONE_APX 
XED_IFORM_RCL_GPR8i8_IMM8_APX 
XED_IFORM_RCL_GPR8i8_MEMi8_CL_APX 
XED_IFORM_RCL_GPR8i8_MEMi8_IMM8_APX 
XED_IFORM_RCL_GPR8i8_MEMi8_ONE_APX 
XED_IFORM_RCL_GPR8i8_ONE_APX 
XED_IFORM_RCL_GPRv_CL 
XED_IFORM_RCL_GPRv_CL_APX 
XED_IFORM_RCL_GPRv_GPRv_CL_APX 
XED_IFORM_RCL_GPRv_GPRv_IMM8_APX 
XED_IFORM_RCL_GPRv_GPRv_ONE_APX 
XED_IFORM_RCL_GPRv_IMM8_APX 
XED_IFORM_RCL_GPRv_IMMb 
XED_IFORM_RCL_GPRv_MEMv_CL_APX 
XED_IFORM_RCL_GPRv_MEMv_IMM8_APX 
XED_IFORM_RCL_GPRv_MEMv_ONE_APX 
XED_IFORM_RCL_GPRv_ONE 
XED_IFORM_RCL_GPRv_ONE_APX 
XED_IFORM_RCL_MEMb_CL 
XED_IFORM_RCL_MEMb_IMMb 
XED_IFORM_RCL_MEMb_ONE 
XED_IFORM_RCL_MEMi8_CL_APX 
XED_IFORM_RCL_MEMi8_IMM8_APX 
XED_IFORM_RCL_MEMi8_ONE_APX 
XED_IFORM_RCL_MEMv_CL 
XED_IFORM_RCL_MEMv_CL_APX 
XED_IFORM_RCL_MEMv_IMM8_APX 
XED_IFORM_RCL_MEMv_IMMb 
XED_IFORM_RCL_MEMv_ONE 
XED_IFORM_RCL_MEMv_ONE_APX 
XED_IFORM_RCPPS_XMMps_MEMps 
XED_IFORM_RCPPS_XMMps_XMMps 
XED_IFORM_RCPSS_XMMss_MEMss 
XED_IFORM_RCPSS_XMMss_XMMss 
XED_IFORM_RCR_GPR8_CL 
XED_IFORM_RCR_GPR8_IMMb 
XED_IFORM_RCR_GPR8_ONE 
XED_IFORM_RCR_GPR8i8_CL_APX 
XED_IFORM_RCR_GPR8i8_GPR8i8_CL_APX 
XED_IFORM_RCR_GPR8i8_GPR8i8_IMM8_APX 
XED_IFORM_RCR_GPR8i8_GPR8i8_ONE_APX 
XED_IFORM_RCR_GPR8i8_IMM8_APX 
XED_IFORM_RCR_GPR8i8_MEMi8_CL_APX 
XED_IFORM_RCR_GPR8i8_MEMi8_IMM8_APX 
XED_IFORM_RCR_GPR8i8_MEMi8_ONE_APX 
XED_IFORM_RCR_GPR8i8_ONE_APX 
XED_IFORM_RCR_GPRv_CL 
XED_IFORM_RCR_GPRv_CL_APX 
XED_IFORM_RCR_GPRv_GPRv_CL_APX 
XED_IFORM_RCR_GPRv_GPRv_IMM8_APX 
XED_IFORM_RCR_GPRv_GPRv_ONE_APX 
XED_IFORM_RCR_GPRv_IMM8_APX 
XED_IFORM_RCR_GPRv_IMMb 
XED_IFORM_RCR_GPRv_MEMv_CL_APX 
XED_IFORM_RCR_GPRv_MEMv_IMM8_APX 
XED_IFORM_RCR_GPRv_MEMv_ONE_APX 
XED_IFORM_RCR_GPRv_ONE 
XED_IFORM_RCR_GPRv_ONE_APX 
XED_IFORM_RCR_MEMb_CL 
XED_IFORM_RCR_MEMb_IMMb 
XED_IFORM_RCR_MEMb_ONE 
XED_IFORM_RCR_MEMi8_CL_APX 
XED_IFORM_RCR_MEMi8_IMM8_APX 
XED_IFORM_RCR_MEMi8_ONE_APX 
XED_IFORM_RCR_MEMv_CL 
XED_IFORM_RCR_MEMv_CL_APX 
XED_IFORM_RCR_MEMv_IMM8_APX 
XED_IFORM_RCR_MEMv_IMMb 
XED_IFORM_RCR_MEMv_ONE 
XED_IFORM_RCR_MEMv_ONE_APX 
XED_IFORM_RDFSBASE_GPRy 
XED_IFORM_RDGSBASE_GPRy 
XED_IFORM_RDMSR 
XED_IFORM_RDMSR_GPR64u64_IMM32 
XED_IFORM_RDMSR_GPR64u64_IMM32_APX 
XED_IFORM_RDMSRLIST 
XED_IFORM_RDPID_GPR32u32 
XED_IFORM_RDPID_GPR64u64 
XED_IFORM_RDPKRU 
XED_IFORM_RDPMC 
XED_IFORM_RDPRU 
XED_IFORM_RDRAND_GPRv 
XED_IFORM_RDSEED_GPRv 
XED_IFORM_RDSSPD_GPR32u32 
XED_IFORM_RDSSPQ_GPR64u64 
XED_IFORM_RDTSC 
XED_IFORM_RDTSCP 
XED_IFORM_REPE_CMPSB 
XED_IFORM_REPE_CMPSD 
XED_IFORM_REPE_CMPSQ 
XED_IFORM_REPE_CMPSW 
XED_IFORM_REPE_SCASB 
XED_IFORM_REPE_SCASD 
XED_IFORM_REPE_SCASQ 
XED_IFORM_REPE_SCASW 
XED_IFORM_REPNE_CMPSB 
XED_IFORM_REPNE_CMPSD 
XED_IFORM_REPNE_CMPSQ 
XED_IFORM_REPNE_CMPSW 
XED_IFORM_REPNE_SCASB 
XED_IFORM_REPNE_SCASD 
XED_IFORM_REPNE_SCASQ 
XED_IFORM_REPNE_SCASW 
XED_IFORM_REP_INSB 
XED_IFORM_REP_INSD 
XED_IFORM_REP_INSW 
XED_IFORM_REP_LODSB 
XED_IFORM_REP_LODSD 
XED_IFORM_REP_LODSQ 
XED_IFORM_REP_LODSW 
XED_IFORM_REP_MONTMUL 
XED_IFORM_REP_MOVSB 
XED_IFORM_REP_MOVSD 
XED_IFORM_REP_MOVSQ 
XED_IFORM_REP_MOVSW 
XED_IFORM_REP_OUTSB 
XED_IFORM_REP_OUTSD 
XED_IFORM_REP_OUTSW 
XED_IFORM_REP_STOSB 
XED_IFORM_REP_STOSD 
XED_IFORM_REP_STOSQ 
XED_IFORM_REP_STOSW 
XED_IFORM_REP_XCRYPTCBC 
XED_IFORM_REP_XCRYPTCFB 
XED_IFORM_REP_XCRYPTCTR 
XED_IFORM_REP_XCRYPTECB 
XED_IFORM_REP_XCRYPTOFB 
XED_IFORM_REP_XSHA1 
XED_IFORM_REP_XSHA256 
XED_IFORM_REP_XSTORE 
XED_IFORM_RET_FAR 
XED_IFORM_RET_FAR_IMMw 
XED_IFORM_RET_NEAR 
XED_IFORM_RET_NEAR_IMMw 
XED_IFORM_RMPADJUST_RAX_RCX_RDX 
XED_IFORM_RMPUPDATE_RAX_RCX 
XED_IFORM_ROL_GPR8_CL 
XED_IFORM_ROL_GPR8_IMMb 
XED_IFORM_ROL_GPR8_ONE 
XED_IFORM_ROL_GPR8i8_CL_APX 
XED_IFORM_ROL_GPR8i8_GPR8i8_CL_APX 
XED_IFORM_ROL_GPR8i8_GPR8i8_IMM8_APX 
XED_IFORM_ROL_GPR8i8_GPR8i8_ONE_APX 
XED_IFORM_ROL_GPR8i8_IMM8_APX 
XED_IFORM_ROL_GPR8i8_MEMi8_CL_APX 
XED_IFORM_ROL_GPR8i8_MEMi8_IMM8_APX 
XED_IFORM_ROL_GPR8i8_MEMi8_ONE_APX 
XED_IFORM_ROL_GPR8i8_ONE_APX 
XED_IFORM_ROL_GPRv_CL 
XED_IFORM_ROL_GPRv_CL_APX 
XED_IFORM_ROL_GPRv_GPRv_CL_APX 
XED_IFORM_ROL_GPRv_GPRv_IMM8_APX 
XED_IFORM_ROL_GPRv_GPRv_ONE_APX 
XED_IFORM_ROL_GPRv_IMM8_APX 
XED_IFORM_ROL_GPRv_IMMb 
XED_IFORM_ROL_GPRv_MEMv_CL_APX 
XED_IFORM_ROL_GPRv_MEMv_IMM8_APX 
XED_IFORM_ROL_GPRv_MEMv_ONE_APX 
XED_IFORM_ROL_GPRv_ONE 
XED_IFORM_ROL_GPRv_ONE_APX 
XED_IFORM_ROL_MEMb_CL 
XED_IFORM_ROL_MEMb_IMMb 
XED_IFORM_ROL_MEMb_ONE 
XED_IFORM_ROL_MEMi8_CL_APX 
XED_IFORM_ROL_MEMi8_IMM8_APX 
XED_IFORM_ROL_MEMi8_ONE_APX 
XED_IFORM_ROL_MEMv_CL 
XED_IFORM_ROL_MEMv_CL_APX 
XED_IFORM_ROL_MEMv_IMM8_APX 
XED_IFORM_ROL_MEMv_IMMb 
XED_IFORM_ROL_MEMv_ONE 
XED_IFORM_ROL_MEMv_ONE_APX 
XED_IFORM_ROR_GPR8_CL 
XED_IFORM_ROR_GPR8_IMMb 
XED_IFORM_ROR_GPR8_ONE 
XED_IFORM_ROR_GPR8i8_CL_APX 
XED_IFORM_ROR_GPR8i8_GPR8i8_CL_APX 
XED_IFORM_ROR_GPR8i8_GPR8i8_IMM8_APX 
XED_IFORM_ROR_GPR8i8_GPR8i8_ONE_APX 
XED_IFORM_ROR_GPR8i8_IMM8_APX 
XED_IFORM_ROR_GPR8i8_MEMi8_CL_APX 
XED_IFORM_ROR_GPR8i8_MEMi8_IMM8_APX 
XED_IFORM_ROR_GPR8i8_MEMi8_ONE_APX 
XED_IFORM_ROR_GPR8i8_ONE_APX 
XED_IFORM_ROR_GPRv_CL 
XED_IFORM_ROR_GPRv_CL_APX 
XED_IFORM_ROR_GPRv_GPRv_CL_APX 
XED_IFORM_ROR_GPRv_GPRv_IMM8_APX 
XED_IFORM_ROR_GPRv_GPRv_ONE_APX 
XED_IFORM_ROR_GPRv_IMM8_APX 
XED_IFORM_ROR_GPRv_IMMb 
XED_IFORM_ROR_GPRv_MEMv_CL_APX 
XED_IFORM_ROR_GPRv_MEMv_IMM8_APX 
XED_IFORM_ROR_GPRv_MEMv_ONE_APX 
XED_IFORM_ROR_GPRv_ONE 
XED_IFORM_ROR_GPRv_ONE_APX 
XED_IFORM_ROR_MEMb_CL 
XED_IFORM_ROR_MEMb_IMMb 
XED_IFORM_ROR_MEMb_ONE 
XED_IFORM_ROR_MEMi8_CL_APX 
XED_IFORM_ROR_MEMi8_IMM8_APX 
XED_IFORM_ROR_MEMi8_ONE_APX 
XED_IFORM_ROR_MEMv_CL 
XED_IFORM_ROR_MEMv_CL_APX 
XED_IFORM_ROR_MEMv_IMM8_APX 
XED_IFORM_ROR_MEMv_IMMb 
XED_IFORM_ROR_MEMv_ONE 
XED_IFORM_ROR_MEMv_ONE_APX 
XED_IFORM_RORX_GPR32d_GPR32d_IMMb 
XED_IFORM_RORX_GPR32d_MEMd_IMMb 
XED_IFORM_RORX_GPR32i32_GPR32i32_IMM8_APX 
XED_IFORM_RORX_GPR32i32_MEMi32_IMM8_APX 
XED_IFORM_RORX_GPR64i64_GPR64i64_IMM8_APX 
XED_IFORM_RORX_GPR64i64_MEMi64_IMM8_APX 
XED_IFORM_RORX_GPR64q_GPR64q_IMMb 
XED_IFORM_RORX_GPR64q_MEMq_IMMb 
XED_IFORM_ROUNDPD_XMMpd_MEMpd_IMMb 
XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb 
XED_IFORM_ROUNDPS_XMMps_MEMps_IMMb 
XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb 
XED_IFORM_ROUNDSD_XMMq_MEMq_IMMb 
XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb 
XED_IFORM_ROUNDSS_XMMd_MEMd_IMMb 
XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb 
XED_IFORM_RSM 
XED_IFORM_RSQRTPS_XMMps_MEMps 
XED_IFORM_RSQRTPS_XMMps_XMMps 
XED_IFORM_RSQRTSS_XMMss_MEMss 
XED_IFORM_RSQRTSS_XMMss_XMMss 
XED_IFORM_RSTORSSP_MEMu64 
XED_IFORM_SAHF 
XED_IFORM_SALC 
XED_IFORM_SAR_GPR8_CL 
XED_IFORM_SAR_GPR8_IMMb 
XED_IFORM_SAR_GPR8_ONE 
XED_IFORM_SAR_GPR8i8_CL_APX 
XED_IFORM_SAR_GPR8i8_GPR8i8_CL_APX 
XED_IFORM_SAR_GPR8i8_GPR8i8_IMM8_APX 
XED_IFORM_SAR_GPR8i8_GPR8i8_ONE_APX 
XED_IFORM_SAR_GPR8i8_IMM8_APX 
XED_IFORM_SAR_GPR8i8_MEMi8_CL_APX 
XED_IFORM_SAR_GPR8i8_MEMi8_IMM8_APX 
XED_IFORM_SAR_GPR8i8_MEMi8_ONE_APX 
XED_IFORM_SAR_GPR8i8_ONE_APX 
XED_IFORM_SAR_GPRv_CL 
XED_IFORM_SAR_GPRv_CL_APX 
XED_IFORM_SAR_GPRv_GPRv_CL_APX 
XED_IFORM_SAR_GPRv_GPRv_IMM8_APX 
XED_IFORM_SAR_GPRv_GPRv_ONE_APX 
XED_IFORM_SAR_GPRv_IMM8_APX 
XED_IFORM_SAR_GPRv_IMMb 
XED_IFORM_SAR_GPRv_MEMv_CL_APX 
XED_IFORM_SAR_GPRv_MEMv_IMM8_APX 
XED_IFORM_SAR_GPRv_MEMv_ONE_APX 
XED_IFORM_SAR_GPRv_ONE 
XED_IFORM_SAR_GPRv_ONE_APX 
XED_IFORM_SAR_MEMb_CL 
XED_IFORM_SAR_MEMb_IMMb 
XED_IFORM_SAR_MEMb_ONE 
XED_IFORM_SAR_MEMi8_CL_APX 
XED_IFORM_SAR_MEMi8_IMM8_APX 
XED_IFORM_SAR_MEMi8_ONE_APX 
XED_IFORM_SAR_MEMv_CL 
XED_IFORM_SAR_MEMv_CL_APX 
XED_IFORM_SAR_MEMv_IMM8_APX 
XED_IFORM_SAR_MEMv_IMMb 
XED_IFORM_SAR_MEMv_ONE 
XED_IFORM_SAR_MEMv_ONE_APX 
XED_IFORM_SARX_GPR32d_GPR32d_GPR32d 
XED_IFORM_SARX_GPR32d_MEMd_GPR32d 
XED_IFORM_SARX_GPR32i32_GPR32i32_GPR32i32_APX 
XED_IFORM_SARX_GPR32i32_MEMi32_GPR32i32_APX 
XED_IFORM_SARX_GPR64i64_GPR64i64_GPR64i64_APX 
XED_IFORM_SARX_GPR64i64_MEMi64_GPR64i64_APX 
XED_IFORM_SARX_GPR64q_GPR64q_GPR64q 
XED_IFORM_SARX_GPR64q_MEMq_GPR64q 
XED_IFORM_SAVEPREVSSP 
XED_IFORM_SBB_AL_IMMb 
XED_IFORM_SBB_GPR8_GPR8_18 
XED_IFORM_SBB_GPR8_GPR8_1A 
XED_IFORM_SBB_GPR8_IMMb_80r3 
XED_IFORM_SBB_GPR8_IMMb_82r3 
XED_IFORM_SBB_GPR8_MEMb 
XED_IFORM_SBB_GPR8i8_GPR8i8_APX 
XED_IFORM_SBB_GPR8i8_GPR8i8_GPR8i8_APX 
XED_IFORM_SBB_GPR8i8_GPR8i8_IMM8_APX 
XED_IFORM_SBB_GPR8i8_GPR8i8_MEMi8_APX 
XED_IFORM_SBB_GPR8i8_IMM8_APX 
XED_IFORM_SBB_GPR8i8_MEMi8_APX 
XED_IFORM_SBB_GPR8i8_MEMi8_GPR8i8_APX 
XED_IFORM_SBB_GPR8i8_MEMi8_IMM8_APX 
XED_IFORM_SBB_GPRv_GPRv_19 
XED_IFORM_SBB_GPRv_GPRv_1B 
XED_IFORM_SBB_GPRv_GPRv_APX 
XED_IFORM_SBB_GPRv_GPRv_GPRv_APX 
XED_IFORM_SBB_GPRv_GPRv_IMM8_APX 
XED_IFORM_SBB_GPRv_GPRv_IMMz_APX 
XED_IFORM_SBB_GPRv_GPRv_MEMv_APX 
XED_IFORM_SBB_GPRv_IMM8_APX 
XED_IFORM_SBB_GPRv_IMMb 
XED_IFORM_SBB_GPRv_IMMz 
XED_IFORM_SBB_GPRv_IMMz_APX 
XED_IFORM_SBB_GPRv_MEMv 
XED_IFORM_SBB_GPRv_MEMv_APX 
XED_IFORM_SBB_GPRv_MEMv_GPRv_APX 
XED_IFORM_SBB_GPRv_MEMv_IMM8_APX 
XED_IFORM_SBB_GPRv_MEMv_IMMz_APX 
XED_IFORM_SBB_MEMb_GPR8 
XED_IFORM_SBB_MEMb_IMMb_80r3 
XED_IFORM_SBB_MEMb_IMMb_82r3 
XED_IFORM_SBB_MEMi8_GPR8i8_APX 
XED_IFORM_SBB_MEMi8_IMM8_APX 
XED_IFORM_SBB_MEMv_GPRv 
XED_IFORM_SBB_MEMv_GPRv_APX 
XED_IFORM_SBB_MEMv_IMM8_APX 
XED_IFORM_SBB_MEMv_IMMb 
XED_IFORM_SBB_MEMv_IMMz 
XED_IFORM_SBB_MEMv_IMMz_APX 
XED_IFORM_SBB_OrAX_IMMz 
XED_IFORM_SBB_LOCK_MEMb_GPR8 
XED_IFORM_SBB_LOCK_MEMb_IMMb_80r3 
XED_IFORM_SBB_LOCK_MEMb_IMMb_82r3 
XED_IFORM_SBB_LOCK_MEMv_GPRv 
XED_IFORM_SBB_LOCK_MEMv_IMMb 
XED_IFORM_SBB_LOCK_MEMv_IMMz 
XED_IFORM_SCASB 
XED_IFORM_SCASD 
XED_IFORM_SCASQ 
XED_IFORM_SCASW 
XED_IFORM_SEAMCALL 
XED_IFORM_SEAMOPS 
XED_IFORM_SEAMRET 
XED_IFORM_SENDUIPI_GPR64u32 
XED_IFORM_SERIALIZE 
XED_IFORM_SETB_GPR8 
XED_IFORM_SETB_GPR8i8_APX 
XED_IFORM_SETB_GPR8i8_APX_ZU 
XED_IFORM_SETB_MEMb 
XED_IFORM_SETB_MEMi8_APX 
XED_IFORM_SETB_MEMi8_APX_ZU 
XED_IFORM_SETBE_GPR8 
XED_IFORM_SETBE_GPR8i8_APX 
XED_IFORM_SETBE_GPR8i8_APX_ZU 
XED_IFORM_SETBE_MEMb 
XED_IFORM_SETBE_MEMi8_APX 
XED_IFORM_SETBE_MEMi8_APX_ZU 
XED_IFORM_SETL_GPR8 
XED_IFORM_SETL_GPR8i8_APX 
XED_IFORM_SETL_GPR8i8_APX_ZU 
XED_IFORM_SETL_MEMb 
XED_IFORM_SETL_MEMi8_APX 
XED_IFORM_SETL_MEMi8_APX_ZU 
XED_IFORM_SETLE_GPR8 
XED_IFORM_SETLE_GPR8i8_APX 
XED_IFORM_SETLE_GPR8i8_APX_ZU 
XED_IFORM_SETLE_MEMb 
XED_IFORM_SETLE_MEMi8_APX 
XED_IFORM_SETLE_MEMi8_APX_ZU 
XED_IFORM_SETNB_GPR8 
XED_IFORM_SETNB_GPR8i8_APX 
XED_IFORM_SETNB_GPR8i8_APX_ZU 
XED_IFORM_SETNB_MEMb 
XED_IFORM_SETNB_MEMi8_APX 
XED_IFORM_SETNB_MEMi8_APX_ZU 
XED_IFORM_SETNBE_GPR8 
XED_IFORM_SETNBE_GPR8i8_APX 
XED_IFORM_SETNBE_GPR8i8_APX_ZU 
XED_IFORM_SETNBE_MEMb 
XED_IFORM_SETNBE_MEMi8_APX 
XED_IFORM_SETNBE_MEMi8_APX_ZU 
XED_IFORM_SETNL_GPR8 
XED_IFORM_SETNL_GPR8i8_APX 
XED_IFORM_SETNL_GPR8i8_APX_ZU 
XED_IFORM_SETNL_MEMb 
XED_IFORM_SETNL_MEMi8_APX 
XED_IFORM_SETNL_MEMi8_APX_ZU 
XED_IFORM_SETNLE_GPR8 
XED_IFORM_SETNLE_GPR8i8_APX 
XED_IFORM_SETNLE_GPR8i8_APX_ZU 
XED_IFORM_SETNLE_MEMb 
XED_IFORM_SETNLE_MEMi8_APX 
XED_IFORM_SETNLE_MEMi8_APX_ZU 
XED_IFORM_SETNO_GPR8 
XED_IFORM_SETNO_GPR8i8_APX 
XED_IFORM_SETNO_GPR8i8_APX_ZU 
XED_IFORM_SETNO_MEMb 
XED_IFORM_SETNO_MEMi8_APX 
XED_IFORM_SETNO_MEMi8_APX_ZU 
XED_IFORM_SETNP_GPR8 
XED_IFORM_SETNP_GPR8i8_APX 
XED_IFORM_SETNP_GPR8i8_APX_ZU 
XED_IFORM_SETNP_MEMb 
XED_IFORM_SETNP_MEMi8_APX 
XED_IFORM_SETNP_MEMi8_APX_ZU 
XED_IFORM_SETNS_GPR8 
XED_IFORM_SETNS_GPR8i8_APX 
XED_IFORM_SETNS_GPR8i8_APX_ZU 
XED_IFORM_SETNS_MEMb 
XED_IFORM_SETNS_MEMi8_APX 
XED_IFORM_SETNS_MEMi8_APX_ZU 
XED_IFORM_SETNZ_GPR8 
XED_IFORM_SETNZ_GPR8i8_APX 
XED_IFORM_SETNZ_GPR8i8_APX_ZU 
XED_IFORM_SETNZ_MEMb 
XED_IFORM_SETNZ_MEMi8_APX 
XED_IFORM_SETNZ_MEMi8_APX_ZU 
XED_IFORM_SETO_GPR8 
XED_IFORM_SETO_GPR8i8_APX 
XED_IFORM_SETO_GPR8i8_APX_ZU 
XED_IFORM_SETO_MEMb 
XED_IFORM_SETO_MEMi8_APX 
XED_IFORM_SETO_MEMi8_APX_ZU 
XED_IFORM_SETP_GPR8 
XED_IFORM_SETP_GPR8i8_APX 
XED_IFORM_SETP_GPR8i8_APX_ZU 
XED_IFORM_SETP_MEMb 
XED_IFORM_SETP_MEMi8_APX 
XED_IFORM_SETP_MEMi8_APX_ZU 
XED_IFORM_SETS_GPR8 
XED_IFORM_SETS_GPR8i8_APX 
XED_IFORM_SETS_GPR8i8_APX_ZU 
XED_IFORM_SETS_MEMb 
XED_IFORM_SETS_MEMi8_APX 
XED_IFORM_SETS_MEMi8_APX_ZU 
XED_IFORM_SETSSBSY 
XED_IFORM_SETZ_GPR8 
XED_IFORM_SETZ_GPR8i8_APX 
XED_IFORM_SETZ_GPR8i8_APX_ZU 
XED_IFORM_SETZ_MEMb 
XED_IFORM_SETZ_MEMi8_APX 
XED_IFORM_SETZ_MEMi8_APX_ZU 
XED_IFORM_SFENCE 
XED_IFORM_SGDT_MEMs 
XED_IFORM_SGDT_MEMs64 
XED_IFORM_SHA1MSG1_XMMi32_MEMi32_SHA 
XED_IFORM_SHA1MSG1_XMMi32_XMMi32_SHA 
XED_IFORM_SHA1MSG2_XMMi32_MEMi32_SHA 
XED_IFORM_SHA1MSG2_XMMi32_XMMi32_SHA 
XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_SHA 
XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_SHA 
XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA 
XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA 
XED_IFORM_SHA256MSG1_XMMi32_MEMi32_SHA 
XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA 
XED_IFORM_SHA256MSG2_XMMi32_MEMi32_SHA 
XED_IFORM_SHA256MSG2_XMMi32_XMMi32_SHA 
XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_SHA 
XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_SHA 
XED_IFORM_SHL_GPR8_CL_D2r4 
XED_IFORM_SHL_GPR8_CL_D2r6 
XED_IFORM_SHL_GPR8_IMMb_C0r4 
XED_IFORM_SHL_GPR8_IMMb_C0r6 
XED_IFORM_SHL_GPR8_ONE_D0r4 
XED_IFORM_SHL_GPR8_ONE_D0r6 
XED_IFORM_SHL_GPR8i8_CL_APX 
XED_IFORM_SHL_GPR8i8_GPR8i8_CL_APX 
XED_IFORM_SHL_GPR8i8_GPR8i8_IMM8_APX 
XED_IFORM_SHL_GPR8i8_GPR8i8_ONE_APX 
XED_IFORM_SHL_GPR8i8_IMM8_APX 
XED_IFORM_SHL_GPR8i8_MEMi8_CL_APX 
XED_IFORM_SHL_GPR8i8_MEMi8_IMM8_APX 
XED_IFORM_SHL_GPR8i8_MEMi8_ONE_APX 
XED_IFORM_SHL_GPR8i8_ONE_APX 
XED_IFORM_SHL_GPRv_CL_APX 
XED_IFORM_SHL_GPRv_CL_D3r4 
XED_IFORM_SHL_GPRv_CL_D3r6 
XED_IFORM_SHL_GPRv_GPRv_CL_APX 
XED_IFORM_SHL_GPRv_GPRv_IMM8_APX 
XED_IFORM_SHL_GPRv_GPRv_ONE_APX 
XED_IFORM_SHL_GPRv_IMM8_APX 
XED_IFORM_SHL_GPRv_IMMb_C1r4 
XED_IFORM_SHL_GPRv_IMMb_C1r6 
XED_IFORM_SHL_GPRv_MEMv_CL_APX 
XED_IFORM_SHL_GPRv_MEMv_IMM8_APX 
XED_IFORM_SHL_GPRv_MEMv_ONE_APX 
XED_IFORM_SHL_GPRv_ONE_APX 
XED_IFORM_SHL_GPRv_ONE_D1r4 
XED_IFORM_SHL_GPRv_ONE_D1r6 
XED_IFORM_SHL_MEMb_CL_D2r4 
XED_IFORM_SHL_MEMb_CL_D2r6 
XED_IFORM_SHL_MEMb_IMMb_C0r4 
XED_IFORM_SHL_MEMb_IMMb_C0r6 
XED_IFORM_SHL_MEMb_ONE_D0r4 
XED_IFORM_SHL_MEMb_ONE_D0r6 
XED_IFORM_SHL_MEMi8_CL_APX 
XED_IFORM_SHL_MEMi8_IMM8_APX 
XED_IFORM_SHL_MEMi8_ONE_APX 
XED_IFORM_SHL_MEMv_CL_APX 
XED_IFORM_SHL_MEMv_CL_D3r4 
XED_IFORM_SHL_MEMv_CL_D3r6 
XED_IFORM_SHL_MEMv_IMM8_APX 
XED_IFORM_SHL_MEMv_IMMb_C1r4 
XED_IFORM_SHL_MEMv_IMMb_C1r6 
XED_IFORM_SHL_MEMv_ONE_APX 
XED_IFORM_SHL_MEMv_ONE_D1r4 
XED_IFORM_SHL_MEMv_ONE_D1r6 
XED_IFORM_SHLD_GPRv_GPRv_CL 
XED_IFORM_SHLD_GPRv_GPRv_CL_APX 
XED_IFORM_SHLD_GPRv_GPRv_GPRv_CL_APX 
XED_IFORM_SHLD_GPRv_GPRv_GPRv_IMM8_APX 
XED_IFORM_SHLD_GPRv_GPRv_IMM8_APX 
XED_IFORM_SHLD_GPRv_GPRv_IMMb 
XED_IFORM_SHLD_GPRv_MEMv_GPRv_CL_APX 
XED_IFORM_SHLD_GPRv_MEMv_GPRv_IMM8_APX 
XED_IFORM_SHLD_MEMv_GPRv_CL 
XED_IFORM_SHLD_MEMv_GPRv_CL_APX 
XED_IFORM_SHLD_MEMv_GPRv_IMM8_APX 
XED_IFORM_SHLD_MEMv_GPRv_IMMb 
XED_IFORM_SHLX_GPR32d_GPR32d_GPR32d 
XED_IFORM_SHLX_GPR32d_MEMd_GPR32d 
XED_IFORM_SHLX_GPR32i32_GPR32i32_GPR32i32_APX 
XED_IFORM_SHLX_GPR32i32_MEMi32_GPR32i32_APX 
XED_IFORM_SHLX_GPR64i64_GPR64i64_GPR64i64_APX 
XED_IFORM_SHLX_GPR64i64_MEMi64_GPR64i64_APX 
XED_IFORM_SHLX_GPR64q_GPR64q_GPR64q 
XED_IFORM_SHLX_GPR64q_MEMq_GPR64q 
XED_IFORM_SHR_GPR8_CL 
XED_IFORM_SHR_GPR8_IMMb 
XED_IFORM_SHR_GPR8_ONE 
XED_IFORM_SHR_GPR8i8_CL_APX 
XED_IFORM_SHR_GPR8i8_GPR8i8_CL_APX 
XED_IFORM_SHR_GPR8i8_GPR8i8_IMM8_APX 
XED_IFORM_SHR_GPR8i8_GPR8i8_ONE_APX 
XED_IFORM_SHR_GPR8i8_IMM8_APX 
XED_IFORM_SHR_GPR8i8_MEMi8_CL_APX 
XED_IFORM_SHR_GPR8i8_MEMi8_IMM8_APX 
XED_IFORM_SHR_GPR8i8_MEMi8_ONE_APX 
XED_IFORM_SHR_GPR8i8_ONE_APX 
XED_IFORM_SHR_GPRv_CL 
XED_IFORM_SHR_GPRv_CL_APX 
XED_IFORM_SHR_GPRv_GPRv_CL_APX 
XED_IFORM_SHR_GPRv_GPRv_IMM8_APX 
XED_IFORM_SHR_GPRv_GPRv_ONE_APX 
XED_IFORM_SHR_GPRv_IMM8_APX 
XED_IFORM_SHR_GPRv_IMMb 
XED_IFORM_SHR_GPRv_MEMv_CL_APX 
XED_IFORM_SHR_GPRv_MEMv_IMM8_APX 
XED_IFORM_SHR_GPRv_MEMv_ONE_APX 
XED_IFORM_SHR_GPRv_ONE 
XED_IFORM_SHR_GPRv_ONE_APX 
XED_IFORM_SHR_MEMb_CL 
XED_IFORM_SHR_MEMb_IMMb 
XED_IFORM_SHR_MEMb_ONE 
XED_IFORM_SHR_MEMi8_CL_APX 
XED_IFORM_SHR_MEMi8_IMM8_APX 
XED_IFORM_SHR_MEMi8_ONE_APX 
XED_IFORM_SHR_MEMv_CL 
XED_IFORM_SHR_MEMv_CL_APX 
XED_IFORM_SHR_MEMv_IMM8_APX 
XED_IFORM_SHR_MEMv_IMMb 
XED_IFORM_SHR_MEMv_ONE 
XED_IFORM_SHR_MEMv_ONE_APX 
XED_IFORM_SHRD_GPRv_GPRv_CL 
XED_IFORM_SHRD_GPRv_GPRv_CL_APX 
XED_IFORM_SHRD_GPRv_GPRv_GPRv_CL_APX 
XED_IFORM_SHRD_GPRv_GPRv_GPRv_IMM8_APX 
XED_IFORM_SHRD_GPRv_GPRv_IMM8_APX 
XED_IFORM_SHRD_GPRv_GPRv_IMMb 
XED_IFORM_SHRD_GPRv_MEMv_GPRv_CL_APX 
XED_IFORM_SHRD_GPRv_MEMv_GPRv_IMM8_APX 
XED_IFORM_SHRD_MEMv_GPRv_CL 
XED_IFORM_SHRD_MEMv_GPRv_CL_APX 
XED_IFORM_SHRD_MEMv_GPRv_IMM8_APX 
XED_IFORM_SHRD_MEMv_GPRv_IMMb 
XED_IFORM_SHRX_GPR32d_GPR32d_GPR32d 
XED_IFORM_SHRX_GPR32d_MEMd_GPR32d 
XED_IFORM_SHRX_GPR32i32_GPR32i32_GPR32i32_APX 
XED_IFORM_SHRX_GPR32i32_MEMi32_GPR32i32_APX 
XED_IFORM_SHRX_GPR64i64_GPR64i64_GPR64i64_APX 
XED_IFORM_SHRX_GPR64i64_MEMi64_GPR64i64_APX 
XED_IFORM_SHRX_GPR64q_GPR64q_GPR64q 
XED_IFORM_SHRX_GPR64q_MEMq_GPR64q 
XED_IFORM_SHUFPD_XMMpd_MEMpd_IMMb 
XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb 
XED_IFORM_SHUFPS_XMMps_MEMps_IMMb 
XED_IFORM_SHUFPS_XMMps_XMMps_IMMb 
XED_IFORM_SIDT_MEMs 
XED_IFORM_SIDT_MEMs64 
XED_IFORM_SKINIT_EAX 
XED_IFORM_SLDT_GPRv 
XED_IFORM_SLDT_MEMw 
XED_IFORM_SLWPCB_GPRyy 
XED_IFORM_SMSW_GPRv 
XED_IFORM_SMSW_MEMw 
XED_IFORM_SQRTPD_XMMpd_MEMpd 
XED_IFORM_SQRTPD_XMMpd_XMMpd 
XED_IFORM_SQRTPS_XMMps_MEMps 
XED_IFORM_SQRTPS_XMMps_XMMps 
XED_IFORM_SQRTSD_XMMsd_MEMsd 
XED_IFORM_SQRTSD_XMMsd_XMMsd 
XED_IFORM_SQRTSS_XMMss_MEMss 
XED_IFORM_SQRTSS_XMMss_XMMss 
XED_IFORM_STAC 
XED_IFORM_STC 
XED_IFORM_STD 
XED_IFORM_STGI 
XED_IFORM_STI 
XED_IFORM_STMXCSR_MEMd 
XED_IFORM_STOSB 
XED_IFORM_STOSD 
XED_IFORM_STOSQ 
XED_IFORM_STOSW 
XED_IFORM_STR_GPRv 
XED_IFORM_STR_MEMw 
XED_IFORM_STTILECFG_MEM 
XED_IFORM_STTILECFG_MEM_APX 
XED_IFORM_STUI 
XED_IFORM_SUB_AL_IMMb 
XED_IFORM_SUB_GPR8_GPR8_28 
XED_IFORM_SUB_GPR8_GPR8_2A 
XED_IFORM_SUB_GPR8_IMMb_80r5 
XED_IFORM_SUB_GPR8_IMMb_82r5 
XED_IFORM_SUB_GPR8_MEMb 
XED_IFORM_SUB_GPR8i8_GPR8i8_APX 
XED_IFORM_SUB_GPR8i8_GPR8i8_GPR8i8_APX 
XED_IFORM_SUB_GPR8i8_GPR8i8_IMM8_APX 
XED_IFORM_SUB_GPR8i8_GPR8i8_MEMi8_APX 
XED_IFORM_SUB_GPR8i8_IMM8_APX 
XED_IFORM_SUB_GPR8i8_MEMi8_APX 
XED_IFORM_SUB_GPR8i8_MEMi8_GPR8i8_APX 
XED_IFORM_SUB_GPR8i8_MEMi8_IMM8_APX 
XED_IFORM_SUB_GPRv_GPRv_29 
XED_IFORM_SUB_GPRv_GPRv_2B 
XED_IFORM_SUB_GPRv_GPRv_APX 
XED_IFORM_SUB_GPRv_GPRv_GPRv_APX 
XED_IFORM_SUB_GPRv_GPRv_IMM8_APX 
XED_IFORM_SUB_GPRv_GPRv_IMMz_APX 
XED_IFORM_SUB_GPRv_GPRv_MEMv_APX 
XED_IFORM_SUB_GPRv_IMM8_APX 
XED_IFORM_SUB_GPRv_IMMb 
XED_IFORM_SUB_GPRv_IMMz 
XED_IFORM_SUB_GPRv_IMMz_APX 
XED_IFORM_SUB_GPRv_MEMv 
XED_IFORM_SUB_GPRv_MEMv_APX 
XED_IFORM_SUB_GPRv_MEMv_GPRv_APX 
XED_IFORM_SUB_GPRv_MEMv_IMM8_APX 
XED_IFORM_SUB_GPRv_MEMv_IMMz_APX 
XED_IFORM_SUB_MEMb_GPR8 
XED_IFORM_SUB_MEMb_IMMb_80r5 
XED_IFORM_SUB_MEMb_IMMb_82r5 
XED_IFORM_SUB_MEMi8_GPR8i8_APX 
XED_IFORM_SUB_MEMi8_IMM8_APX 
XED_IFORM_SUB_MEMv_GPRv 
XED_IFORM_SUB_MEMv_GPRv_APX 
XED_IFORM_SUB_MEMv_IMM8_APX 
XED_IFORM_SUB_MEMv_IMMb 
XED_IFORM_SUB_MEMv_IMMz 
XED_IFORM_SUB_MEMv_IMMz_APX 
XED_IFORM_SUB_OrAX_IMMz 
XED_IFORM_SUBPD_XMMpd_MEMpd 
XED_IFORM_SUBPD_XMMpd_XMMpd 
XED_IFORM_SUBPS_XMMps_MEMps 
XED_IFORM_SUBPS_XMMps_XMMps 
XED_IFORM_SUBSD_XMMsd_MEMsd 
XED_IFORM_SUBSD_XMMsd_XMMsd 
XED_IFORM_SUBSS_XMMss_MEMss 
XED_IFORM_SUBSS_XMMss_XMMss 
XED_IFORM_SUB_LOCK_MEMb_GPR8 
XED_IFORM_SUB_LOCK_MEMb_IMMb_80r5 
XED_IFORM_SUB_LOCK_MEMb_IMMb_82r5 
XED_IFORM_SUB_LOCK_MEMv_GPRv 
XED_IFORM_SUB_LOCK_MEMv_IMMb 
XED_IFORM_SUB_LOCK_MEMv_IMMz 
XED_IFORM_SWAPGS 
XED_IFORM_SYSCALL 
XED_IFORM_SYSCALL_AMD 
XED_IFORM_SYSENTER 
XED_IFORM_SYSEXIT 
XED_IFORM_SYSRET 
XED_IFORM_SYSRET64 
XED_IFORM_SYSRET_AMD 
XED_IFORM_T1MSKC_GPR32d_GPR32d 
XED_IFORM_T1MSKC_GPR32d_MEMd 
XED_IFORM_T1MSKC_GPRyy_GPRyy 
XED_IFORM_T1MSKC_GPRyy_MEMy 
XED_IFORM_T2RPNTLVWZ0_TMM2u16_MEMu16 
XED_IFORM_T2RPNTLVWZ0_TMM2u16_MEMu16_APX 
XED_IFORM_T2RPNTLVWZ0RS_TMM2u16_MEMu16 
XED_IFORM_T2RPNTLVWZ0RS_TMM2u16_MEMu16_APX 
XED_IFORM_T2RPNTLVWZ0RST1_TMM2u16_MEMu16 
XED_IFORM_T2RPNTLVWZ0RST1_TMM2u16_MEMu16_APX 
XED_IFORM_T2RPNTLVWZ0T1_TMM2u16_MEMu16 
XED_IFORM_T2RPNTLVWZ0T1_TMM2u16_MEMu16_APX 
XED_IFORM_T2RPNTLVWZ1_TMM2u16_MEMu16 
XED_IFORM_T2RPNTLVWZ1_TMM2u16_MEMu16_APX 
XED_IFORM_T2RPNTLVWZ1RS_TMM2u16_MEMu16 
XED_IFORM_T2RPNTLVWZ1RS_TMM2u16_MEMu16_APX 
XED_IFORM_T2RPNTLVWZ1RST1_TMM2u16_MEMu16 
XED_IFORM_T2RPNTLVWZ1RST1_TMM2u16_MEMu16_APX 
XED_IFORM_T2RPNTLVWZ1T1_TMM2u16_MEMu16 
XED_IFORM_T2RPNTLVWZ1T1_TMM2u16_MEMu16_APX 
XED_IFORM_TCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16 
XED_IFORM_TCMMRLFP16PS_TMMf32_TMM2f16_TMM2f16 
XED_IFORM_TCONJTCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16 
XED_IFORM_TCONJTFP16_TMM2f16_TMM2f16 
XED_IFORM_TCVTROWD2PS_ZMMf32_TMMu32_GPR32u32 
XED_IFORM_TCVTROWD2PS_ZMMf32_TMMu32_IMM8 
XED_IFORM_TCVTROWPS2BF16H_ZMMbf16_TMMf32_GPR32u32 
XED_IFORM_TCVTROWPS2BF16H_ZMMbf16_TMMf32_IMM8 
XED_IFORM_TCVTROWPS2BF16L_ZMMbf16_TMMf32_GPR32u32 
XED_IFORM_TCVTROWPS2BF16L_ZMMbf16_TMMf32_IMM8 
XED_IFORM_TCVTROWPS2PHH_ZMMf16_TMMf32_GPR32u32 
XED_IFORM_TCVTROWPS2PHH_ZMMf16_TMMf32_IMM8 
XED_IFORM_TCVTROWPS2PHL_ZMMf16_TMMf32_GPR32u32 
XED_IFORM_TCVTROWPS2PHL_ZMMf16_TMMf32_IMM8 
XED_IFORM_TDCALL 
XED_IFORM_TDPBF16PS_TMMf32_TMM2bf16_TMM2bf16 
XED_IFORM_TDPBF8PS_TMMf32_TMM4bf8_TMM4bf8 
XED_IFORM_TDPBHF8PS_TMMf32_TMM4bf8_TMM4hf8 
XED_IFORM_TDPBSSD_TMMi32_TMM4i8_TMM4i8 
XED_IFORM_TDPBSUD_TMMi32_TMM4i8_TMM4u8 
XED_IFORM_TDPBUSD_TMMi32_TMM4u8_TMM4i8 
XED_IFORM_TDPBUUD_TMMu32_TMM4u8_TMM4u8 
XED_IFORM_TDPFP16PS_TMMf32_TMM2f16_TMM2f16 
XED_IFORM_TDPHBF8PS_TMMf32_TMM4hf8_TMM4bf8 
XED_IFORM_TDPHF8PS_TMMf32_TMM4hf8_TMM4hf8 
XED_IFORM_TEST_AL_IMMb 
XED_IFORM_TEST_GPR8_GPR8 
XED_IFORM_TEST_GPR8_IMMb_F6r0 
XED_IFORM_TEST_GPR8_IMMb_F6r1 
XED_IFORM_TEST_GPRv_GPRv 
XED_IFORM_TEST_GPRv_IMMz_F7r0 
XED_IFORM_TEST_GPRv_IMMz_F7r1 
XED_IFORM_TEST_MEMb_GPR8 
XED_IFORM_TEST_MEMb_IMMb_F6r0 
XED_IFORM_TEST_MEMb_IMMb_F6r1 
XED_IFORM_TEST_MEMv_GPRv 
XED_IFORM_TEST_MEMv_IMMz_F7r0 
XED_IFORM_TEST_MEMv_IMMz_F7r1 
XED_IFORM_TEST_OrAX_IMMz 
XED_IFORM_TESTUI 
XED_IFORM_TILELOADD_TMMu32_MEMu32 
XED_IFORM_TILELOADD_TMMu32_MEMu32_APX 
XED_IFORM_TILELOADDRS_TMMu32_MEMu32 
XED_IFORM_TILELOADDRS_TMMu32_MEMu32_APX 
XED_IFORM_TILELOADDRST1_TMMu32_MEMu32 
XED_IFORM_TILELOADDRST1_TMMu32_MEMu32_APX 
XED_IFORM_TILELOADDT1_TMMu32_MEMu32 
XED_IFORM_TILELOADDT1_TMMu32_MEMu32_APX 
XED_IFORM_TILEMOVROW_ZMMu8_TMMu8_GPR32u32 
XED_IFORM_TILEMOVROW_ZMMu8_TMMu8_IMM8 
XED_IFORM_TILERELEASE 
XED_IFORM_TILESTORED_MEMu32_TMMu32 
XED_IFORM_TILESTORED_MEMu32_TMMu32_APX 
XED_IFORM_TILEZERO_TMMu32 
XED_IFORM_TLBSYNC 
XED_IFORM_TMMULTF32PS_TMMf32_TMMf32_TMMf32 
XED_IFORM_TPAUSE_GPR32u32 
XED_IFORM_TTCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16 
XED_IFORM_TTCMMRLFP16PS_TMMf32_TMM2f16_TMM2f16 
XED_IFORM_TTDPBF16PS_TMMf32_TMMbf16_TMMbf16 
XED_IFORM_TTDPFP16PS_TMMf32_TMMf16_TMMf16 
XED_IFORM_TTMMULTF32PS_TMMf32_TMMf32_TMMf32 
XED_IFORM_TTRANSPOSED_TMMu32_TMMu32 
XED_IFORM_TZCNT_GPRv_GPRv 
XED_IFORM_TZCNT_GPRv_GPRv_APX 
XED_IFORM_TZCNT_GPRv_MEMv 
XED_IFORM_TZCNT_GPRv_MEMv_APX 
XED_IFORM_TZMSK_GPR32d_GPR32d 
XED_IFORM_TZMSK_GPR32d_MEMd 
XED_IFORM_TZMSK_GPRyy_GPRyy 
XED_IFORM_TZMSK_GPRyy_MEMy 
XED_IFORM_UCOMISD_XMMsd_MEMsd 
XED_IFORM_UCOMISD_XMMsd_XMMsd 
XED_IFORM_UCOMISS_XMMss_MEMss 
XED_IFORM_UCOMISS_XMMss_XMMss 
XED_IFORM_UD0 
XED_IFORM_UD0_GPR32_GPR32 
XED_IFORM_UD0_GPR32_MEMd 
XED_IFORM_UD1_GPR32_GPR32 
XED_IFORM_UD1_GPR32_MEMd 
XED_IFORM_UD2 
XED_IFORM_UIRET 
XED_IFORM_UMONITOR_GPRa 
XED_IFORM_UMWAIT_GPR32 
XED_IFORM_UNPCKHPD_XMMpd_MEMdq 
XED_IFORM_UNPCKHPD_XMMpd_XMMq 
XED_IFORM_UNPCKHPS_XMMps_MEMdq 
XED_IFORM_UNPCKHPS_XMMps_XMMdq 
XED_IFORM_UNPCKLPD_XMMpd_MEMdq 
XED_IFORM_UNPCKLPD_XMMpd_XMMq 
XED_IFORM_UNPCKLPS_XMMps_MEMdq 
XED_IFORM_UNPCKLPS_XMMps_XMMq 
XED_IFORM_URDMSR_GPR64u64_GPR64u64 
XED_IFORM_URDMSR_GPR64u64_GPR64u64_APX 
XED_IFORM_URDMSR_GPR64u64_IMM32 
XED_IFORM_URDMSR_GPR64u64_IMM32_APX 
XED_IFORM_UWRMSR_GPR64u64_GPR64u64 
XED_IFORM_UWRMSR_GPR64u64_GPR64u64_APX 
XED_IFORM_UWRMSR_IMM32_GPR64u64 
XED_IFORM_UWRMSR_IMM32_GPR64u64_APX 
XED_IFORM_V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VADDBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 
XED_IFORM_VADDBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 
XED_IFORM_VADDBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 
XED_IFORM_VADDBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 
XED_IFORM_VADDBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 
XED_IFORM_VADDBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 
XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VADDPS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VADDPS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VADDSD_XMMdq_XMMdq_MEMq 
XED_IFORM_VADDSD_XMMdq_XMMdq_XMMq 
XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd 
XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd 
XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VADDSUBPD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VADDSUBPD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VADDSUBPS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VADDSUBPS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VADDSUBPS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VADDSUBPS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VAESDEC_XMMdq_XMMdq_MEMdq 
XED_IFORM_VAESDEC_XMMdq_XMMdq_XMMdq 
XED_IFORM_VAESDEC_XMMu128_XMMu128_MEMu128_AVX512 
XED_IFORM_VAESDEC_XMMu128_XMMu128_XMMu128_AVX512 
XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128 
XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_AVX512 
XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128 
XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_AVX512 
XED_IFORM_VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512 
XED_IFORM_VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512 
XED_IFORM_VAESDECLAST_XMMdq_XMMdq_MEMdq 
XED_IFORM_VAESDECLAST_XMMdq_XMMdq_XMMdq 
XED_IFORM_VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512 
XED_IFORM_VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512 
XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128 
XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512 
XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128 
XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512 
XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512 
XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 
XED_IFORM_VAESENC_XMMdq_XMMdq_MEMdq 
XED_IFORM_VAESENC_XMMdq_XMMdq_XMMdq 
XED_IFORM_VAESENC_XMMu128_XMMu128_MEMu128_AVX512 
XED_IFORM_VAESENC_XMMu128_XMMu128_XMMu128_AVX512 
XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128 
XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_AVX512 
XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128 
XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_AVX512 
XED_IFORM_VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512 
XED_IFORM_VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512 
XED_IFORM_VAESENCLAST_XMMdq_XMMdq_MEMdq 
XED_IFORM_VAESENCLAST_XMMdq_XMMdq_XMMdq 
XED_IFORM_VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512 
XED_IFORM_VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512 
XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128 
XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512 
XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128 
XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512 
XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512 
XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 
XED_IFORM_VAESIMC_XMMdq_MEMdq 
XED_IFORM_VAESIMC_XMMdq_XMMdq 
XED_IFORM_VAESKEYGENASSIST_XMMdq_MEMdq_IMMb 
XED_IFORM_VAESKEYGENASSIST_XMMdq_XMMdq_IMMb 
XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 
XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 
XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 
XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 
XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 
XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 
XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 
XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 
XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 
XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 
XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 
XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 
XED_IFORM_VANDNPD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VANDNPD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VANDNPD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VANDNPD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VANDNPS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VANDNPS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VANDNPS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VANDNPS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VANDPD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VANDPD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VANDPD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VANDPD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VANDPS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VANDPS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VANDPS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VANDPS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VBCSTNEBF162PS_XMMf32_MEMbf16 
XED_IFORM_VBCSTNEBF162PS_YMMf32_MEMbf16 
XED_IFORM_VBCSTNESH2PS_XMMf32_MEMf16 
XED_IFORM_VBCSTNESH2PS_YMMf32_MEMf16 
XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb 
XED_IFORM_VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb 
XED_IFORM_VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb 
XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb 
XED_IFORM_VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb 
XED_IFORM_VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb 
XED_IFORM_VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb 
XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb 
XED_IFORM_VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq 
XED_IFORM_VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq 
XED_IFORM_VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq 
XED_IFORM_VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq 
XED_IFORM_VBROADCASTF128_YMMqq_MEMdq 
XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512 
XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512 
XED_IFORM_VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VBROADCASTI128_YMMqq_MEMdq 
XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512 
XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512 
XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512 
XED_IFORM_VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512 
XED_IFORM_VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512 
XED_IFORM_VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512 
XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512 
XED_IFORM_VBROADCASTSD_YMMqq_MEMq 
XED_IFORM_VBROADCASTSD_YMMqq_XMMdq 
XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512 
XED_IFORM_VBROADCASTSS_XMMdq_MEMd 
XED_IFORM_VBROADCASTSS_XMMdq_XMMdq 
XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512 
XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512 
XED_IFORM_VBROADCASTSS_YMMqq_MEMd 
XED_IFORM_VBROADCASTSS_YMMqq_XMMdq 
XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_XMMbf16_MEMbf16_IMM8_AVX512 
XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_XMMbf16_XMMbf16_IMM8_AVX512 
XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_YMMbf16_MEMbf16_IMM8_AVX512 
XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_YMMbf16_YMMbf16_IMM8_AVX512 
XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_ZMMbf16_MEMbf16_IMM8_AVX512 
XED_IFORM_VCMPBF16_MASKmskw_MASKmskw_ZMMbf16_ZMMbf16_IMM8_AVX512 
XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 
XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 
XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 
XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 
XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 
XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 
XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb 
XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb 
XED_IFORM_VCMPPD_YMMqq_YMMqq_MEMqq_IMMb 
XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb 
XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 
XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 
XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512 
XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512 
XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512 
XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512 
XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 
XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 
XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 
XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 
XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 
XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 
XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb 
XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb 
XED_IFORM_VCMPPS_YMMqq_YMMqq_MEMqq_IMMb 
XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb 
XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 
XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 
XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb 
XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb 
XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 
XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 
XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 
XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 
XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb 
XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb 
XED_IFORM_VCOMISBF16_XMMbf16_MEMbf16_AVX512 
XED_IFORM_VCOMISBF16_XMMbf16_XMMbf16_AVX512 
XED_IFORM_VCOMISD_XMMf64_MEMf64_AVX512 
XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512 
XED_IFORM_VCOMISD_XMMq_MEMq 
XED_IFORM_VCOMISD_XMMq_XMMq 
XED_IFORM_VCOMISH_XMMf16_MEMf16_AVX512 
XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512 
XED_IFORM_VCOMISS_XMMd_MEMd 
XED_IFORM_VCOMISS_XMMd_XMMd 
XED_IFORM_VCOMISS_XMMf32_MEMf32_AVX512 
XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512 
XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512 
XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512 
XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512 
XED_IFORM_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512 
XED_IFORM_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512 
XED_IFORM_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512 
XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512 
XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512 
XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512 
XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512 
XED_IFORM_VCOMXSD_XMMf64_MEMf64_AVX512 
XED_IFORM_VCOMXSD_XMMf64_XMMf64_AVX512 
XED_IFORM_VCOMXSH_XMMf16_MEMf16_AVX512 
XED_IFORM_VCOMXSH_XMMf16_XMMf16_AVX512 
XED_IFORM_VCOMXSS_XMMf32_MEMf32_AVX512 
XED_IFORM_VCOMXSS_XMMf32_XMMf32_AVX512 
XED_IFORM_VCVT2PH2BF8_XMMbf8_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VCVT2PH2BF8_XMMbf8_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VCVT2PH2BF8_YMMbf8_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VCVT2PH2BF8_YMMbf8_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VCVT2PH2BF8_ZMMbf8_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VCVT2PH2BF8_ZMMbf8_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VCVT2PH2BF8S_XMMbf8_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VCVT2PH2BF8S_XMMbf8_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VCVT2PH2BF8S_YMMbf8_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VCVT2PH2BF8S_YMMbf8_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VCVT2PH2BF8S_ZMMbf8_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VCVT2PH2BF8S_ZMMbf8_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VCVT2PH2HF8_XMMhf8_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VCVT2PH2HF8_XMMhf8_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VCVT2PH2HF8_YMMhf8_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VCVT2PH2HF8_YMMhf8_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VCVT2PH2HF8_ZMMhf8_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VCVT2PH2HF8_ZMMhf8_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VCVT2PH2HF8S_XMMhf8_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VCVT2PH2HF8S_XMMhf8_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VCVT2PH2HF8S_YMMhf8_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VCVT2PH2HF8S_YMMhf8_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VCVT2PH2HF8S_ZMMhf8_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VCVT2PH2HF8S_ZMMhf8_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VCVT2PS2PHX_XMMf16_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VCVT2PS2PHX_XMMf16_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VCVT2PS2PHX_YMMf16_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VCVT2PS2PHX_YMMf16_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VCVT2PS2PHX_ZMMf16_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VCVT2PS2PHX_ZMMf16_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VCVTBF162IBS_XMMi8_MASKmskw_MEMbf16_AVX512 
XED_IFORM_VCVTBF162IBS_XMMi8_MASKmskw_XMMbf16_AVX512 
XED_IFORM_VCVTBF162IBS_YMMi8_MASKmskw_MEMbf16_AVX512 
XED_IFORM_VCVTBF162IBS_YMMi8_MASKmskw_YMMbf16_AVX512 
XED_IFORM_VCVTBF162IBS_ZMMi8_MASKmskw_MEMbf16_AVX512 
XED_IFORM_VCVTBF162IBS_ZMMi8_MASKmskw_ZMMbf16_AVX512 
XED_IFORM_VCVTBF162IUBS_XMMu8_MASKmskw_MEMbf16_AVX512 
XED_IFORM_VCVTBF162IUBS_XMMu8_MASKmskw_XMMbf16_AVX512 
XED_IFORM_VCVTBF162IUBS_YMMu8_MASKmskw_MEMbf16_AVX512 
XED_IFORM_VCVTBF162IUBS_YMMu8_MASKmskw_YMMbf16_AVX512 
XED_IFORM_VCVTBF162IUBS_ZMMu8_MASKmskw_MEMbf16_AVX512 
XED_IFORM_VCVTBF162IUBS_ZMMu8_MASKmskw_ZMMbf16_AVX512 
XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128 
XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_XMM2i8_XMMf16_AVX512 
XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256 
XED_IFORM_VCVTBIASPH2BF8_XMMbf8_MASKmskw_YMM2i8_YMMf16_AVX512 
XED_IFORM_VCVTBIASPH2BF8_YMMbf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512 
XED_IFORM_VCVTBIASPH2BF8_YMMbf8_MASKmskw_ZMM2i8_ZMMf16_AVX512 
XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128 
XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_XMM2i8_XMMf16_AVX512 
XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256 
XED_IFORM_VCVTBIASPH2BF8S_XMMbf8_MASKmskw_YMM2i8_YMMf16_AVX512 
XED_IFORM_VCVTBIASPH2BF8S_YMMbf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512 
XED_IFORM_VCVTBIASPH2BF8S_YMMbf8_MASKmskw_ZMM2i8_ZMMf16_AVX512 
XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128 
XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_XMM2i8_XMMf16_AVX512 
XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256 
XED_IFORM_VCVTBIASPH2HF8_XMMhf8_MASKmskw_YMM2i8_YMMf16_AVX512 
XED_IFORM_VCVTBIASPH2HF8_YMMhf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512 
XED_IFORM_VCVTBIASPH2HF8_YMMhf8_MASKmskw_ZMM2i8_ZMMf16_AVX512 
XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_XMM2i8_MEMf16_AVX512_VL128 
XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_XMM2i8_XMMf16_AVX512 
XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_YMM2i8_MEMf16_AVX512_VL256 
XED_IFORM_VCVTBIASPH2HF8S_XMMhf8_MASKmskw_YMM2i8_YMMf16_AVX512 
XED_IFORM_VCVTBIASPH2HF8S_YMMhf8_MASKmskw_ZMM2i8_MEMf16_AVX512_VL512 
XED_IFORM_VCVTBIASPH2HF8S_YMMhf8_MASKmskw_ZMM2i8_ZMMf16_AVX512 
XED_IFORM_VCVTDQ2PD_XMMdq_MEMq 
XED_IFORM_VCVTDQ2PD_XMMdq_XMMq 
XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512 
XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512 
XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512 
XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512 
XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq 
XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq 
XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512 
XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512 
XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128 
XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256 
XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512 
XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512 
XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512 
XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512 
XED_IFORM_VCVTDQ2PS_XMMdq_MEMdq 
XED_IFORM_VCVTDQ2PS_XMMdq_XMMdq 
XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512 
XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512 
XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512 
XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512 
XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq 
XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq 
XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512 
XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512 
XED_IFORM_VCVTHF82PH_XMMf16_MASKmskw_MEMhf8_AVX512 
XED_IFORM_VCVTHF82PH_XMMf16_MASKmskw_XMMhf8_AVX512 
XED_IFORM_VCVTHF82PH_YMMf16_MASKmskw_MEMhf8_AVX512 
XED_IFORM_VCVTHF82PH_YMMf16_MASKmskw_XMMhf8_AVX512 
XED_IFORM_VCVTHF82PH_ZMMf16_MASKmskw_MEMhf8_AVX512 
XED_IFORM_VCVTHF82PH_ZMMf16_MASKmskw_YMMhf8_AVX512 
XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128 
XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256 
XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512 
XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VCVTNEEBF162PS_XMMf32_MEM2bf16 
XED_IFORM_VCVTNEEBF162PS_YMMf32_MEM2bf16 
XED_IFORM_VCVTNEEPH2PS_XMMf32_MEM2f16 
XED_IFORM_VCVTNEEPH2PS_YMMf32_MEM2f16 
XED_IFORM_VCVTNEOBF162PS_XMMf32_MEM2bf16 
XED_IFORM_VCVTNEOBF162PS_YMMf32_MEM2bf16 
XED_IFORM_VCVTNEOPH2PS_XMMf32_MEM2f16 
XED_IFORM_VCVTNEOPH2PS_YMMf32_MEM2f16 
XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128 
XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256 
XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512 
XED_IFORM_VCVTNEPS2BF16_XMMbf16_MEMf32_VL128 
XED_IFORM_VCVTNEPS2BF16_XMMbf16_MEMf32_VL256 
XED_IFORM_VCVTNEPS2BF16_XMMbf16_XMMf32 
XED_IFORM_VCVTNEPS2BF16_XMMbf16_YMMf32 
XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512 
XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512 
XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq 
XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq 
XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq 
XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq 
XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 
XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 
XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 
XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 
XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 
XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 
XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128 
XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256 
XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512 
XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512 
XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512 
XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512 
XED_IFORM_VCVTPD2PS_XMMdq_MEMdq 
XED_IFORM_VCVTPD2PS_XMMdq_MEMqq 
XED_IFORM_VCVTPD2PS_XMMdq_XMMdq 
XED_IFORM_VCVTPD2PS_XMMdq_YMMqq 
XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128 
XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256 
XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128 
XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256 
XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512 
XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512 
XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 
XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 
XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 
XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 
XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 
XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 
XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 
XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 
XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 
XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 
XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 
XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 
XED_IFORM_VCVTPH2BF8_XMMbf8_MASKmskw_MEMf16_AVX512_VL128 
XED_IFORM_VCVTPH2BF8_XMMbf8_MASKmskw_MEMf16_AVX512_VL256 
XED_IFORM_VCVTPH2BF8_XMMbf8_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTPH2BF8_XMMbf8_MASKmskw_YMMf16_AVX512 
XED_IFORM_VCVTPH2BF8_YMMbf8_MASKmskw_MEMf16_AVX512_VL512 
XED_IFORM_VCVTPH2BF8_YMMbf8_MASKmskw_ZMMf16_AVX512 
XED_IFORM_VCVTPH2BF8S_XMMbf8_MASKmskw_MEMf16_AVX512_VL128 
XED_IFORM_VCVTPH2BF8S_XMMbf8_MASKmskw_MEMf16_AVX512_VL256 
XED_IFORM_VCVTPH2BF8S_XMMbf8_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTPH2BF8S_XMMbf8_MASKmskw_YMMf16_AVX512 
XED_IFORM_VCVTPH2BF8S_YMMbf8_MASKmskw_MEMf16_AVX512_VL512 
XED_IFORM_VCVTPH2BF8S_YMMbf8_MASKmskw_ZMMf16_AVX512 
XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 
XED_IFORM_VCVTPH2HF8_XMMhf8_MASKmskw_MEMf16_AVX512_VL128 
XED_IFORM_VCVTPH2HF8_XMMhf8_MASKmskw_MEMf16_AVX512_VL256 
XED_IFORM_VCVTPH2HF8_XMMhf8_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTPH2HF8_XMMhf8_MASKmskw_YMMf16_AVX512 
XED_IFORM_VCVTPH2HF8_YMMhf8_MASKmskw_MEMf16_AVX512_VL512 
XED_IFORM_VCVTPH2HF8_YMMhf8_MASKmskw_ZMMf16_AVX512 
XED_IFORM_VCVTPH2HF8S_XMMhf8_MASKmskw_MEMf16_AVX512_VL128 
XED_IFORM_VCVTPH2HF8S_XMMhf8_MASKmskw_MEMf16_AVX512_VL256 
XED_IFORM_VCVTPH2HF8S_XMMhf8_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTPH2HF8S_XMMhf8_MASKmskw_YMMf16_AVX512 
XED_IFORM_VCVTPH2HF8S_YMMhf8_MASKmskw_MEMf16_AVX512_VL512 
XED_IFORM_VCVTPH2HF8S_YMMhf8_MASKmskw_ZMMf16_AVX512 
XED_IFORM_VCVTPH2IBS_XMMi8_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2IBS_XMMi8_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTPH2IBS_YMMi8_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2IBS_YMMi8_MASKmskw_YMMf16_AVX512 
XED_IFORM_VCVTPH2IBS_ZMMi8_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2IBS_ZMMi8_MASKmskw_ZMMf16_AVX512 
XED_IFORM_VCVTPH2IUBS_XMMu8_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2IUBS_XMMu8_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTPH2IUBS_YMMu8_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2IUBS_YMMu8_MASKmskw_YMMf16_AVX512 
XED_IFORM_VCVTPH2IUBS_ZMMu8_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2IUBS_ZMMu8_MASKmskw_ZMMf16_AVX512 
XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTPH2PS_XMMdq_MEMq 
XED_IFORM_VCVTPH2PS_XMMdq_XMMq 
XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTPH2PS_YMMqq_MEMdq 
XED_IFORM_VCVTPH2PS_YMMqq_XMMdq 
XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512 
XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512 
XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 
XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512 
XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 
XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512 
XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 
XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq 
XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq 
XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 
XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq 
XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq 
XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 
XED_IFORM_VCVTPS2IBS_XMMi8_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTPS2IBS_XMMi8_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCVTPS2IBS_YMMi8_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTPS2IBS_YMMi8_MASKmskw_YMMf32_AVX512 
XED_IFORM_VCVTPS2IBS_ZMMi8_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTPS2IBS_ZMMi8_MASKmskw_ZMMf32_AVX512 
XED_IFORM_VCVTPS2IUBS_XMMu8_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTPS2IUBS_XMMu8_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCVTPS2IUBS_YMMu8_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTPS2IUBS_YMMu8_MASKmskw_YMMf32_AVX512 
XED_IFORM_VCVTPS2IUBS_ZMMu8_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTPS2IUBS_ZMMu8_MASKmskw_ZMMf32_AVX512 
XED_IFORM_VCVTPS2PD_XMMdq_MEMq 
XED_IFORM_VCVTPS2PD_XMMdq_XMMq 
XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCVTPS2PD_YMMqq_MEMdq 
XED_IFORM_VCVTPS2PD_YMMqq_XMMdq 
XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512 
XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb 
XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512 
XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512 
XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512 
XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb 
XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb 
XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512 
XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512 
XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb 
XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512 
XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128 
XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256 
XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512 
XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512 
XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512 
XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 
XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 
XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 
XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 
XED_IFORM_VCVTQQ2PD_XMMf64_MASKmskw_MEMi64_AVX512 
XED_IFORM_VCVTQQ2PD_XMMf64_MASKmskw_XMMi64_AVX512 
XED_IFORM_VCVTQQ2PD_YMMf64_MASKmskw_MEMi64_AVX512 
XED_IFORM_VCVTQQ2PD_YMMf64_MASKmskw_YMMi64_AVX512 
XED_IFORM_VCVTQQ2PD_ZMMf64_MASKmskw_MEMi64_AVX512 
XED_IFORM_VCVTQQ2PD_ZMMf64_MASKmskw_ZMMi64_AVX512 
XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128 
XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256 
XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512 
XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512 
XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512 
XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 
XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 
XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 
XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 
XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 
XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 
XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 
XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VCVTSD2SI_GPR32d_MEMq 
XED_IFORM_VCVTSD2SI_GPR32d_XMMq 
XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512 
XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512 
XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512 
XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512 
XED_IFORM_VCVTSD2SI_GPR64q_MEMq 
XED_IFORM_VCVTSD2SI_GPR64q_XMMq 
XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq 
XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq 
XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512 
XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512 
XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512 
XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512 
XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512 
XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512 
XED_IFORM_VCVTSH2SI_GPR32i32_MEMf16_AVX512 
XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512 
XED_IFORM_VCVTSH2SI_GPR64i64_MEMf16_AVX512 
XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512 
XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512 
XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512 
XED_IFORM_VCVTSH2USI_GPR32u32_MEMf16_AVX512 
XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512 
XED_IFORM_VCVTSH2USI_GPR64u64_MEMf16_AVX512 
XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512 
XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d 
XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q 
XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd 
XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq 
XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512 
XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512 
XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512 
XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512 
XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512 
XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512 
XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512 
XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512 
XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d 
XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q 
XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd 
XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq 
XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 
XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512 
XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512 
XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512 
XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd 
XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd 
XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512 
XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512 
XED_IFORM_VCVTSS2SI_GPR32d_MEMd 
XED_IFORM_VCVTSS2SI_GPR32d_XMMd 
XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512 
XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512 
XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512 
XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512 
XED_IFORM_VCVTSS2SI_GPR64q_MEMd 
XED_IFORM_VCVTSS2SI_GPR64q_XMMd 
XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512 
XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512 
XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512 
XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512 
XED_IFORM_VCVTTBF162IBS_XMMi8_MASKmskw_MEMbf16_AVX512 
XED_IFORM_VCVTTBF162IBS_XMMi8_MASKmskw_XMMbf16_AVX512 
XED_IFORM_VCVTTBF162IBS_YMMi8_MASKmskw_MEMbf16_AVX512 
XED_IFORM_VCVTTBF162IBS_YMMi8_MASKmskw_YMMbf16_AVX512 
XED_IFORM_VCVTTBF162IBS_ZMMi8_MASKmskw_MEMbf16_AVX512 
XED_IFORM_VCVTTBF162IBS_ZMMi8_MASKmskw_ZMMbf16_AVX512 
XED_IFORM_VCVTTBF162IUBS_XMMu8_MASKmskw_MEMbf16_AVX512 
XED_IFORM_VCVTTBF162IUBS_XMMu8_MASKmskw_XMMbf16_AVX512 
XED_IFORM_VCVTTBF162IUBS_YMMu8_MASKmskw_MEMbf16_AVX512 
XED_IFORM_VCVTTBF162IUBS_YMMu8_MASKmskw_YMMbf16_AVX512 
XED_IFORM_VCVTTBF162IUBS_ZMMu8_MASKmskw_MEMbf16_AVX512 
XED_IFORM_VCVTTBF162IUBS_ZMMu8_MASKmskw_ZMMbf16_AVX512 
XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq 
XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq 
XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq 
XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq 
XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 
XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 
XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 
XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 
XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 
XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 
XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_MEMf64_AVX512_VL128 
XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_MEMf64_AVX512_VL256 
XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_XMMf64_AVX512 
XED_IFORM_VCVTTPD2DQS_XMMi32_MASKmskw_YMMf64_AVX512 
XED_IFORM_VCVTTPD2DQS_YMMi32_MASKmskw_MEMf64_AVX512_VL512 
XED_IFORM_VCVTTPD2DQS_YMMi32_MASKmskw_ZMMf64_AVX512 
XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 
XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 
XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 
XED_IFORM_VCVTTPD2QQS_XMMi64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VCVTTPD2QQS_XMMi64_MASKmskw_XMMf64_AVX512 
XED_IFORM_VCVTTPD2QQS_YMMi64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VCVTTPD2QQS_YMMi64_MASKmskw_YMMf64_AVX512 
XED_IFORM_VCVTTPD2QQS_ZMMi64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VCVTTPD2QQS_ZMMi64_MASKmskw_ZMMf64_AVX512 
XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 
XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 
XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 
XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 
XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 
XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 
XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_MEMf64_AVX512_VL128 
XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_MEMf64_AVX512_VL256 
XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_XMMf64_AVX512 
XED_IFORM_VCVTTPD2UDQS_XMMu32_MASKmskw_YMMf64_AVX512 
XED_IFORM_VCVTTPD2UDQS_YMMu32_MASKmskw_MEMf64_AVX512_VL512 
XED_IFORM_VCVTTPD2UDQS_YMMu32_MASKmskw_ZMMf64_AVX512 
XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 
XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 
XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 
XED_IFORM_VCVTTPD2UQQS_XMMu64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VCVTTPD2UQQS_XMMu64_MASKmskw_XMMf64_AVX512 
XED_IFORM_VCVTTPD2UQQS_YMMu64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VCVTTPD2UQQS_YMMu64_MASKmskw_YMMf64_AVX512 
XED_IFORM_VCVTTPD2UQQS_ZMMu64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VCVTTPD2UQQS_ZMMu64_MASKmskw_ZMMf64_AVX512 
XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 
XED_IFORM_VCVTTPH2IBS_XMMi8_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTTPH2IBS_XMMi8_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTTPH2IBS_YMMi8_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTTPH2IBS_YMMi8_MASKmskw_YMMf16_AVX512 
XED_IFORM_VCVTTPH2IBS_ZMMi8_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTTPH2IBS_ZMMi8_MASKmskw_ZMMf16_AVX512 
XED_IFORM_VCVTTPH2IUBS_XMMu8_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTTPH2IUBS_XMMu8_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTTPH2IUBS_YMMu8_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTTPH2IUBS_YMMu8_MASKmskw_YMMf16_AVX512 
XED_IFORM_VCVTTPH2IUBS_ZMMu8_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTTPH2IUBS_ZMMu8_MASKmskw_ZMMf16_AVX512 
XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 
XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512 
XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 
XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512 
XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512 
XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512 
XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 
XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq 
XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq 
XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 
XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq 
XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq 
XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 
XED_IFORM_VCVTTPS2DQS_XMMi32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2DQS_XMMi32_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCVTTPS2DQS_YMMi32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2DQS_YMMi32_MASKmskw_YMMf32_AVX512 
XED_IFORM_VCVTTPS2DQS_ZMMi32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2DQS_ZMMi32_MASKmskw_ZMMf32_AVX512 
XED_IFORM_VCVTTPS2IBS_XMMi8_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2IBS_XMMi8_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCVTTPS2IBS_YMMi8_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2IBS_YMMi8_MASKmskw_YMMf32_AVX512 
XED_IFORM_VCVTTPS2IBS_ZMMi8_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2IBS_ZMMi8_MASKmskw_ZMMf32_AVX512 
XED_IFORM_VCVTTPS2IUBS_XMMu8_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2IUBS_XMMu8_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCVTTPS2IUBS_YMMu8_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2IUBS_YMMu8_MASKmskw_YMMf32_AVX512 
XED_IFORM_VCVTTPS2IUBS_ZMMu8_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2IUBS_ZMMu8_MASKmskw_ZMMf32_AVX512 
XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 
XED_IFORM_VCVTTPS2QQS_XMMi64_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2QQS_XMMi64_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCVTTPS2QQS_YMMi64_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2QQS_YMMi64_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCVTTPS2QQS_ZMMi64_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2QQS_ZMMi64_MASKmskw_YMMf32_AVX512 
XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 
XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 
XED_IFORM_VCVTTPS2UDQS_XMMu32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2UDQS_XMMu32_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCVTTPS2UDQS_YMMu32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2UDQS_YMMu32_MASKmskw_YMMf32_AVX512 
XED_IFORM_VCVTTPS2UDQS_ZMMu32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2UDQS_ZMMu32_MASKmskw_ZMMf32_AVX512 
XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 
XED_IFORM_VCVTTPS2UQQS_XMMu64_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2UQQS_XMMu64_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCVTTPS2UQQS_YMMu64_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2UQQS_YMMu64_MASKmskw_XMMf32_AVX512 
XED_IFORM_VCVTTPS2UQQS_ZMMu64_MASKmskw_MEMf32_AVX512 
XED_IFORM_VCVTTPS2UQQS_ZMMu64_MASKmskw_YMMf32_AVX512 
XED_IFORM_VCVTTSD2SI_GPR32d_MEMq 
XED_IFORM_VCVTTSD2SI_GPR32d_XMMq 
XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512 
XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512 
XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512 
XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512 
XED_IFORM_VCVTTSD2SI_GPR64q_MEMq 
XED_IFORM_VCVTTSD2SI_GPR64q_XMMq 
XED_IFORM_VCVTTSD2SIS_GPR32i32_MEMf64_AVX512 
XED_IFORM_VCVTTSD2SIS_GPR32i32_XMMf64_AVX512 
XED_IFORM_VCVTTSD2SIS_GPR64i64_MEMf64_AVX512 
XED_IFORM_VCVTTSD2SIS_GPR64i64_XMMf64_AVX512 
XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512 
XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512 
XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512 
XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512 
XED_IFORM_VCVTTSD2USIS_GPR32u32_MEMf64_AVX512 
XED_IFORM_VCVTTSD2USIS_GPR32u32_XMMf64_AVX512 
XED_IFORM_VCVTTSD2USIS_GPR64u64_MEMf64_AVX512 
XED_IFORM_VCVTTSD2USIS_GPR64u64_XMMf64_AVX512 
XED_IFORM_VCVTTSH2SI_GPR32i32_MEMf16_AVX512 
XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512 
XED_IFORM_VCVTTSH2SI_GPR64i64_MEMf16_AVX512 
XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512 
XED_IFORM_VCVTTSH2USI_GPR32u32_MEMf16_AVX512 
XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512 
XED_IFORM_VCVTTSH2USI_GPR64u64_MEMf16_AVX512 
XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512 
XED_IFORM_VCVTTSS2SI_GPR32d_MEMd 
XED_IFORM_VCVTTSS2SI_GPR32d_XMMd 
XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512 
XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512 
XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512 
XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512 
XED_IFORM_VCVTTSS2SI_GPR64q_MEMd 
XED_IFORM_VCVTTSS2SI_GPR64q_XMMd 
XED_IFORM_VCVTTSS2SIS_GPR32i32_MEMf32_AVX512 
XED_IFORM_VCVTTSS2SIS_GPR32i32_XMMf32_AVX512 
XED_IFORM_VCVTTSS2SIS_GPR64i64_MEMf32_AVX512 
XED_IFORM_VCVTTSS2SIS_GPR64i64_XMMf32_AVX512 
XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512 
XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512 
XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512 
XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512 
XED_IFORM_VCVTTSS2USIS_GPR32u32_MEMf32_AVX512 
XED_IFORM_VCVTTSS2USIS_GPR32u32_XMMf32_AVX512 
XED_IFORM_VCVTTSS2USIS_GPR64u64_MEMf32_AVX512 
XED_IFORM_VCVTTSS2USIS_GPR64u64_XMMf32_AVX512 
XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512 
XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512 
XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512 
XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512 
XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512 
XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512 
XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128 
XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256 
XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512 
XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512 
XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512 
XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512 
XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512 
XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512 
XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512 
XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512 
XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512 
XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512 
XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512 
XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512 
XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512 
XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128 
XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256 
XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512 
XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512 
XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512 
XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 
XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 
XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 
XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 
XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 
XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 
XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 
XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512 
XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512 
XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512 
XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512 
XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512 
XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512 
XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512 
XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512 
XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 
XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512 
XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512 
XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512 
XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512 
XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512 
XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512 
XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512 
XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512 
XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512 
XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512 
XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512 
XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512 
XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512 
XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512 
XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512 
XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 
XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 
XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 
XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 
XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 
XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 
XED_IFORM_VDIVBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 
XED_IFORM_VDIVBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 
XED_IFORM_VDIVBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 
XED_IFORM_VDIVBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 
XED_IFORM_VDIVBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 
XED_IFORM_VDIVBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 
XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VDIVPS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VDIVPS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VDIVSD_XMMdq_XMMdq_MEMq 
XED_IFORM_VDIVSD_XMMdq_XMMdq_XMMq 
XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd 
XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd 
XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb 
XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb 
XED_IFORM_VDPPHPS_XMMf32_MASKmskw_XMM2f16_MEM2f16_AVX512 
XED_IFORM_VDPPHPS_XMMf32_MASKmskw_XMM2f16_XMM2f16_AVX512 
XED_IFORM_VDPPHPS_YMMf32_MASKmskw_YMM2f16_MEM2f16_AVX512 
XED_IFORM_VDPPHPS_YMMf32_MASKmskw_YMM2f16_YMM2f16_AVX512 
XED_IFORM_VDPPHPS_ZMMf32_MASKmskw_ZMM2f16_MEM2f16_AVX512 
XED_IFORM_VDPPHPS_ZMMf32_MASKmskw_ZMM2f16_ZMM2f16_AVX512 
XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb 
XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb 
XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb 
XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb 
XED_IFORM_VERR_GPR16 
XED_IFORM_VERR_MEMw 
XED_IFORM_VERW_GPR16 
XED_IFORM_VERW_MEMw 
XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER 
XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER 
XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER 
XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER 
XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512 
XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512 
XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512 
XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512 
XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512 
XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512 
XED_IFORM_VEXTRACTF128_MEMdq_YMMdq_IMMb 
XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb 
XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512 
XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 
XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512 
XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512 
XED_IFORM_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 
XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512 
XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512 
XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 
XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512 
XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512 
XED_IFORM_VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 
XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512 
XED_IFORM_VEXTRACTI128_MEMdq_YMMqq_IMMb 
XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb 
XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512 
XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 
XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512 
XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512 
XED_IFORM_VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 
XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512 
XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512 
XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 
XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512 
XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512 
XED_IFORM_VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 
XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512 
XED_IFORM_VEXTRACTPS_GPR32_XMMdq_IMMb 
XED_IFORM_VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512 
XED_IFORM_VEXTRACTPS_MEMd_XMMdq_IMMb 
XED_IFORM_VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512 
XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 
XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 
XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 
XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 
XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 
XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 
XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 
XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 
XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 
XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 
XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 
XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 
XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 
XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 
XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 
XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 
XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 
XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 
XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 
XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 
XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 
XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 
XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 
XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 
XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 
XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 
XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 
XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 
XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 
XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 
XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 
XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 
XED_IFORM_VFMADD132BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 
XED_IFORM_VFMADD132BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 
XED_IFORM_VFMADD132BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 
XED_IFORM_VFMADD132BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 
XED_IFORM_VFMADD132BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 
XED_IFORM_VFMADD132BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 
XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VFMADD132PS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMADD132PS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VFMADD132SD_XMMdq_XMMq_MEMq 
XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq 
XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd 
XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd 
XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFMADD213BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 
XED_IFORM_VFMADD213BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 
XED_IFORM_VFMADD213BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 
XED_IFORM_VFMADD213BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 
XED_IFORM_VFMADD213BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 
XED_IFORM_VFMADD213BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 
XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VFMADD213PS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMADD213PS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VFMADD213SD_XMMdq_XMMq_MEMq 
XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq 
XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd 
XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd 
XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFMADD231BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 
XED_IFORM_VFMADD231BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 
XED_IFORM_VFMADD231BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 
XED_IFORM_VFMADD231BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 
XED_IFORM_VFMADD231BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 
XED_IFORM_VFMADD231BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 
XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VFMADD231PS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMADD231PS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VFMADD231SD_XMMdq_XMMq_MEMq 
XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq 
XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd 
XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd 
XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 
XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 
XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 
XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 
XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 
XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 
XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 
XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 
XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq 
XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq 
XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMADDSD_XMMdq_XMMq_MEMq_XMMq 
XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_MEMq 
XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_XMMq 
XED_IFORM_VFMADDSS_XMMdq_XMMd_MEMd_XMMd 
XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_MEMd 
XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_XMMd 
XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq 
XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq 
XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMSUB132BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 
XED_IFORM_VFMSUB132BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 
XED_IFORM_VFMSUB132BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 
XED_IFORM_VFMSUB132BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 
XED_IFORM_VFMSUB132BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 
XED_IFORM_VFMSUB132BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 
XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VFMSUB132SD_XMMdq_XMMq_MEMq 
XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq 
XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd 
XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd 
XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFMSUB213BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 
XED_IFORM_VFMSUB213BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 
XED_IFORM_VFMSUB213BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 
XED_IFORM_VFMSUB213BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 
XED_IFORM_VFMSUB213BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 
XED_IFORM_VFMSUB213BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 
XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VFMSUB213SD_XMMdq_XMMq_MEMq 
XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq 
XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd 
XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd 
XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFMSUB231BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 
XED_IFORM_VFMSUB231BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 
XED_IFORM_VFMSUB231BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 
XED_IFORM_VFMSUB231BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 
XED_IFORM_VFMSUB231BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 
XED_IFORM_VFMSUB231BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 
XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VFMSUB231SD_XMMdq_XMMq_MEMq 
XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq 
XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd 
XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd 
XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq 
XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq 
XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq 
XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq 
XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFMSUBSD_XMMdq_XMMq_MEMq_XMMq 
XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_MEMq 
XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_XMMq 
XED_IFORM_VFMSUBSS_XMMdq_XMMd_MEMd_XMMd 
XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_MEMd 
XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_XMMd 
XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 
XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 
XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 
XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 
XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 
XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 
XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 
XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 
XED_IFORM_VFNMADD132BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 
XED_IFORM_VFNMADD132BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 
XED_IFORM_VFNMADD132BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 
XED_IFORM_VFNMADD132BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 
XED_IFORM_VFNMADD132BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 
XED_IFORM_VFNMADD132BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 
XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VFNMADD132SD_XMMdq_XMMq_MEMq 
XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq 
XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd 
XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd 
XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFNMADD213BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 
XED_IFORM_VFNMADD213BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 
XED_IFORM_VFNMADD213BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 
XED_IFORM_VFNMADD213BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 
XED_IFORM_VFNMADD213BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 
XED_IFORM_VFNMADD213BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 
XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VFNMADD213SD_XMMdq_XMMq_MEMq 
XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq 
XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd 
XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd 
XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFNMADD231BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 
XED_IFORM_VFNMADD231BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 
XED_IFORM_VFNMADD231BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 
XED_IFORM_VFNMADD231BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 
XED_IFORM_VFNMADD231BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 
XED_IFORM_VFNMADD231BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 
XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VFNMADD231SD_XMMdq_XMMq_MEMq 
XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq 
XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd 
XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd 
XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq 
XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq 
XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFNMADDSD_XMMdq_XMMq_MEMq_XMMq 
XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_MEMq 
XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_XMMq 
XED_IFORM_VFNMADDSS_XMMdq_XMMd_MEMd_XMMd 
XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_MEMd 
XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd 
XED_IFORM_VFNMSUB132BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 
XED_IFORM_VFNMSUB132BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 
XED_IFORM_VFNMSUB132BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 
XED_IFORM_VFNMSUB132BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 
XED_IFORM_VFNMSUB132BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 
XED_IFORM_VFNMSUB132BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 
XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_MEMq 
XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq 
XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd 
XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd 
XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFNMSUB213BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 
XED_IFORM_VFNMSUB213BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 
XED_IFORM_VFNMSUB213BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 
XED_IFORM_VFNMSUB213BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 
XED_IFORM_VFNMSUB213BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 
XED_IFORM_VFNMSUB213BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 
XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_MEMq 
XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq 
XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd 
XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd 
XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFNMSUB231BF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 
XED_IFORM_VFNMSUB231BF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 
XED_IFORM_VFNMSUB231BF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 
XED_IFORM_VFNMSUB231BF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 
XED_IFORM_VFNMSUB231BF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 
XED_IFORM_VFNMSUB231BF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 
XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_MEMq 
XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq 
XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd 
XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd 
XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq 
XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq 
XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq 
XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq 
XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq 
XED_IFORM_VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq 
XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq 
XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq 
XED_IFORM_VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd 
XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd 
XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd 
XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL128 
XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL256 
XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_MEMbf16_IMM8_AVX512_VL512 
XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_XMMbf16_IMM8_AVX512 
XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_YMMbf16_IMM8_AVX512 
XED_IFORM_VFPCLASSBF16_MASKi1_MASKmskw_ZMMbf16_IMM8_AVX512 
XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128 
XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256 
XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512 
XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 
XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512 
XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512 
XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128 
XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256 
XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512 
XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512 
XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512 
XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512 
XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128 
XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256 
XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512 
XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 
XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512 
XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512 
XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512 
XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 
XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512 
XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512 
XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512 
XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 
XED_IFORM_VFRCZPD_XMMdq_MEMdq 
XED_IFORM_VFRCZPD_XMMdq_XMMdq 
XED_IFORM_VFRCZPD_YMMqq_MEMqq 
XED_IFORM_VFRCZPD_YMMqq_YMMqq 
XED_IFORM_VFRCZPS_XMMdq_MEMdq 
XED_IFORM_VFRCZPS_XMMdq_XMMdq 
XED_IFORM_VFRCZPS_YMMqq_MEMqq 
XED_IFORM_VFRCZPS_YMMqq_YMMqq 
XED_IFORM_VFRCZSD_XMMdq_MEMq 
XED_IFORM_VFRCZSD_XMMdq_XMMq 
XED_IFORM_VFRCZSS_XMMdq_MEMd 
XED_IFORM_VFRCZSS_XMMdq_XMMd 
XED_IFORM_VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 
XED_IFORM_VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128 
XED_IFORM_VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 
XED_IFORM_VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256 
XED_IFORM_VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 
XED_IFORM_VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 
XED_IFORM_VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128 
XED_IFORM_VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256 
XED_IFORM_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256 
XED_IFORM_VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512 
XED_IFORM_VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 
XED_IFORM_VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 
XED_IFORM_VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 
XED_IFORM_VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 
XED_IFORM_VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 
XED_IFORM_VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 
XED_IFORM_VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 
XED_IFORM_VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 
XED_IFORM_VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 
XED_IFORM_VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128 
XED_IFORM_VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 
XED_IFORM_VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256 
XED_IFORM_VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 
XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 
XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256 
XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128 
XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256 
XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512 
XED_IFORM_VGETEXPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512 
XED_IFORM_VGETEXPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512 
XED_IFORM_VGETEXPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512 
XED_IFORM_VGETEXPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512 
XED_IFORM_VGETEXPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512 
XED_IFORM_VGETEXPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512 
XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512 
XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512 
XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512 
XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512 
XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512 
XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512 
XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512 
XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512 
XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512 
XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512 
XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512 
XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512 
XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VGETMANTBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512 
XED_IFORM_VGETMANTBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512 
XED_IFORM_VGETMANTBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512 
XED_IFORM_VGETMANTBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512 
XED_IFORM_VGETMANTBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512 
XED_IFORM_VGETMANTBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512 
XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 
XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 
XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 
XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 
XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 
XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 
XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 
XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 
XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 
XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 
XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 
XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 
XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 
XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 
XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 
XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 
XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 
XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 
XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 
XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 
XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 
XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 
XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 
XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 
XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 
XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 
XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8 
XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8 
XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 
XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 
XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8 
XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8 
XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 
XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 
XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 
XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 
XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8 
XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8 
XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 
XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 
XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8 
XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8 
XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 
XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 
XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 
XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 
XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_MEMu8 
XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_XMMu8 
XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 
XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 
XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_MEMu8 
XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_YMMu8 
XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 
XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 
XED_IFORM_VHADDPD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VHADDPD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VHADDPD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VHADDPD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VHADDPS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VHADDPS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VHADDPS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VHADDPS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VHSUBPD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VHSUBPD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VHSUBPD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VHSUBPD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VHSUBPS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VHSUBPS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VHSUBPS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VHSUBPS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb 
XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb 
XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 
XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512 
XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 
XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512 
XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 
XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512 
XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 
XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512 
XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 
XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512 
XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 
XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512 
XED_IFORM_VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb 
XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb 
XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 
XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512 
XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 
XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512 
XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 
XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512 
XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 
XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512 
XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 
XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512 
XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 
XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512 
XED_IFORM_VINSERTPS_XMMdq_XMMdq_MEMd_IMMb 
XED_IFORM_VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb 
XED_IFORM_VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512 
XED_IFORM_VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512 
XED_IFORM_VLDDQU_XMMdq_MEMdq 
XED_IFORM_VLDDQU_YMMqq_MEMqq 
XED_IFORM_VLDMXCSR_MEMd 
XED_IFORM_VMASKMOVDQU_XMMxub_XMMxub 
XED_IFORM_VMASKMOVPD_MEMdq_XMMdq_XMMdq 
XED_IFORM_VMASKMOVPD_MEMqq_YMMqq_YMMqq 
XED_IFORM_VMASKMOVPD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VMASKMOVPD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VMASKMOVPS_MEMdq_XMMdq_XMMdq 
XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq 
XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VMAXBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 
XED_IFORM_VMAXBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 
XED_IFORM_VMAXBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 
XED_IFORM_VMAXBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 
XED_IFORM_VMAXBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 
XED_IFORM_VMAXBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 
XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VMAXPS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VMAXPS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VMAXSD_XMMdq_XMMdq_MEMq 
XED_IFORM_VMAXSD_XMMdq_XMMdq_XMMq 
XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd 
XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd 
XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VMCALL 
XED_IFORM_VMCLEAR_MEMq 
XED_IFORM_VMFUNC 
XED_IFORM_VMINBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 
XED_IFORM_VMINBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 
XED_IFORM_VMINBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 
XED_IFORM_VMINBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 
XED_IFORM_VMINBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 
XED_IFORM_VMINBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 
XED_IFORM_VMINMAXBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_IMM8_AVX512 
XED_IFORM_VMINMAXBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_IMM8_AVX512 
XED_IFORM_VMINMAXBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_IMM8_AVX512 
XED_IFORM_VMINMAXBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_IMM8_AVX512 
XED_IFORM_VMINMAXBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_IMM8_AVX512 
XED_IFORM_VMINMAXBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_IMM8_AVX512 
XED_IFORM_VMINMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 
XED_IFORM_VMINMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 
XED_IFORM_VMINMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 
XED_IFORM_VMINMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 
XED_IFORM_VMINMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 
XED_IFORM_VMINMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 
XED_IFORM_VMINMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 
XED_IFORM_VMINMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 
XED_IFORM_VMINMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_IMM8_AVX512 
XED_IFORM_VMINMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_IMM8_AVX512 
XED_IFORM_VMINMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512 
XED_IFORM_VMINMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512 
XED_IFORM_VMINMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 
XED_IFORM_VMINMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 
XED_IFORM_VMINMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 
XED_IFORM_VMINMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 
XED_IFORM_VMINMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 
XED_IFORM_VMINMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 
XED_IFORM_VMINMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 
XED_IFORM_VMINMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 
XED_IFORM_VMINMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 
XED_IFORM_VMINMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 
XED_IFORM_VMINMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 
XED_IFORM_VMINMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 
XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VMINPS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VMINPS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VMINSD_XMMdq_XMMdq_MEMq 
XED_IFORM_VMINSD_XMMdq_XMMdq_XMMq 
XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd 
XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd 
XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VMLAUNCH 
XED_IFORM_VMLOAD_ArAX 
XED_IFORM_VMMCALL 
XED_IFORM_VMOVAPD_MEMdq_XMMdq 
XED_IFORM_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512 
XED_IFORM_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512 
XED_IFORM_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512 
XED_IFORM_VMOVAPD_MEMqq_YMMqq 
XED_IFORM_VMOVAPD_XMMdq_MEMdq 
XED_IFORM_VMOVAPD_XMMdq_XMMdq_28 
XED_IFORM_VMOVAPD_XMMdq_XMMdq_29 
XED_IFORM_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512 
XED_IFORM_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512 
XED_IFORM_VMOVAPD_YMMqq_MEMqq 
XED_IFORM_VMOVAPD_YMMqq_YMMqq_28 
XED_IFORM_VMOVAPD_YMMqq_YMMqq_29 
XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512 
XED_IFORM_VMOVAPS_MEMdq_XMMdq 
XED_IFORM_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512 
XED_IFORM_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512 
XED_IFORM_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512 
XED_IFORM_VMOVAPS_MEMqq_YMMqq 
XED_IFORM_VMOVAPS_XMMdq_MEMdq 
XED_IFORM_VMOVAPS_XMMdq_XMMdq_28 
XED_IFORM_VMOVAPS_XMMdq_XMMdq_29 
XED_IFORM_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512 
XED_IFORM_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512 
XED_IFORM_VMOVAPS_YMMqq_MEMqq 
XED_IFORM_VMOVAPS_YMMqq_YMMqq_28 
XED_IFORM_VMOVAPS_YMMqq_YMMqq_29 
XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512 
XED_IFORM_VMOVD_GPR32d_XMMd 
XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512 
XED_IFORM_VMOVD_MEMd_XMMd 
XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512 
XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512_MOVZXC 
XED_IFORM_VMOVD_XMMdq_GPR32d 
XED_IFORM_VMOVD_XMMdq_MEMd 
XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512 
XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512 
XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512_MOVZXC 
XED_IFORM_VMOVD_XMMu32_XMMu32_AVX512_MOVZXC 
XED_IFORM_VMOVDDUP_XMMdq_MEMq 
XED_IFORM_VMOVDDUP_XMMdq_XMMq 
XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512 
XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512 
XED_IFORM_VMOVDDUP_YMMqq_MEMqq 
XED_IFORM_VMOVDDUP_YMMqq_YMMqq 
XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512 
XED_IFORM_VMOVDQA_MEMdq_XMMdq 
XED_IFORM_VMOVDQA_MEMqq_YMMqq 
XED_IFORM_VMOVDQA_XMMdq_MEMdq 
XED_IFORM_VMOVDQA_XMMdq_XMMdq_6F 
XED_IFORM_VMOVDQA_XMMdq_XMMdq_7F 
XED_IFORM_VMOVDQA_YMMqq_MEMqq 
XED_IFORM_VMOVDQA_YMMqq_YMMqq_6F 
XED_IFORM_VMOVDQA_YMMqq_YMMqq_7F 
XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512 
XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512 
XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512 
XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512 
XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512 
XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512 
XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512 
XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512 
XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512 
XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512 
XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512 
XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512 
XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512 
XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512 
XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512 
XED_IFORM_VMOVDQU_MEMdq_XMMdq 
XED_IFORM_VMOVDQU_MEMqq_YMMqq 
XED_IFORM_VMOVDQU_XMMdq_MEMdq 
XED_IFORM_VMOVDQU_XMMdq_XMMdq_6F 
XED_IFORM_VMOVDQU_XMMdq_XMMdq_7F 
XED_IFORM_VMOVDQU_YMMqq_MEMqq 
XED_IFORM_VMOVDQU_YMMqq_YMMqq_6F 
XED_IFORM_VMOVDQU_YMMqq_YMMqq_7F 
XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512 
XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512 
XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512 
XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512 
XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512 
XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512 
XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512 
XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512 
XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512 
XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512 
XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512 
XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512 
XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512 
XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512 
XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512 
XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512 
XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512 
XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512 
XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512 
XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512 
XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512 
XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512 
XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512 
XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512 
XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512 
XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512 
XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512 
XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512 
XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512 
XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512 
XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512 
XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512 
XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512 
XED_IFORM_VMOVHLPS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512 
XED_IFORM_VMOVHPD_MEMf64_XMMf64_AVX512 
XED_IFORM_VMOVHPD_MEMq_XMMdq 
XED_IFORM_VMOVHPD_XMMdq_XMMq_MEMq 
XED_IFORM_VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512 
XED_IFORM_VMOVHPS_MEMf32_XMMf32_AVX512 
XED_IFORM_VMOVHPS_MEMq_XMMdq 
XED_IFORM_VMOVHPS_XMMdq_XMMq_MEMq 
XED_IFORM_VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512 
XED_IFORM_VMOVLHPS_XMMdq_XMMq_XMMq 
XED_IFORM_VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512 
XED_IFORM_VMOVLPD_MEMf64_XMMf64_AVX512 
XED_IFORM_VMOVLPD_MEMq_XMMq 
XED_IFORM_VMOVLPD_XMMdq_XMMdq_MEMq 
XED_IFORM_VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512 
XED_IFORM_VMOVLPS_MEMf32_XMMf32_AVX512 
XED_IFORM_VMOVLPS_MEMq_XMMq 
XED_IFORM_VMOVLPS_XMMdq_XMMdq_MEMq 
XED_IFORM_VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512 
XED_IFORM_VMOVMSKPD_GPR32d_XMMdq 
XED_IFORM_VMOVMSKPD_GPR32d_YMMqq 
XED_IFORM_VMOVMSKPS_GPR32d_XMMdq 
XED_IFORM_VMOVMSKPS_GPR32d_YMMqq 
XED_IFORM_VMOVNTDQ_MEMdq_XMMdq 
XED_IFORM_VMOVNTDQ_MEMqq_YMMqq 
XED_IFORM_VMOVNTDQ_MEMu32_XMMu32_AVX512 
XED_IFORM_VMOVNTDQ_MEMu32_YMMu32_AVX512 
XED_IFORM_VMOVNTDQ_MEMu32_ZMMu32_AVX512 
XED_IFORM_VMOVNTDQA_XMMdq_MEMdq 
XED_IFORM_VMOVNTDQA_XMMu32_MEMu32_AVX512 
XED_IFORM_VMOVNTDQA_YMMqq_MEMqq 
XED_IFORM_VMOVNTDQA_YMMu32_MEMu32_AVX512 
XED_IFORM_VMOVNTDQA_ZMMu32_MEMu32_AVX512 
XED_IFORM_VMOVNTPD_MEMdq_XMMdq 
XED_IFORM_VMOVNTPD_MEMf64_XMMf64_AVX512 
XED_IFORM_VMOVNTPD_MEMf64_YMMf64_AVX512 
XED_IFORM_VMOVNTPD_MEMf64_ZMMf64_AVX512 
XED_IFORM_VMOVNTPD_MEMqq_YMMqq 
XED_IFORM_VMOVNTPS_MEMdq_XMMdq 
XED_IFORM_VMOVNTPS_MEMf32_XMMf32_AVX512 
XED_IFORM_VMOVNTPS_MEMf32_YMMf32_AVX512 
XED_IFORM_VMOVNTPS_MEMf32_ZMMf32_AVX512 
XED_IFORM_VMOVNTPS_MEMqq_YMMqq 
XED_IFORM_VMOVQ_GPR64q_XMMq 
XED_IFORM_VMOVQ_GPR64u64_XMMu64_AVX512 
XED_IFORM_VMOVQ_MEMq_XMMq_7E 
XED_IFORM_VMOVQ_MEMq_XMMq_D6 
XED_IFORM_VMOVQ_MEMu64_XMMu64_AVX512 
XED_IFORM_VMOVQ_XMMdq_GPR64q 
XED_IFORM_VMOVQ_XMMdq_MEMq_6E 
XED_IFORM_VMOVQ_XMMdq_MEMq_7E 
XED_IFORM_VMOVQ_XMMdq_XMMq_7E 
XED_IFORM_VMOVQ_XMMdq_XMMq_D6 
XED_IFORM_VMOVQ_XMMu64_GPR64u64_AVX512 
XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512 
XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512 
XED_IFORM_VMOVRSB_XMMu8_MASKmskw_MEMu8_AVX512 
XED_IFORM_VMOVRSB_YMMu8_MASKmskw_MEMu8_AVX512 
XED_IFORM_VMOVRSB_ZMMu8_MASKmskw_MEMu8_AVX512 
XED_IFORM_VMOVRSD_XMMu32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VMOVRSD_YMMu32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VMOVRSD_ZMMu32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VMOVRSQ_XMMu64_MASKmskw_MEMu64_AVX512 
XED_IFORM_VMOVRSQ_YMMu64_MASKmskw_MEMu64_AVX512 
XED_IFORM_VMOVRSQ_ZMMu64_MASKmskw_MEMu64_AVX512 
XED_IFORM_VMOVRSW_XMMu16_MASKmskw_MEMu16_AVX512 
XED_IFORM_VMOVRSW_YMMu16_MASKmskw_MEMu16_AVX512 
XED_IFORM_VMOVRSW_ZMMu16_MASKmskw_MEMu16_AVX512 
XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512 
XED_IFORM_VMOVSD_MEMq_XMMq 
XED_IFORM_VMOVSD_XMMdq_MEMq 
XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_10 
XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_11 
XED_IFORM_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512 
XED_IFORM_VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512 
XED_IFORM_VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VMOVSHDUP_XMMdq_MEMdq 
XED_IFORM_VMOVSHDUP_XMMdq_XMMdq 
XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512 
XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512 
XED_IFORM_VMOVSHDUP_YMMqq_MEMqq 
XED_IFORM_VMOVSHDUP_YMMqq_YMMqq 
XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 
XED_IFORM_VMOVSLDUP_XMMdq_MEMdq 
XED_IFORM_VMOVSLDUP_XMMdq_XMMdq 
XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512 
XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512 
XED_IFORM_VMOVSLDUP_YMMqq_MEMqq 
XED_IFORM_VMOVSLDUP_YMMqq_YMMqq 
XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 
XED_IFORM_VMOVSS_MEMd_XMMd 
XED_IFORM_VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512 
XED_IFORM_VMOVSS_XMMdq_MEMd 
XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_10 
XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_11 
XED_IFORM_VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VMOVUPD_MEMdq_XMMdq 
XED_IFORM_VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512 
XED_IFORM_VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512 
XED_IFORM_VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512 
XED_IFORM_VMOVUPD_MEMqq_YMMqq 
XED_IFORM_VMOVUPD_XMMdq_MEMdq 
XED_IFORM_VMOVUPD_XMMdq_XMMdq_10 
XED_IFORM_VMOVUPD_XMMdq_XMMdq_11 
XED_IFORM_VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512 
XED_IFORM_VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512 
XED_IFORM_VMOVUPD_YMMqq_MEMqq 
XED_IFORM_VMOVUPD_YMMqq_YMMqq_10 
XED_IFORM_VMOVUPD_YMMqq_YMMqq_11 
XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512 
XED_IFORM_VMOVUPS_MEMdq_XMMdq 
XED_IFORM_VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512 
XED_IFORM_VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512 
XED_IFORM_VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512 
XED_IFORM_VMOVUPS_MEMqq_YMMqq 
XED_IFORM_VMOVUPS_XMMdq_MEMdq 
XED_IFORM_VMOVUPS_XMMdq_XMMdq_10 
XED_IFORM_VMOVUPS_XMMdq_XMMdq_11 
XED_IFORM_VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512 
XED_IFORM_VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512 
XED_IFORM_VMOVUPS_YMMqq_MEMqq 
XED_IFORM_VMOVUPS_YMMqq_YMMqq_10 
XED_IFORM_VMOVUPS_YMMqq_YMMqq_11 
XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512 
XED_IFORM_VMOVW_GPR32f16_XMMf16_AVX512 
XED_IFORM_VMOVW_MEMf16_XMMf16_AVX512 
XED_IFORM_VMOVW_MEMu16_XMMu16_AVX512_MOVZXC 
XED_IFORM_VMOVW_XMMf16_GPR32f16_AVX512 
XED_IFORM_VMOVW_XMMf16_MEMf16_AVX512 
XED_IFORM_VMOVW_XMMu16_MEMu16_AVX512_MOVZXC 
XED_IFORM_VMOVW_XMMu16_XMMu16_AVX512_MOVZXC 
XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb 
XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb 
XED_IFORM_VMPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 
XED_IFORM_VMPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 
XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb 
XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb 
XED_IFORM_VMPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 
XED_IFORM_VMPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 
XED_IFORM_VMPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 
XED_IFORM_VMPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 
XED_IFORM_VMPTRLD_MEMq 
XED_IFORM_VMPTRST_MEMq 
XED_IFORM_VMREAD_GPR32_GPR32 
XED_IFORM_VMREAD_GPR64_GPR64 
XED_IFORM_VMREAD_MEMd_GPR32 
XED_IFORM_VMREAD_MEMq_GPR64 
XED_IFORM_VMRESUME 
XED_IFORM_VMRUN_ArAX 
XED_IFORM_VMSAVE 
XED_IFORM_VMULBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 
XED_IFORM_VMULBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 
XED_IFORM_VMULBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 
XED_IFORM_VMULBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 
XED_IFORM_VMULBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 
XED_IFORM_VMULBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 
XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VMULPS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VMULPS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VMULSD_XMMdq_XMMdq_MEMq 
XED_IFORM_VMULSD_XMMdq_XMMdq_XMMq 
XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd 
XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd 
XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VMWRITE_GPR32_GPR32 
XED_IFORM_VMWRITE_GPR32_MEMd 
XED_IFORM_VMWRITE_GPR64_GPR64 
XED_IFORM_VMWRITE_GPR64_MEMq 
XED_IFORM_VMXOFF 
XED_IFORM_VMXON_MEMq 
XED_IFORM_VORPD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VORPD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VORPD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VORPD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VORPS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VORPS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VORPS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VORPS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 
XED_IFORM_VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 
XED_IFORM_VPABSB_XMMdq_MEMdq 
XED_IFORM_VPABSB_XMMdq_XMMdq 
XED_IFORM_VPABSB_XMMi8_MASKmskw_MEMi8_AVX512 
XED_IFORM_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512 
XED_IFORM_VPABSB_YMMi8_MASKmskw_MEMi8_AVX512 
XED_IFORM_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512 
XED_IFORM_VPABSB_YMMqq_MEMqq 
XED_IFORM_VPABSB_YMMqq_YMMqq 
XED_IFORM_VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512 
XED_IFORM_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512 
XED_IFORM_VPABSD_XMMdq_MEMdq 
XED_IFORM_VPABSD_XMMdq_XMMdq 
XED_IFORM_VPABSD_XMMi32_MASKmskw_MEMi32_AVX512 
XED_IFORM_VPABSD_XMMi32_MASKmskw_XMMi32_AVX512 
XED_IFORM_VPABSD_YMMi32_MASKmskw_MEMi32_AVX512 
XED_IFORM_VPABSD_YMMi32_MASKmskw_YMMi32_AVX512 
XED_IFORM_VPABSD_YMMqq_MEMqq 
XED_IFORM_VPABSD_YMMqq_YMMqq 
XED_IFORM_VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512 
XED_IFORM_VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512 
XED_IFORM_VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512 
XED_IFORM_VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512 
XED_IFORM_VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512 
XED_IFORM_VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512 
XED_IFORM_VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512 
XED_IFORM_VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512 
XED_IFORM_VPABSW_XMMdq_MEMdq 
XED_IFORM_VPABSW_XMMdq_XMMdq 
XED_IFORM_VPABSW_XMMi16_MASKmskw_MEMi16_AVX512 
XED_IFORM_VPABSW_XMMi16_MASKmskw_XMMi16_AVX512 
XED_IFORM_VPABSW_YMMi16_MASKmskw_MEMi16_AVX512 
XED_IFORM_VPABSW_YMMi16_MASKmskw_YMMi16_AVX512 
XED_IFORM_VPABSW_YMMqq_MEMqq 
XED_IFORM_VPABSW_YMMqq_YMMqq 
XED_IFORM_VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512 
XED_IFORM_VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512 
XED_IFORM_VPACKSSDW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPACKSSDW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512 
XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512 
XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512 
XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512 
XED_IFORM_VPACKSSDW_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPACKSSDW_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512 
XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512 
XED_IFORM_VPACKSSWB_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPACKSSWB_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512 
XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512 
XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512 
XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512 
XED_IFORM_VPACKSSWB_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPACKSSWB_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512 
XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512 
XED_IFORM_VPACKUSDW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPACKUSDW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VPACKUSDW_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPACKUSDW_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VPACKUSWB_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPACKUSWB_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPACKUSWB_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPACKUSWB_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512 
XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512 
XED_IFORM_VPADDB_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPADDB_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 
XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 
XED_IFORM_VPADDB_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPADDB_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 
XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 
XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 
XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 
XED_IFORM_VPADDD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPADDD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VPADDD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPADDD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VPADDQ_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPADDQ_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPADDQ_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPADDQ_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VPADDSB_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPADDSB_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 
XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 
XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 
XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 
XED_IFORM_VPADDSB_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPADDSB_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 
XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 
XED_IFORM_VPADDSW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPADDSW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 
XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 
XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 
XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 
XED_IFORM_VPADDSW_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPADDSW_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 
XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 
XED_IFORM_VPADDUSB_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPADDUSB_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 
XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 
XED_IFORM_VPADDUSB_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPADDUSB_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 
XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 
XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 
XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 
XED_IFORM_VPADDUSW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPADDUSW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPADDUSW_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPADDUSW_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 
XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 
XED_IFORM_VPADDW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPADDW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPADDW_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPADDW_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 
XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 
XED_IFORM_VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb 
XED_IFORM_VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb 
XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 
XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 
XED_IFORM_VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb 
XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb 
XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 
XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 
XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 
XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 
XED_IFORM_VPAND_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPAND_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPAND_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPAND_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VPANDN_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPANDN_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPANDN_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPANDN_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VPAVGB_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPAVGB_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 
XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 
XED_IFORM_VPAVGB_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPAVGB_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 
XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 
XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 
XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 
XED_IFORM_VPAVGW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPAVGW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPAVGW_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPAVGW_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 
XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 
XED_IFORM_VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb 
XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb 
XED_IFORM_VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb 
XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb 
XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 
XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 
XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 
XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 
XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 
XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 
XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 
XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 
XED_IFORM_VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq 
XED_IFORM_VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb 
XED_IFORM_VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb 
XED_IFORM_VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb 
XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb 
XED_IFORM_VPBROADCASTB_XMMdq_MEMb 
XED_IFORM_VPBROADCASTB_XMMdq_XMMb 
XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512 
XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512 
XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512 
XED_IFORM_VPBROADCASTB_YMMqq_MEMb 
XED_IFORM_VPBROADCASTB_YMMqq_XMMb 
XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512 
XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512 
XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512 
XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512 
XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512 
XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512 
XED_IFORM_VPBROADCASTD_XMMdq_MEMd 
XED_IFORM_VPBROADCASTD_XMMdq_XMMd 
XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512 
XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512 
XED_IFORM_VPBROADCASTD_YMMqq_MEMd 
XED_IFORM_VPBROADCASTD_YMMqq_XMMd 
XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512 
XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512 
XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512 
XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512 
XED_IFORM_VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512 
XED_IFORM_VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512 
XED_IFORM_VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD 
XED_IFORM_VPBROADCASTMW2D_XMMu32_MASKu32_AVX512 
XED_IFORM_VPBROADCASTMW2D_YMMu32_MASKu32_AVX512 
XED_IFORM_VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD 
XED_IFORM_VPBROADCASTQ_XMMdq_MEMq 
XED_IFORM_VPBROADCASTQ_XMMdq_XMMq 
XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512 
XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512 
XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512 
XED_IFORM_VPBROADCASTQ_YMMqq_MEMq 
XED_IFORM_VPBROADCASTQ_YMMqq_XMMq 
XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512 
XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512 
XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512 
XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512 
XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512 
XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512 
XED_IFORM_VPBROADCASTW_XMMdq_MEMw 
XED_IFORM_VPBROADCASTW_XMMdq_XMMw 
XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512 
XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512 
XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512 
XED_IFORM_VPBROADCASTW_YMMqq_MEMw 
XED_IFORM_VPBROADCASTW_YMMqq_XMMw 
XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512 
XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512 
XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512 
XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512 
XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512 
XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512 
XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb 
XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb 
XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512 
XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512 
XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8 
XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512 
XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8 
XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512 
XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512 
XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512 
XED_IFORM_VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq 
XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512 
XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512 
XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512 
XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512 
XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512 
XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512 
XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512 
XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512 
XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512 
XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512 
XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512 
XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512 
XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 
XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 
XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 
XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 
XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 
XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 
XED_IFORM_VPCMPEQB_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPCMPEQB_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPCMPEQB_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPCMPEQB_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VPCMPEQD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPCMPEQD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPCMPEQD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPCMPEQD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 
XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 
XED_IFORM_VPCMPEQW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPCMPEQW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPCMPEQW_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPCMPEQW_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb 
XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb 
XED_IFORM_VPCMPESTRI64_XMMdq_MEMdq_IMMb 
XED_IFORM_VPCMPESTRI64_XMMdq_XMMdq_IMMb 
XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb 
XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb 
XED_IFORM_VPCMPESTRM64_XMMdq_MEMdq_IMMb 
XED_IFORM_VPCMPESTRM64_XMMdq_XMMdq_IMMb 
XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 
XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 
XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 
XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 
XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 
XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 
XED_IFORM_VPCMPGTB_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPCMPGTB_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPCMPGTB_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPCMPGTB_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512 
XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512 
XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512 
XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512 
XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512 
XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512 
XED_IFORM_VPCMPGTD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPCMPGTD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPCMPGTD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPCMPGTD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512 
XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512 
XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512 
XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512 
XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512 
XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512 
XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 
XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 
XED_IFORM_VPCMPGTW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPCMPGTW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPCMPGTW_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPCMPGTW_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb 
XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb 
XED_IFORM_VPCMPISTRI64_XMMdq_MEMdq_IMMb 
XED_IFORM_VPCMPISTRI64_XMMdq_XMMdq_IMMb 
XED_IFORM_VPCMPISTRM_XMMdq_MEMdq_IMMb 
XED_IFORM_VPCMPISTRM_XMMdq_XMMdq_IMMb 
XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512 
XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512 
XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512 
XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512 
XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512 
XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512 
XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 
XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 
XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 
XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 
XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 
XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 
XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 
XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 
XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 
XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 
XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 
XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 
XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 
XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 
XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 
XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 
XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 
XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 
XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 
XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 
XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 
XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 
XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 
XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 
XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512 
XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512 
XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512 
XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512 
XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512 
XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512 
XED_IFORM_VPCOMB_XMMdq_XMMdq_MEMdq_IMMb 
XED_IFORM_VPCOMB_XMMdq_XMMdq_XMMdq_IMMb 
XED_IFORM_VPCOMD_XMMdq_XMMdq_MEMdq_IMMb 
XED_IFORM_VPCOMD_XMMdq_XMMdq_XMMdq_IMMb 
XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512 
XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512 
XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512 
XED_IFORM_VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512 
XED_IFORM_VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512 
XED_IFORM_VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512 
XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512 
XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512 
XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512 
XED_IFORM_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512 
XED_IFORM_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512 
XED_IFORM_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512 
XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512 
XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512 
XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512 
XED_IFORM_VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512 
XED_IFORM_VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512 
XED_IFORM_VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512 
XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512 
XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512 
XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512 
XED_IFORM_VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512 
XED_IFORM_VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512 
XED_IFORM_VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512 
XED_IFORM_VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb 
XED_IFORM_VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb 
XED_IFORM_VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb 
XED_IFORM_VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb 
XED_IFORM_VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb 
XED_IFORM_VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb 
XED_IFORM_VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb 
XED_IFORM_VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb 
XED_IFORM_VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb 
XED_IFORM_VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb 
XED_IFORM_VPCOMW_XMMdq_XMMdq_MEMdq_IMMb 
XED_IFORM_VPCOMW_XMMdq_XMMdq_XMMdq_IMMb 
XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512 
XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512 
XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD 
XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD 
XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512 
XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512 
XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512 
XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512 
XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD 
XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD 
XED_IFORM_VPDPBSSD_XMMi32_MASKmskw_XMM4i8_MEM4i8_AVX512 
XED_IFORM_VPDPBSSD_XMMi32_MASKmskw_XMM4i8_XMM4i8_AVX512 
XED_IFORM_VPDPBSSD_XMMi32_XMM4i8_MEM4i8 
XED_IFORM_VPDPBSSD_XMMi32_XMM4i8_XMM4i8 
XED_IFORM_VPDPBSSD_YMMi32_MASKmskw_YMM4i8_MEM4i8_AVX512 
XED_IFORM_VPDPBSSD_YMMi32_MASKmskw_YMM4i8_YMM4i8_AVX512 
XED_IFORM_VPDPBSSD_YMMi32_YMM4i8_MEM4i8 
XED_IFORM_VPDPBSSD_YMMi32_YMM4i8_YMM4i8 
XED_IFORM_VPDPBSSD_ZMMi32_MASKmskw_ZMM4i8_MEM4i8_AVX512 
XED_IFORM_VPDPBSSD_ZMMi32_MASKmskw_ZMM4i8_ZMM4i8_AVX512 
XED_IFORM_VPDPBSSDS_XMMi32_MASKmskw_XMM4i8_MEM4i8_AVX512 
XED_IFORM_VPDPBSSDS_XMMi32_MASKmskw_XMM4i8_XMM4i8_AVX512 
XED_IFORM_VPDPBSSDS_XMMi32_XMM4i8_MEM4i8 
XED_IFORM_VPDPBSSDS_XMMi32_XMM4i8_XMM4i8 
XED_IFORM_VPDPBSSDS_YMMi32_MASKmskw_YMM4i8_MEM4i8_AVX512 
XED_IFORM_VPDPBSSDS_YMMi32_MASKmskw_YMM4i8_YMM4i8_AVX512 
XED_IFORM_VPDPBSSDS_YMMi32_YMM4i8_MEM4i8 
XED_IFORM_VPDPBSSDS_YMMi32_YMM4i8_YMM4i8 
XED_IFORM_VPDPBSSDS_ZMMi32_MASKmskw_ZMM4i8_MEM4i8_AVX512 
XED_IFORM_VPDPBSSDS_ZMMi32_MASKmskw_ZMM4i8_ZMM4i8_AVX512 
XED_IFORM_VPDPBSUD_XMMi32_MASKmskw_XMM4i8_MEM4u8_AVX512 
XED_IFORM_VPDPBSUD_XMMi32_MASKmskw_XMM4i8_XMM4u8_AVX512 
XED_IFORM_VPDPBSUD_XMMi32_XMM4i8_MEM4u8 
XED_IFORM_VPDPBSUD_XMMi32_XMM4i8_XMM4u8 
XED_IFORM_VPDPBSUD_YMMi32_MASKmskw_YMM4i8_MEM4u8_AVX512 
XED_IFORM_VPDPBSUD_YMMi32_MASKmskw_YMM4i8_YMM4u8_AVX512 
XED_IFORM_VPDPBSUD_YMMi32_YMM4i8_MEM4u8 
XED_IFORM_VPDPBSUD_YMMi32_YMM4i8_YMM4u8 
XED_IFORM_VPDPBSUD_ZMMi32_MASKmskw_ZMM4i8_MEM4u8_AVX512 
XED_IFORM_VPDPBSUD_ZMMi32_MASKmskw_ZMM4i8_ZMM4u8_AVX512 
XED_IFORM_VPDPBSUDS_XMMi32_MASKmskw_XMM4i8_MEM4u8_AVX512 
XED_IFORM_VPDPBSUDS_XMMi32_MASKmskw_XMM4i8_XMM4u8_AVX512 
XED_IFORM_VPDPBSUDS_XMMi32_XMM4i8_MEM4u8 
XED_IFORM_VPDPBSUDS_XMMi32_XMM4i8_XMM4u8 
XED_IFORM_VPDPBSUDS_YMMi32_MASKmskw_YMM4i8_MEM4u8_AVX512 
XED_IFORM_VPDPBSUDS_YMMi32_MASKmskw_YMM4i8_YMM4u8_AVX512 
XED_IFORM_VPDPBSUDS_YMMi32_YMM4i8_MEM4u8 
XED_IFORM_VPDPBSUDS_YMMi32_YMM4i8_YMM4u8 
XED_IFORM_VPDPBSUDS_ZMMi32_MASKmskw_ZMM4i8_MEM4u8_AVX512 
XED_IFORM_VPDPBSUDS_ZMMi32_MASKmskw_ZMM4i8_ZMM4u8_AVX512 
XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 
XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 
XED_IFORM_VPDPBUSD_XMMi32_XMMu32_MEMu32 
XED_IFORM_VPDPBUSD_XMMi32_XMMu32_XMMu32 
XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 
XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 
XED_IFORM_VPDPBUSD_YMMi32_YMMu32_MEMu32 
XED_IFORM_VPDPBUSD_YMMi32_YMMu32_YMMu32 
XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 
XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 
XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 
XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 
XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_MEMu32 
XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_XMMu32 
XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 
XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 
XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_MEMu32 
XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_YMMu32 
XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 
XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 
XED_IFORM_VPDPBUUD_XMMu32_MASKmskw_XMM4u8_MEM4u8_AVX512 
XED_IFORM_VPDPBUUD_XMMu32_MASKmskw_XMM4u8_XMM4u8_AVX512 
XED_IFORM_VPDPBUUD_XMMu32_XMM4u8_MEM4u8 
XED_IFORM_VPDPBUUD_XMMu32_XMM4u8_XMM4u8 
XED_IFORM_VPDPBUUD_YMMu32_MASKmskw_YMM4u8_MEM4u8_AVX512 
XED_IFORM_VPDPBUUD_YMMu32_MASKmskw_YMM4u8_YMM4u8_AVX512 
XED_IFORM_VPDPBUUD_YMMu32_YMM4u8_MEM4u8 
XED_IFORM_VPDPBUUD_YMMu32_YMM4u8_YMM4u8 
XED_IFORM_VPDPBUUD_ZMMu32_MASKmskw_ZMM4u8_MEM4u8_AVX512 
XED_IFORM_VPDPBUUD_ZMMu32_MASKmskw_ZMM4u8_ZMM4u8_AVX512 
XED_IFORM_VPDPBUUDS_XMMu32_MASKmskw_XMM4u8_MEM4u8_AVX512 
XED_IFORM_VPDPBUUDS_XMMu32_MASKmskw_XMM4u8_XMM4u8_AVX512 
XED_IFORM_VPDPBUUDS_XMMu32_XMM4u8_MEM4u8 
XED_IFORM_VPDPBUUDS_XMMu32_XMM4u8_XMM4u8 
XED_IFORM_VPDPBUUDS_YMMu32_MASKmskw_YMM4u8_MEM4u8_AVX512 
XED_IFORM_VPDPBUUDS_YMMu32_MASKmskw_YMM4u8_YMM4u8_AVX512 
XED_IFORM_VPDPBUUDS_YMMu32_YMM4u8_MEM4u8 
XED_IFORM_VPDPBUUDS_YMMu32_YMM4u8_YMM4u8 
XED_IFORM_VPDPBUUDS_ZMMu32_MASKmskw_ZMM4u8_MEM4u8_AVX512 
XED_IFORM_VPDPBUUDS_ZMMu32_MASKmskw_ZMM4u8_ZMM4u8_AVX512 
XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 
XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 
XED_IFORM_VPDPWSSD_XMMi32_XMMu32_MEMu32 
XED_IFORM_VPDPWSSD_XMMi32_XMMu32_XMMu32 
XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 
XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 
XED_IFORM_VPDPWSSD_YMMi32_YMMu32_MEMu32 
XED_IFORM_VPDPWSSD_YMMi32_YMMu32_YMMu32 
XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 
XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 
XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 
XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 
XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_MEMu32 
XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_XMMu32 
XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 
XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 
XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_MEMu32 
XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_YMMu32 
XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 
XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 
XED_IFORM_VPDPWSUD_XMMi32_MASKmskw_XMM2i16_MEM2u16_AVX512 
XED_IFORM_VPDPWSUD_XMMi32_MASKmskw_XMM2i16_XMM2u16_AVX512 
XED_IFORM_VPDPWSUD_XMMi32_XMM2i16_MEM2u16 
XED_IFORM_VPDPWSUD_XMMi32_XMM2i16_XMM2u16 
XED_IFORM_VPDPWSUD_YMMi32_MASKmskw_YMM2i16_MEM2u16_AVX512 
XED_IFORM_VPDPWSUD_YMMi32_MASKmskw_YMM2i16_YMM2u16_AVX512 
XED_IFORM_VPDPWSUD_YMMi32_YMM2i16_MEM2u16 
XED_IFORM_VPDPWSUD_YMMi32_YMM2i16_YMM2u16 
XED_IFORM_VPDPWSUD_ZMMi32_MASKmskw_ZMM2i16_MEM2u16_AVX512 
XED_IFORM_VPDPWSUD_ZMMi32_MASKmskw_ZMM2i16_ZMM2u16_AVX512 
XED_IFORM_VPDPWSUDS_XMMi32_MASKmskw_XMM2i16_MEM2u16_AVX512 
XED_IFORM_VPDPWSUDS_XMMi32_MASKmskw_XMM2i16_XMM2u16_AVX512 
XED_IFORM_VPDPWSUDS_XMMi32_XMM2i16_MEM2u16 
XED_IFORM_VPDPWSUDS_XMMi32_XMM2i16_XMM2u16 
XED_IFORM_VPDPWSUDS_YMMi32_MASKmskw_YMM2i16_MEM2u16_AVX512 
XED_IFORM_VPDPWSUDS_YMMi32_MASKmskw_YMM2i16_YMM2u16_AVX512 
XED_IFORM_VPDPWSUDS_YMMi32_YMM2i16_MEM2u16 
XED_IFORM_VPDPWSUDS_YMMi32_YMM2i16_YMM2u16 
XED_IFORM_VPDPWSUDS_ZMMi32_MASKmskw_ZMM2i16_MEM2u16_AVX512 
XED_IFORM_VPDPWSUDS_ZMMi32_MASKmskw_ZMM2i16_ZMM2u16_AVX512 
XED_IFORM_VPDPWUSD_XMMi32_MASKmskw_XMM2u16_MEM2i16_AVX512 
XED_IFORM_VPDPWUSD_XMMi32_MASKmskw_XMM2u16_XMM2i16_AVX512 
XED_IFORM_VPDPWUSD_XMMi32_XMM2u16_MEM2i16 
XED_IFORM_VPDPWUSD_XMMi32_XMM2u16_XMM2i16 
XED_IFORM_VPDPWUSD_YMMi32_MASKmskw_YMM2u16_MEM2i16_AVX512 
XED_IFORM_VPDPWUSD_YMMi32_MASKmskw_YMM2u16_YMM2i16_AVX512 
XED_IFORM_VPDPWUSD_YMMi32_YMM2u16_MEM2i16 
XED_IFORM_VPDPWUSD_YMMi32_YMM2u16_YMM2i16 
XED_IFORM_VPDPWUSD_ZMMi32_MASKmskw_ZMM2u16_MEM2i16_AVX512 
XED_IFORM_VPDPWUSD_ZMMi32_MASKmskw_ZMM2u16_ZMM2i16_AVX512 
XED_IFORM_VPDPWUSDS_XMMi32_MASKmskw_XMM2u16_MEM2i16_AVX512 
XED_IFORM_VPDPWUSDS_XMMi32_MASKmskw_XMM2u16_XMM2i16_AVX512 
XED_IFORM_VPDPWUSDS_XMMi32_XMM2u16_MEM2i16 
XED_IFORM_VPDPWUSDS_XMMi32_XMM2u16_XMM2i16 
XED_IFORM_VPDPWUSDS_YMMi32_MASKmskw_YMM2u16_MEM2i16_AVX512 
XED_IFORM_VPDPWUSDS_YMMi32_MASKmskw_YMM2u16_YMM2i16_AVX512 
XED_IFORM_VPDPWUSDS_YMMi32_YMM2u16_MEM2i16 
XED_IFORM_VPDPWUSDS_YMMi32_YMM2u16_YMM2i16 
XED_IFORM_VPDPWUSDS_ZMMi32_MASKmskw_ZMM2u16_MEM2i16_AVX512 
XED_IFORM_VPDPWUSDS_ZMMi32_MASKmskw_ZMM2u16_ZMM2i16_AVX512 
XED_IFORM_VPDPWUUD_XMMu32_MASKmskw_XMM2u16_MEM2u16_AVX512 
XED_IFORM_VPDPWUUD_XMMu32_MASKmskw_XMM2u16_XMM2u16_AVX512 
XED_IFORM_VPDPWUUD_XMMu32_XMM2u16_MEM2u16 
XED_IFORM_VPDPWUUD_XMMu32_XMM2u16_XMM2u16 
XED_IFORM_VPDPWUUD_YMMu32_MASKmskw_YMM2u16_MEM2u16_AVX512 
XED_IFORM_VPDPWUUD_YMMu32_MASKmskw_YMM2u16_YMM2u16_AVX512 
XED_IFORM_VPDPWUUD_YMMu32_YMM2u16_MEM2u16 
XED_IFORM_VPDPWUUD_YMMu32_YMM2u16_YMM2u16 
XED_IFORM_VPDPWUUD_ZMMu32_MASKmskw_ZMM2u16_MEM2u16_AVX512 
XED_IFORM_VPDPWUUD_ZMMu32_MASKmskw_ZMM2u16_ZMM2u16_AVX512 
XED_IFORM_VPDPWUUDS_XMMu32_MASKmskw_XMM2u16_MEM2u16_AVX512 
XED_IFORM_VPDPWUUDS_XMMu32_MASKmskw_XMM2u16_XMM2u16_AVX512 
XED_IFORM_VPDPWUUDS_XMMu32_XMM2u16_MEM2u16 
XED_IFORM_VPDPWUUDS_XMMu32_XMM2u16_XMM2u16 
XED_IFORM_VPDPWUUDS_YMMu32_MASKmskw_YMM2u16_MEM2u16_AVX512 
XED_IFORM_VPDPWUUDS_YMMu32_MASKmskw_YMM2u16_YMM2u16_AVX512 
XED_IFORM_VPDPWUUDS_YMMu32_YMM2u16_MEM2u16 
XED_IFORM_VPDPWUUDS_YMMu32_YMM2u16_YMM2u16 
XED_IFORM_VPDPWUUDS_ZMMu32_MASKmskw_ZMM2u16_MEM2u16_AVX512 
XED_IFORM_VPDPWUUDS_ZMMu32_MASKmskw_ZMM2u16_ZMM2u16_AVX512 
XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb 
XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb 
XED_IFORM_VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb 
XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb 
XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 
XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 
XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 
XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 
XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 
XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 
XED_IFORM_VPERMD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPERMD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 
XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 
XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 
XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 
XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 
XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 
XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 
XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 
XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb 
XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb 
XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb 
XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb 
XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb 
XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb 
XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb 
XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb 
XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb 
XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb 
XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb 
XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb 
XED_IFORM_VPERMILPD_XMMdq_MEMdq_IMMb 
XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb 
XED_IFORM_VPERMILPD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPERMILPD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 
XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 
XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 
XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 
XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VPERMILPD_YMMqq_MEMqq_IMMb 
XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb 
XED_IFORM_VPERMILPD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPERMILPD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 
XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 
XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VPERMILPS_XMMdq_MEMdq_IMMb 
XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb 
XED_IFORM_VPERMILPS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPERMILPS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 
XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 
XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 
XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 
XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VPERMILPS_YMMqq_MEMqq_IMMb 
XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb 
XED_IFORM_VPERMILPS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPERMILPS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 
XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 
XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 
XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 
XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VPERMPD_YMMqq_MEMqq_IMMb 
XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb 
XED_IFORM_VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 
XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 
XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VPERMPS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPERMPS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VPERMQ_YMMqq_MEMqq_IMMb 
XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb 
XED_IFORM_VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 
XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 
XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 
XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 
XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 
XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 
XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 
XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 
XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 
XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 
XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 
XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 
XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 
XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 
XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512 
XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512 
XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512 
XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512 
XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512 
XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512 
XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512 
XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512 
XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512 
XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512 
XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512 
XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512 
XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512 
XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512 
XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512 
XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512 
XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512 
XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512 
XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512 
XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512 
XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512 
XED_IFORM_VPEXTRB_GPR32d_XMMdq_IMMb 
XED_IFORM_VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512 
XED_IFORM_VPEXTRB_MEMb_XMMdq_IMMb 
XED_IFORM_VPEXTRB_MEMu8_XMMu8_IMM8_AVX512 
XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb 
XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512 
XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb 
XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 
XED_IFORM_VPEXTRQ_GPR64q_XMMdq_IMMb 
XED_IFORM_VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512 
XED_IFORM_VPEXTRQ_MEMq_XMMdq_IMMb 
XED_IFORM_VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512 
XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_15 
XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_C5 
XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512 
XED_IFORM_VPEXTRW_MEMu16_XMMu16_IMM8_AVX512 
XED_IFORM_VPEXTRW_MEMw_XMMdq_IMMb 
XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5 
XED_IFORM_VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 
XED_IFORM_VPGATHERDD_XMMu32_MEMd_XMMi32_VL128 
XED_IFORM_VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256 
XED_IFORM_VPGATHERDD_YMMu32_MEMd_YMMi32_VL256 
XED_IFORM_VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512 
XED_IFORM_VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 
XED_IFORM_VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128 
XED_IFORM_VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 
XED_IFORM_VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256 
XED_IFORM_VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 
XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 
XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256 
XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL128 
XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL256 
XED_IFORM_VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512 
XED_IFORM_VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 
XED_IFORM_VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128 
XED_IFORM_VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 
XED_IFORM_VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256 
XED_IFORM_VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 
XED_IFORM_VPHADDBD_XMMdq_MEMdq 
XED_IFORM_VPHADDBD_XMMdq_XMMdq 
XED_IFORM_VPHADDBQ_XMMdq_MEMdq 
XED_IFORM_VPHADDBQ_XMMdq_XMMdq 
XED_IFORM_VPHADDBW_XMMdq_MEMdq 
XED_IFORM_VPHADDBW_XMMdq_XMMdq 
XED_IFORM_VPHADDD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPHADDD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPHADDD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPHADDD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPHADDDQ_XMMdq_MEMdq 
XED_IFORM_VPHADDDQ_XMMdq_XMMdq 
XED_IFORM_VPHADDSW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPHADDSW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPHADDSW_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPHADDSW_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPHADDUBD_XMMdq_MEMdq 
XED_IFORM_VPHADDUBD_XMMdq_XMMdq 
XED_IFORM_VPHADDUBQ_XMMdq_MEMdq 
XED_IFORM_VPHADDUBQ_XMMdq_XMMdq 
XED_IFORM_VPHADDUBW_XMMdq_MEMdq 
XED_IFORM_VPHADDUBW_XMMdq_XMMdq 
XED_IFORM_VPHADDUDQ_XMMdq_MEMdq 
XED_IFORM_VPHADDUDQ_XMMdq_XMMdq 
XED_IFORM_VPHADDUWD_XMMdq_MEMdq 
XED_IFORM_VPHADDUWD_XMMdq_XMMdq 
XED_IFORM_VPHADDUWQ_XMMdq_MEMdq 
XED_IFORM_VPHADDUWQ_XMMdq_XMMdq 
XED_IFORM_VPHADDW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPHADDW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPHADDW_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPHADDW_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPHADDWD_XMMdq_MEMdq 
XED_IFORM_VPHADDWD_XMMdq_XMMdq 
XED_IFORM_VPHADDWQ_XMMdq_MEMdq 
XED_IFORM_VPHADDWQ_XMMdq_XMMdq 
XED_IFORM_VPHMINPOSUW_XMMdq_MEMdq 
XED_IFORM_VPHMINPOSUW_XMMdq_XMMdq 
XED_IFORM_VPHSUBBW_XMMdq_MEMdq 
XED_IFORM_VPHSUBBW_XMMdq_XMMdq 
XED_IFORM_VPHSUBD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPHSUBD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPHSUBD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPHSUBD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPHSUBDQ_XMMdq_MEMdq 
XED_IFORM_VPHSUBDQ_XMMdq_XMMdq 
XED_IFORM_VPHSUBSW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPHSUBSW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPHSUBSW_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPHSUBSW_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPHSUBW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPHSUBW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPHSUBW_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPHSUBW_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPHSUBWD_XMMdq_MEMdq 
XED_IFORM_VPHSUBWD_XMMdq_XMMdq 
XED_IFORM_VPINSRB_XMMdq_XMMdq_GPR32d_IMMb 
XED_IFORM_VPINSRB_XMMdq_XMMdq_MEMb_IMMb 
XED_IFORM_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512 
XED_IFORM_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512 
XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb 
XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb 
XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512 
XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 
XED_IFORM_VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb 
XED_IFORM_VPINSRQ_XMMdq_XMMdq_MEMq_IMMb 
XED_IFORM_VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512 
XED_IFORM_VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512 
XED_IFORM_VPINSRW_XMMdq_XMMdq_GPR32d_IMMb 
XED_IFORM_VPINSRW_XMMdq_XMMdq_MEMw_IMMb 
XED_IFORM_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512 
XED_IFORM_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512 
XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512 
XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512 
XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD 
XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD 
XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 
XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 
XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 
XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 
XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD 
XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD 
XED_IFORM_VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPMADD52HUQ_XMMu64_XMMu64_MEMu64 
XED_IFORM_VPMADD52HUQ_XMMu64_XMMu64_XMMu64 
XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VPMADD52HUQ_YMMu64_YMMu64_MEMu64 
XED_IFORM_VPMADD52HUQ_YMMu64_YMMu64_YMMu64 
XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPMADD52LUQ_XMMu64_XMMu64_MEMu64 
XED_IFORM_VPMADD52LUQ_XMMu64_XMMu64_XMMu64 
XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VPMADD52LUQ_YMMu64_YMMu64_MEMu64 
XED_IFORM_VPMADD52LUQ_YMMu64_YMMu64_YMMu64 
XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 
XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 
XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 
XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 
XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 
XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 
XED_IFORM_VPMADDWD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPMADDWD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512 
XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512 
XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512 
XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512 
XED_IFORM_VPMADDWD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPMADDWD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512 
XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512 
XED_IFORM_VPMASKMOVD_MEMdq_XMMdq_XMMdq 
XED_IFORM_VPMASKMOVD_MEMqq_YMMqq_YMMqq 
XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPMASKMOVD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPMASKMOVQ_MEMdq_XMMdq_XMMdq 
XED_IFORM_VPMASKMOVQ_MEMqq_YMMqq_YMMqq 
XED_IFORM_VPMASKMOVQ_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPMASKMOVQ_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPMAXSB_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPMAXSB_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 
XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 
XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 
XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 
XED_IFORM_VPMAXSB_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPMAXSB_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 
XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 
XED_IFORM_VPMAXSD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPMAXSD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 
XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 
XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 
XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 
XED_IFORM_VPMAXSD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPMAXSD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 
XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 
XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 
XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 
XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 
XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 
XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 
XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 
XED_IFORM_VPMAXSW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPMAXSW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 
XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 
XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 
XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 
XED_IFORM_VPMAXSW_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPMAXSW_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 
XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 
XED_IFORM_VPMAXUB_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPMAXUB_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 
XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 
XED_IFORM_VPMAXUB_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPMAXUB_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 
XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 
XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 
XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 
XED_IFORM_VPMAXUD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPMAXUD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VPMAXUD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPMAXUD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VPMAXUW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPMAXUW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPMAXUW_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPMAXUW_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 
XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 
XED_IFORM_VPMINSB_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPMINSB_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 
XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 
XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 
XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 
XED_IFORM_VPMINSB_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPMINSB_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 
XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 
XED_IFORM_VPMINSD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPMINSD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 
XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 
XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 
XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 
XED_IFORM_VPMINSD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPMINSD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 
XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 
XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 
XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 
XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 
XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 
XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 
XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 
XED_IFORM_VPMINSW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPMINSW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 
XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 
XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 
XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 
XED_IFORM_VPMINSW_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPMINSW_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 
XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 
XED_IFORM_VPMINUB_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPMINUB_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 
XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 
XED_IFORM_VPMINUB_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPMINUB_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 
XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 
XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 
XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 
XED_IFORM_VPMINUD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPMINUD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VPMINUD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPMINUD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VPMINUW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPMINUW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPMINUW_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPMINUW_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 
XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 
XED_IFORM_VPMOVB2M_MASKmskw_XMMu8_AVX512 
XED_IFORM_VPMOVB2M_MASKmskw_YMMu8_AVX512 
XED_IFORM_VPMOVB2M_MASKmskw_ZMMu8_AVX512 
XED_IFORM_VPMOVD2M_MASKmskw_XMMu32_AVX512 
XED_IFORM_VPMOVD2M_MASKmskw_YMMu32_AVX512 
XED_IFORM_VPMOVD2M_MASKmskw_ZMMu32_AVX512 
XED_IFORM_VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512 
XED_IFORM_VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512 
XED_IFORM_VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512 
XED_IFORM_VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512 
XED_IFORM_VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512 
XED_IFORM_VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512 
XED_IFORM_VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512 
XED_IFORM_VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512 
XED_IFORM_VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512 
XED_IFORM_VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512 
XED_IFORM_VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512 
XED_IFORM_VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512 
XED_IFORM_VPMOVM2B_XMMu8_MASKmskw_AVX512 
XED_IFORM_VPMOVM2B_YMMu8_MASKmskw_AVX512 
XED_IFORM_VPMOVM2B_ZMMu8_MASKmskw_AVX512 
XED_IFORM_VPMOVM2D_XMMu32_MASKmskw_AVX512 
XED_IFORM_VPMOVM2D_YMMu32_MASKmskw_AVX512 
XED_IFORM_VPMOVM2D_ZMMu32_MASKmskw_AVX512 
XED_IFORM_VPMOVM2Q_XMMu64_MASKmskw_AVX512 
XED_IFORM_VPMOVM2Q_YMMu64_MASKmskw_AVX512 
XED_IFORM_VPMOVM2Q_ZMMu64_MASKmskw_AVX512 
XED_IFORM_VPMOVM2W_XMMu16_MASKmskw_AVX512 
XED_IFORM_VPMOVM2W_YMMu16_MASKmskw_AVX512 
XED_IFORM_VPMOVM2W_ZMMu16_MASKmskw_AVX512 
XED_IFORM_VPMOVMSKB_GPR32d_XMMdq 
XED_IFORM_VPMOVMSKB_GPR32d_YMMqq 
XED_IFORM_VPMOVQ2M_MASKmskw_XMMu64_AVX512 
XED_IFORM_VPMOVQ2M_MASKmskw_YMMu64_AVX512 
XED_IFORM_VPMOVQ2M_MASKmskw_ZMMu64_AVX512 
XED_IFORM_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512 
XED_IFORM_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512 
XED_IFORM_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512 
XED_IFORM_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512 
XED_IFORM_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512 
XED_IFORM_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512 
XED_IFORM_VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512 
XED_IFORM_VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512 
XED_IFORM_VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512 
XED_IFORM_VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512 
XED_IFORM_VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512 
XED_IFORM_VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512 
XED_IFORM_VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512 
XED_IFORM_VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512 
XED_IFORM_VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512 
XED_IFORM_VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512 
XED_IFORM_VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512 
XED_IFORM_VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512 
XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512 
XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512 
XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512 
XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512 
XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512 
XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512 
XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512 
XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512 
XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512 
XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512 
XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512 
XED_IFORM_VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512 
XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512 
XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512 
XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512 
XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512 
XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512 
XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512 
XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512 
XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512 
XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512 
XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512 
XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512 
XED_IFORM_VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512 
XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512 
XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512 
XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512 
XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512 
XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512 
XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512 
XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512 
XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512 
XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512 
XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512 
XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512 
XED_IFORM_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512 
XED_IFORM_VPMOVSXBD_XMMdq_MEMd 
XED_IFORM_VPMOVSXBD_XMMdq_XMMd 
XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512 
XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512 
XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512 
XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512 
XED_IFORM_VPMOVSXBD_YMMqq_MEMq 
XED_IFORM_VPMOVSXBD_YMMqq_XMMq 
XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512 
XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512 
XED_IFORM_VPMOVSXBQ_XMMdq_MEMw 
XED_IFORM_VPMOVSXBQ_XMMdq_XMMw 
XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512 
XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512 
XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512 
XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512 
XED_IFORM_VPMOVSXBQ_YMMqq_MEMd 
XED_IFORM_VPMOVSXBQ_YMMqq_XMMd 
XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 
XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 
XED_IFORM_VPMOVSXBW_XMMdq_MEMq 
XED_IFORM_VPMOVSXBW_XMMdq_XMMq 
XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512 
XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512 
XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512 
XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512 
XED_IFORM_VPMOVSXBW_YMMqq_MEMdq 
XED_IFORM_VPMOVSXBW_YMMqq_XMMdq 
XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512 
XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512 
XED_IFORM_VPMOVSXDQ_XMMdq_MEMq 
XED_IFORM_VPMOVSXDQ_XMMdq_XMMq 
XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512 
XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512 
XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512 
XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512 
XED_IFORM_VPMOVSXDQ_YMMqq_MEMdq 
XED_IFORM_VPMOVSXDQ_YMMqq_XMMdq 
XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 
XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 
XED_IFORM_VPMOVSXWD_XMMdq_MEMq 
XED_IFORM_VPMOVSXWD_XMMdq_XMMq 
XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512 
XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512 
XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512 
XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512 
XED_IFORM_VPMOVSXWD_YMMqq_MEMdq 
XED_IFORM_VPMOVSXWD_YMMqq_XMMdq 
XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512 
XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512 
XED_IFORM_VPMOVSXWQ_XMMdq_MEMd 
XED_IFORM_VPMOVSXWQ_XMMdq_XMMd 
XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512 
XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512 
XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512 
XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512 
XED_IFORM_VPMOVSXWQ_YMMqq_MEMq 
XED_IFORM_VPMOVSXWQ_YMMqq_XMMq 
XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 
XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 
XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512 
XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512 
XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512 
XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512 
XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512 
XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512 
XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512 
XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512 
XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512 
XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512 
XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512 
XED_IFORM_VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512 
XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512 
XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512 
XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512 
XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512 
XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512 
XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512 
XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512 
XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512 
XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512 
XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512 
XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512 
XED_IFORM_VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512 
XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512 
XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512 
XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512 
XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512 
XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512 
XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512 
XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512 
XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512 
XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512 
XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512 
XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512 
XED_IFORM_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512 
XED_IFORM_VPMOVW2M_MASKmskw_XMMu16_AVX512 
XED_IFORM_VPMOVW2M_MASKmskw_YMMu16_AVX512 
XED_IFORM_VPMOVW2M_MASKmskw_ZMMu16_AVX512 
XED_IFORM_VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512 
XED_IFORM_VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512 
XED_IFORM_VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512 
XED_IFORM_VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512 
XED_IFORM_VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512 
XED_IFORM_VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512 
XED_IFORM_VPMOVZXBD_XMMdq_MEMd 
XED_IFORM_VPMOVZXBD_XMMdq_XMMd 
XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512 
XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512 
XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512 
XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512 
XED_IFORM_VPMOVZXBD_YMMqq_MEMq 
XED_IFORM_VPMOVZXBD_YMMqq_XMMq 
XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512 
XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512 
XED_IFORM_VPMOVZXBQ_XMMdq_MEMw 
XED_IFORM_VPMOVZXBQ_XMMdq_XMMw 
XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512 
XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512 
XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512 
XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512 
XED_IFORM_VPMOVZXBQ_YMMqq_MEMd 
XED_IFORM_VPMOVZXBQ_YMMqq_XMMd 
XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 
XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 
XED_IFORM_VPMOVZXBW_XMMdq_MEMq 
XED_IFORM_VPMOVZXBW_XMMdq_XMMq 
XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512 
XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512 
XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512 
XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512 
XED_IFORM_VPMOVZXBW_YMMqq_MEMdq 
XED_IFORM_VPMOVZXBW_YMMqq_XMMdq 
XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512 
XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512 
XED_IFORM_VPMOVZXDQ_XMMdq_MEMq 
XED_IFORM_VPMOVZXDQ_XMMdq_XMMq 
XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512 
XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512 
XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512 
XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512 
XED_IFORM_VPMOVZXDQ_YMMqq_MEMdq 
XED_IFORM_VPMOVZXDQ_YMMqq_XMMdq 
XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 
XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 
XED_IFORM_VPMOVZXWD_XMMdq_MEMq 
XED_IFORM_VPMOVZXWD_XMMdq_XMMq 
XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512 
XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512 
XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512 
XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512 
XED_IFORM_VPMOVZXWD_YMMqq_MEMdq 
XED_IFORM_VPMOVZXWD_YMMqq_XMMdq 
XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512 
XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512 
XED_IFORM_VPMOVZXWQ_XMMdq_MEMd 
XED_IFORM_VPMOVZXWQ_XMMdq_XMMd 
XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512 
XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512 
XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512 
XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512 
XED_IFORM_VPMOVZXWQ_YMMqq_MEMq 
XED_IFORM_VPMOVZXWQ_YMMqq_XMMq 
XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 
XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 
XED_IFORM_VPMULDQ_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPMULDQ_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 
XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 
XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 
XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 
XED_IFORM_VPMULDQ_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPMULDQ_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 
XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 
XED_IFORM_VPMULHRSW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPMULHRSW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 
XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 
XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 
XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 
XED_IFORM_VPMULHRSW_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPMULHRSW_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 
XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 
XED_IFORM_VPMULHUW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPMULHUW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPMULHUW_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPMULHUW_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 
XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 
XED_IFORM_VPMULHW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPMULHW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPMULHW_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPMULHW_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 
XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 
XED_IFORM_VPMULLD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPMULLD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VPMULLD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPMULLD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VPMULLW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPMULLW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPMULLW_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPMULLW_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 
XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 
XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512 
XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512 
XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512 
XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512 
XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512 
XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512 
XED_IFORM_VPMULUDQ_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPMULUDQ_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPMULUDQ_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPMULUDQ_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512 
XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512 
XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512 
XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512 
XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512 
XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512 
XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512 
XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512 
XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512 
XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512 
XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 
XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 
XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 
XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 
XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512 
XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512 
XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512 
XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512 
XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512 
XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512 
XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512 
XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512 
XED_IFORM_VPOR_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPOR_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPOR_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPOR_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VPPERM_XMMdq_XMMdq_MEMdq_XMMdq 
XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 
XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 
XED_IFORM_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 
XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 
XED_IFORM_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 
XED_IFORM_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 
XED_IFORM_VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 
XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 
XED_IFORM_VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 
XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 
XED_IFORM_VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 
XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 
XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 
XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 
XED_IFORM_VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 
XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 
XED_IFORM_VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 
XED_IFORM_VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 
XED_IFORM_VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 
XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 
XED_IFORM_VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 
XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 
XED_IFORM_VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 
XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 
XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VPROTB_XMMdq_MEMdq_IMMb 
XED_IFORM_VPROTB_XMMdq_MEMdq_XMMdq 
XED_IFORM_VPROTB_XMMdq_XMMdq_IMMb 
XED_IFORM_VPROTB_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPROTB_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPROTD_XMMdq_MEMdq_IMMb 
XED_IFORM_VPROTD_XMMdq_MEMdq_XMMdq 
XED_IFORM_VPROTD_XMMdq_XMMdq_IMMb 
XED_IFORM_VPROTD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPROTD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPROTQ_XMMdq_MEMdq_IMMb 
XED_IFORM_VPROTQ_XMMdq_MEMdq_XMMdq 
XED_IFORM_VPROTQ_XMMdq_XMMdq_IMMb 
XED_IFORM_VPROTQ_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPROTQ_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPROTW_XMMdq_MEMdq_IMMb 
XED_IFORM_VPROTW_XMMdq_MEMdq_XMMdq 
XED_IFORM_VPROTW_XMMdq_XMMdq_IMMb 
XED_IFORM_VPROTW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPROTW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSADBW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSADBW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSADBW_XMMu16_XMMu8_MEMu8_AVX512 
XED_IFORM_VPSADBW_XMMu16_XMMu8_XMMu8_AVX512 
XED_IFORM_VPSADBW_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPSADBW_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPSADBW_YMMu16_YMMu8_MEMu8_AVX512 
XED_IFORM_VPSADBW_YMMu16_YMMu8_YMMu8_AVX512 
XED_IFORM_VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512 
XED_IFORM_VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512 
XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 
XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256 
XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512 
XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 
XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 
XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 
XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 
XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256 
XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512 
XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 
XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 
XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 
XED_IFORM_VPSHAB_XMMdq_MEMdq_XMMdq 
XED_IFORM_VPSHAB_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSHAB_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSHAD_XMMdq_MEMdq_XMMdq 
XED_IFORM_VPSHAD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSHAD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSHAQ_XMMdq_MEMdq_XMMdq 
XED_IFORM_VPSHAQ_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSHAQ_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSHAW_XMMdq_MEMdq_XMMdq 
XED_IFORM_VPSHAW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSHAW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSHLB_XMMdq_MEMdq_XMMdq 
XED_IFORM_VPSHLB_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSHLB_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSHLD_XMMdq_MEMdq_XMMdq 
XED_IFORM_VPSHLD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSHLD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 
XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 
XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 
XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 
XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 
XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 
XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 
XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 
XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 
XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 
XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 
XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 
XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 
XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 
XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 
XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 
XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 
XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 
XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 
XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 
XED_IFORM_VPSHLQ_XMMdq_MEMdq_XMMdq 
XED_IFORM_VPSHLQ_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSHLQ_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSHLW_XMMdq_MEMdq_XMMdq 
XED_IFORM_VPSHLW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSHLW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 
XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 
XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 
XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 
XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 
XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 
XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 
XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 
XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 
XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 
XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 
XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 
XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 
XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 
XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 
XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 
XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 
XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 
XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 
XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 
XED_IFORM_VPSHUFB_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSHUFB_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 
XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 
XED_IFORM_VPSHUFB_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPSHUFB_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 
XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 
XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 
XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 
XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512 
XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512 
XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512 
XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512 
XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512 
XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512 
XED_IFORM_VPSHUFD_XMMdq_MEMdq_IMMb 
XED_IFORM_VPSHUFD_XMMdq_XMMdq_IMMb 
XED_IFORM_VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 
XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 
XED_IFORM_VPSHUFD_YMMqq_MEMqq_IMMb 
XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb 
XED_IFORM_VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 
XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 
XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 
XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 
XED_IFORM_VPSHUFHW_XMMdq_MEMdq_IMMb 
XED_IFORM_VPSHUFHW_XMMdq_XMMdq_IMMb 
XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 
XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 
XED_IFORM_VPSHUFHW_YMMqq_MEMqq_IMMb 
XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb 
XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 
XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 
XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 
XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 
XED_IFORM_VPSHUFLW_XMMdq_MEMdq_IMMb 
XED_IFORM_VPSHUFLW_XMMdq_XMMdq_IMMb 
XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 
XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 
XED_IFORM_VPSHUFLW_YMMqq_MEMqq_IMMb 
XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb 
XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 
XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 
XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 
XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 
XED_IFORM_VPSIGNB_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSIGNB_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSIGNB_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPSIGNB_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPSIGND_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSIGND_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSIGND_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPSIGND_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPSIGNW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSIGNW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSIGNW_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPSIGNW_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPSLLD_XMMdq_XMMdq_IMMb 
XED_IFORM_VPSLLD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSLLD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 
XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 
XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb 
XED_IFORM_VPSLLD_YMMqq_YMMqq_MEMdq 
XED_IFORM_VPSLLD_YMMqq_YMMqq_XMMq 
XED_IFORM_VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 
XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 
XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 
XED_IFORM_VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 
XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 
XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 
XED_IFORM_VPSLLDQ_XMMdq_XMMdq_IMMb 
XED_IFORM_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512 
XED_IFORM_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512 
XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb 
XED_IFORM_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512 
XED_IFORM_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512 
XED_IFORM_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512 
XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512 
XED_IFORM_VPSLLQ_XMMdq_XMMdq_IMMb 
XED_IFORM_VPSLLQ_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSLLQ_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 
XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 
XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb 
XED_IFORM_VPSLLQ_YMMqq_YMMqq_MEMdq 
XED_IFORM_VPSLLQ_YMMqq_YMMqq_XMMq 
XED_IFORM_VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 
XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 
XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 
XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 
XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 
XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 
XED_IFORM_VPSLLVD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSLLVD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VPSLLVD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPSLLVD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VPSLLVQ_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSLLVQ_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPSLLVQ_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPSLLVQ_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 
XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 
XED_IFORM_VPSLLW_XMMdq_XMMdq_IMMb 
XED_IFORM_VPSLLW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSLLW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 
XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 
XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb 
XED_IFORM_VPSLLW_YMMqq_YMMqq_MEMdq 
XED_IFORM_VPSLLW_YMMqq_YMMqq_XMMq 
XED_IFORM_VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 
XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 
XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 
XED_IFORM_VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 
XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 
XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 
XED_IFORM_VPSRAD_XMMdq_XMMdq_IMMb 
XED_IFORM_VPSRAD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSRAD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 
XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 
XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb 
XED_IFORM_VPSRAD_YMMqq_YMMqq_MEMdq 
XED_IFORM_VPSRAD_YMMqq_YMMqq_XMMq 
XED_IFORM_VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 
XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 
XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 
XED_IFORM_VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 
XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 
XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 
XED_IFORM_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 
XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 
XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 
XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 
XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 
XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 
XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 
XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 
XED_IFORM_VPSRAVD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSRAVD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VPSRAVD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPSRAVD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 
XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 
XED_IFORM_VPSRAW_XMMdq_XMMdq_IMMb 
XED_IFORM_VPSRAW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSRAW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 
XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 
XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb 
XED_IFORM_VPSRAW_YMMqq_YMMqq_MEMdq 
XED_IFORM_VPSRAW_YMMqq_YMMqq_XMMq 
XED_IFORM_VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 
XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 
XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 
XED_IFORM_VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 
XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 
XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 
XED_IFORM_VPSRLD_XMMdq_XMMdq_IMMb 
XED_IFORM_VPSRLD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSRLD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 
XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 
XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb 
XED_IFORM_VPSRLD_YMMqq_YMMqq_MEMdq 
XED_IFORM_VPSRLD_YMMqq_YMMqq_XMMq 
XED_IFORM_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 
XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 
XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 
XED_IFORM_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 
XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 
XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 
XED_IFORM_VPSRLDQ_XMMdq_XMMdq_IMMb 
XED_IFORM_VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512 
XED_IFORM_VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512 
XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb 
XED_IFORM_VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512 
XED_IFORM_VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512 
XED_IFORM_VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512 
XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512 
XED_IFORM_VPSRLQ_XMMdq_XMMdq_IMMb 
XED_IFORM_VPSRLQ_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSRLQ_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 
XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 
XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb 
XED_IFORM_VPSRLQ_YMMqq_YMMqq_MEMdq 
XED_IFORM_VPSRLQ_YMMqq_YMMqq_XMMq 
XED_IFORM_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 
XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 
XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 
XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 
XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 
XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 
XED_IFORM_VPSRLVD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSRLVD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VPSRLVD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPSRLVD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VPSRLVQ_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSRLVQ_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPSRLVQ_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPSRLVQ_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 
XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 
XED_IFORM_VPSRLW_XMMdq_XMMdq_IMMb 
XED_IFORM_VPSRLW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSRLW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 
XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 
XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb 
XED_IFORM_VPSRLW_YMMqq_YMMqq_MEMdq 
XED_IFORM_VPSRLW_YMMqq_YMMqq_XMMq 
XED_IFORM_VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 
XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 
XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 
XED_IFORM_VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 
XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 
XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 
XED_IFORM_VPSUBB_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSUBB_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 
XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 
XED_IFORM_VPSUBB_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPSUBB_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 
XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 
XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 
XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 
XED_IFORM_VPSUBD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSUBD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VPSUBD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPSUBD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VPSUBQ_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSUBQ_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPSUBQ_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPSUBQ_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VPSUBSB_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSUBSB_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 
XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 
XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 
XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 
XED_IFORM_VPSUBSB_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPSUBSB_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 
XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 
XED_IFORM_VPSUBSW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSUBSW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 
XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 
XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 
XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 
XED_IFORM_VPSUBSW_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPSUBSW_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 
XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 
XED_IFORM_VPSUBUSB_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSUBUSB_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 
XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 
XED_IFORM_VPSUBUSB_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPSUBUSB_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 
XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 
XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 
XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 
XED_IFORM_VPSUBUSW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSUBUSW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPSUBUSW_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPSUBUSW_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 
XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 
XED_IFORM_VPSUBW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPSUBW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPSUBW_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPSUBW_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 
XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 
XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 
XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 
XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 
XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 
XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 
XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 
XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 
XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 
XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 
XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 
XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 
XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 
XED_IFORM_VPTEST_XMMdq_MEMdq 
XED_IFORM_VPTEST_XMMdq_XMMdq 
XED_IFORM_VPTEST_YMMqq_MEMqq 
XED_IFORM_VPTEST_YMMqq_YMMqq 
XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 
XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 
XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 
XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 
XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 
XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 
XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 
XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 
XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 
XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 
XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 
XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 
XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 
XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 
XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 
XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 
XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 
XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 
XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 
XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 
XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 
XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 
XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 
XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 
XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 
XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 
XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 
XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 
XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 
XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 
XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 
XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 
XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 
XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 
XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 
XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 
XED_IFORM_VPXOR_XMMdq_XMMdq_MEMdq 
XED_IFORM_VPXOR_XMMdq_XMMdq_XMMdq 
XED_IFORM_VPXOR_YMMqq_YMMqq_MEMqq 
XED_IFORM_VPXOR_YMMqq_YMMqq_YMMqq 
XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 
XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 
XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 
XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 
XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 
XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 
XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 
XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 
XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 
XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 
XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 
XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 
XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 
XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 
XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 
XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 
XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512 
XED_IFORM_VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512 
XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 
XED_IFORM_VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512 
XED_IFORM_VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512 
XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 
XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER 
XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER 
XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER 
XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER 
XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER 
XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER 
XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER 
XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER 
XED_IFORM_VRCPBF16_XMMbf16_MASKmskw_MEMbf16_AVX512 
XED_IFORM_VRCPBF16_XMMbf16_MASKmskw_XMMbf16_AVX512 
XED_IFORM_VRCPBF16_YMMbf16_MASKmskw_MEMbf16_AVX512 
XED_IFORM_VRCPBF16_YMMbf16_MASKmskw_YMMbf16_AVX512 
XED_IFORM_VRCPBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512 
XED_IFORM_VRCPBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512 
XED_IFORM_VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512 
XED_IFORM_VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512 
XED_IFORM_VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512 
XED_IFORM_VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512 
XED_IFORM_VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512 
XED_IFORM_VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512 
XED_IFORM_VRCPPS_XMMdq_MEMdq 
XED_IFORM_VRCPPS_XMMdq_XMMdq 
XED_IFORM_VRCPPS_YMMqq_MEMqq 
XED_IFORM_VRCPPS_YMMqq_YMMqq 
XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VRCPSS_XMMdq_XMMdq_MEMd 
XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd 
XED_IFORM_VREDUCEBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512 
XED_IFORM_VREDUCEBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512 
XED_IFORM_VREDUCEBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512 
XED_IFORM_VREDUCEBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512 
XED_IFORM_VREDUCEBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512 
XED_IFORM_VREDUCEBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512 
XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 
XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 
XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 
XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 
XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 
XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 
XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 
XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 
XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 
XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 
XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 
XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 
XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 
XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 
XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 
XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 
XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 
XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 
XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 
XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 
XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 
XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 
XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 
XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 
XED_IFORM_VRNDSCALEBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512 
XED_IFORM_VRNDSCALEBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512 
XED_IFORM_VRNDSCALEBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512 
XED_IFORM_VRNDSCALEBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512 
XED_IFORM_VRNDSCALEBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512 
XED_IFORM_VRNDSCALEBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512 
XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 
XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 
XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 
XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 
XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 
XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 
XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 
XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 
XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 
XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 
XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 
XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 
XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 
XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 
XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 
XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 
XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 
XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 
XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 
XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 
XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 
XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 
XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 
XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 
XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb 
XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb 
XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb 
XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb 
XED_IFORM_VROUNDPS_XMMdq_MEMdq_IMMb 
XED_IFORM_VROUNDPS_XMMdq_XMMdq_IMMb 
XED_IFORM_VROUNDPS_YMMqq_MEMqq_IMMb 
XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb 
XED_IFORM_VROUNDSD_XMMdq_XMMdq_MEMq_IMMb 
XED_IFORM_VROUNDSD_XMMdq_XMMdq_XMMq_IMMb 
XED_IFORM_VROUNDSS_XMMdq_XMMdq_MEMd_IMMb 
XED_IFORM_VROUNDSS_XMMdq_XMMdq_XMMd_IMMb 
XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512 
XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512 
XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 
XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512 
XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512 
XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 
XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER 
XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER 
XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER 
XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER 
XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER 
XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER 
XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER 
XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER 
XED_IFORM_VRSQRTBF16_XMMbf16_MASKmskw_MEMbf16_AVX512 
XED_IFORM_VRSQRTBF16_XMMbf16_MASKmskw_XMMbf16_AVX512 
XED_IFORM_VRSQRTBF16_YMMbf16_MASKmskw_MEMbf16_AVX512 
XED_IFORM_VRSQRTBF16_YMMbf16_MASKmskw_YMMbf16_AVX512 
XED_IFORM_VRSQRTBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512 
XED_IFORM_VRSQRTBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512 
XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512 
XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512 
XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512 
XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512 
XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512 
XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512 
XED_IFORM_VRSQRTPS_XMMdq_MEMdq 
XED_IFORM_VRSQRTPS_XMMdq_XMMdq 
XED_IFORM_VRSQRTPS_YMMqq_MEMqq 
XED_IFORM_VRSQRTPS_YMMqq_YMMqq 
XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VRSQRTSS_XMMdq_XMMdq_MEMd 
XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd 
XED_IFORM_VSCALEFBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 
XED_IFORM_VSCALEFBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 
XED_IFORM_VSCALEFBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 
XED_IFORM_VSCALEFBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 
XED_IFORM_VSCALEFBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 
XED_IFORM_VSCALEFBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 
XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 
XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 
XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 
XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 
XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256 
XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512 
XED_IFORM_VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 
XED_IFORM_VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 
XED_IFORM_VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 
XED_IFORM_VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 
XED_IFORM_VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 
XED_IFORM_VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 
XED_IFORM_VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 
XED_IFORM_VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 
XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 
XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 
XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 
XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 
XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256 
XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512 
XED_IFORM_VSHA512MSG1_YMMu64_XMMu64 
XED_IFORM_VSHA512MSG2_YMMu64_YMMu64 
XED_IFORM_VSHA512RNDS2_YMMu64_YMMu64_XMMu64 
XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 
XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 
XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 
XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 
XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 
XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 
XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 
XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 
XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 
XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 
XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 
XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 
XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 
XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 
XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 
XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 
XED_IFORM_VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb 
XED_IFORM_VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb 
XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 
XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 
XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 
XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 
XED_IFORM_VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb 
XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb 
XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 
XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 
XED_IFORM_VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb 
XED_IFORM_VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb 
XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 
XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 
XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 
XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 
XED_IFORM_VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb 
XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb 
XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 
XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 
XED_IFORM_VSM3MSG1_XMMu32_XMMu32_MEMu32 
XED_IFORM_VSM3MSG1_XMMu32_XMMu32_XMMu32 
XED_IFORM_VSM3MSG2_XMMu32_XMMu32_MEMu32 
XED_IFORM_VSM3MSG2_XMMu32_XMMu32_XMMu32 
XED_IFORM_VSM3RNDS2_XMMu32_XMMu32_MEMu32_IMM8 
XED_IFORM_VSM3RNDS2_XMMu32_XMMu32_XMMu32_IMM8 
XED_IFORM_VSM4KEY4_XMMu32_XMMu32_MEMu32 
XED_IFORM_VSM4KEY4_XMMu32_XMMu32_MEMu32_AVX512 
XED_IFORM_VSM4KEY4_XMMu32_XMMu32_XMMu32 
XED_IFORM_VSM4KEY4_XMMu32_XMMu32_XMMu32_AVX512 
XED_IFORM_VSM4KEY4_YMMu32_YMMu32_MEMu32 
XED_IFORM_VSM4KEY4_YMMu32_YMMu32_MEMu32_AVX512 
XED_IFORM_VSM4KEY4_YMMu32_YMMu32_YMMu32 
XED_IFORM_VSM4KEY4_YMMu32_YMMu32_YMMu32_AVX512 
XED_IFORM_VSM4KEY4_ZMMu32_ZMMu32_MEMu32_AVX512 
XED_IFORM_VSM4KEY4_ZMMu32_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_MEMu32 
XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_MEMu32_AVX512 
XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_XMMu32 
XED_IFORM_VSM4RNDS4_XMMu32_XMMu32_XMMu32_AVX512 
XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_MEMu32 
XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_MEMu32_AVX512 
XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_YMMu32 
XED_IFORM_VSM4RNDS4_YMMu32_YMMu32_YMMu32_AVX512 
XED_IFORM_VSM4RNDS4_ZMMu32_ZMMu32_MEMu32_AVX512 
XED_IFORM_VSM4RNDS4_ZMMu32_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VSQRTBF16_XMMbf16_MASKmskw_MEMbf16_AVX512 
XED_IFORM_VSQRTBF16_XMMbf16_MASKmskw_XMMbf16_AVX512 
XED_IFORM_VSQRTBF16_YMMbf16_MASKmskw_MEMbf16_AVX512 
XED_IFORM_VSQRTBF16_YMMbf16_MASKmskw_YMMbf16_AVX512 
XED_IFORM_VSQRTBF16_ZMMbf16_MASKmskw_MEMbf16_AVX512 
XED_IFORM_VSQRTBF16_ZMMbf16_MASKmskw_ZMMbf16_AVX512 
XED_IFORM_VSQRTPD_XMMdq_MEMdq 
XED_IFORM_VSQRTPD_XMMdq_XMMdq 
XED_IFORM_VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512 
XED_IFORM_VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512 
XED_IFORM_VSQRTPD_YMMqq_MEMqq 
XED_IFORM_VSQRTPD_YMMqq_YMMqq 
XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512 
XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512 
XED_IFORM_VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512 
XED_IFORM_VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512 
XED_IFORM_VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512 
XED_IFORM_VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512 
XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512 
XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512 
XED_IFORM_VSQRTPS_XMMdq_MEMdq 
XED_IFORM_VSQRTPS_XMMdq_XMMdq 
XED_IFORM_VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512 
XED_IFORM_VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512 
XED_IFORM_VSQRTPS_YMMqq_MEMqq 
XED_IFORM_VSQRTPS_YMMqq_YMMqq 
XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512 
XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512 
XED_IFORM_VSQRTSD_XMMdq_XMMdq_MEMq 
XED_IFORM_VSQRTSD_XMMdq_XMMdq_XMMq 
XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd 
XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd 
XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VSTMXCSR_MEMd 
XED_IFORM_VSUBBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_AVX512 
XED_IFORM_VSUBBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_AVX512 
XED_IFORM_VSUBBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_AVX512 
XED_IFORM_VSUBBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_AVX512 
XED_IFORM_VSUBBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_AVX512 
XED_IFORM_VSUBBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_AVX512 
XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 
XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 
XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 
XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 
XED_IFORM_VSUBPS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VSUBPS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VSUBSD_XMMdq_XMMdq_MEMq 
XED_IFORM_VSUBSD_XMMdq_XMMdq_XMMq 
XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 
XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 
XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd 
XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd 
XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VTESTPD_XMMdq_MEMdq 
XED_IFORM_VTESTPD_XMMdq_XMMdq 
XED_IFORM_VTESTPD_YMMqq_MEMqq 
XED_IFORM_VTESTPD_YMMqq_YMMqq 
XED_IFORM_VTESTPS_XMMdq_MEMdq 
XED_IFORM_VTESTPS_XMMdq_XMMdq 
XED_IFORM_VTESTPS_YMMqq_MEMqq 
XED_IFORM_VTESTPS_YMMqq_YMMqq 
XED_IFORM_VUCOMISD_XMMdq_MEMq 
XED_IFORM_VUCOMISD_XMMdq_XMMq 
XED_IFORM_VUCOMISD_XMMf64_MEMf64_AVX512 
XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512 
XED_IFORM_VUCOMISH_XMMf16_MEMf16_AVX512 
XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512 
XED_IFORM_VUCOMISS_XMMdq_MEMd 
XED_IFORM_VUCOMISS_XMMdq_XMMd 
XED_IFORM_VUCOMISS_XMMf32_MEMf32_AVX512 
XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512 
XED_IFORM_VUCOMXSD_XMMf64_MEMf64_AVX512 
XED_IFORM_VUCOMXSD_XMMf64_XMMf64_AVX512 
XED_IFORM_VUCOMXSH_XMMf16_MEMf16_AVX512 
XED_IFORM_VUCOMXSH_XMMf16_XMMf16_AVX512 
XED_IFORM_VUCOMXSS_XMMf32_MEMf32_AVX512 
XED_IFORM_VUCOMXSS_XMMf32_XMMf32_AVX512 
XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 
XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 
XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 
XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 
XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 
XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 
XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 
XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 
XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 
XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 
XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 
XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 
XED_IFORM_VXORPD_XMMdq_XMMdq_MEMdq 
XED_IFORM_VXORPD_XMMdq_XMMdq_XMMdq 
XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 
XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 
XED_IFORM_VXORPD_YMMqq_YMMqq_MEMqq 
XED_IFORM_VXORPD_YMMqq_YMMqq_YMMqq 
XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 
XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 
XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 
XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 
XED_IFORM_VXORPS_XMMdq_XMMdq_MEMdq 
XED_IFORM_VXORPS_XMMdq_XMMdq_XMMdq 
XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 
XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 
XED_IFORM_VXORPS_YMMqq_YMMqq_MEMqq 
XED_IFORM_VXORPS_YMMqq_YMMqq_YMMqq 
XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 
XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 
XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 
XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 
XED_IFORM_VZEROALL 
XED_IFORM_VZEROUPPER 
XED_IFORM_WBINVD 
XED_IFORM_WBNOINVD 
XED_IFORM_WRFSBASE_GPRy 
XED_IFORM_WRGSBASE_GPRy 
XED_IFORM_WRMSR 
XED_IFORM_WRMSRLIST 
XED_IFORM_WRMSRNS 
XED_IFORM_WRMSRNS_IMM32_GPR64u64 
XED_IFORM_WRMSRNS_IMM32_GPR64u64_APX 
XED_IFORM_WRPKRU 
XED_IFORM_WRSSD_MEMu32_GPR32u32 
XED_IFORM_WRSSD_MEMu32_GPR32u32_APX 
XED_IFORM_WRSSQ_MEMu64_GPR64u64 
XED_IFORM_WRSSQ_MEMu64_GPR64u64_APX 
XED_IFORM_WRUSSD_MEMu32_GPR32u32 
XED_IFORM_WRUSSD_MEMu32_GPR32u32_APX 
XED_IFORM_WRUSSQ_MEMu64_GPR64u64 
XED_IFORM_WRUSSQ_MEMu64_GPR64u64_APX 
XED_IFORM_XABORT_IMMb 
XED_IFORM_XADD_GPR8_GPR8 
XED_IFORM_XADD_GPRv_GPRv 
XED_IFORM_XADD_MEMb_GPR8 
XED_IFORM_XADD_MEMv_GPRv 
XED_IFORM_XADD_LOCK_MEMb_GPR8 
XED_IFORM_XADD_LOCK_MEMv_GPRv 
XED_IFORM_XBEGIN_RELBRz 
XED_IFORM_XCHG_GPR8_GPR8 
XED_IFORM_XCHG_GPRv_GPRv 
XED_IFORM_XCHG_GPRv_OrAX 
XED_IFORM_XCHG_MEMb_GPR8 
XED_IFORM_XCHG_MEMv_GPRv 
XED_IFORM_XEND 
XED_IFORM_XGETBV 
XED_IFORM_XLAT 
XED_IFORM_XOR_AL_IMMb 
XED_IFORM_XOR_GPR8_GPR8_30 
XED_IFORM_XOR_GPR8_GPR8_32 
XED_IFORM_XOR_GPR8_IMMb_80r6 
XED_IFORM_XOR_GPR8_IMMb_82r6 
XED_IFORM_XOR_GPR8_MEMb 
XED_IFORM_XOR_GPR8i8_GPR8i8_APX 
XED_IFORM_XOR_GPR8i8_GPR8i8_GPR8i8_APX 
XED_IFORM_XOR_GPR8i8_GPR8i8_IMM8_APX 
XED_IFORM_XOR_GPR8i8_GPR8i8_MEMi8_APX 
XED_IFORM_XOR_GPR8i8_IMM8_APX 
XED_IFORM_XOR_GPR8i8_MEMi8_APX 
XED_IFORM_XOR_GPR8i8_MEMi8_GPR8i8_APX 
XED_IFORM_XOR_GPR8i8_MEMi8_IMM8_APX 
XED_IFORM_XOR_GPRv_GPRv_31 
XED_IFORM_XOR_GPRv_GPRv_33 
XED_IFORM_XOR_GPRv_GPRv_APX 
XED_IFORM_XOR_GPRv_GPRv_GPRv_APX 
XED_IFORM_XOR_GPRv_GPRv_IMM8_APX 
XED_IFORM_XOR_GPRv_GPRv_IMMz_APX 
XED_IFORM_XOR_GPRv_GPRv_MEMv_APX 
XED_IFORM_XOR_GPRv_IMM8_APX 
XED_IFORM_XOR_GPRv_IMMb 
XED_IFORM_XOR_GPRv_IMMz 
XED_IFORM_XOR_GPRv_IMMz_APX 
XED_IFORM_XOR_GPRv_MEMv 
XED_IFORM_XOR_GPRv_MEMv_APX 
XED_IFORM_XOR_GPRv_MEMv_GPRv_APX 
XED_IFORM_XOR_GPRv_MEMv_IMM8_APX 
XED_IFORM_XOR_GPRv_MEMv_IMMz_APX 
XED_IFORM_XOR_MEMb_GPR8 
XED_IFORM_XOR_MEMb_IMMb_80r6 
XED_IFORM_XOR_MEMb_IMMb_82r6 
XED_IFORM_XOR_MEMi8_GPR8i8_APX 
XED_IFORM_XOR_MEMi8_IMM8_APX 
XED_IFORM_XOR_MEMv_GPRv 
XED_IFORM_XOR_MEMv_GPRv_APX 
XED_IFORM_XOR_MEMv_IMM8_APX 
XED_IFORM_XOR_MEMv_IMMb 
XED_IFORM_XOR_MEMv_IMMz 
XED_IFORM_XOR_MEMv_IMMz_APX 
XED_IFORM_XOR_OrAX_IMMz 
XED_IFORM_XORPD_XMMxuq_MEMxuq 
XED_IFORM_XORPD_XMMxuq_XMMxuq 
XED_IFORM_XORPS_XMMxud_MEMxud 
XED_IFORM_XORPS_XMMxud_XMMxud 
XED_IFORM_XOR_LOCK_MEMb_GPR8 
XED_IFORM_XOR_LOCK_MEMb_IMMb_80r6 
XED_IFORM_XOR_LOCK_MEMb_IMMb_82r6 
XED_IFORM_XOR_LOCK_MEMv_GPRv 
XED_IFORM_XOR_LOCK_MEMv_IMMb 
XED_IFORM_XOR_LOCK_MEMv_IMMz 
XED_IFORM_XRESLDTRK 
XED_IFORM_XRSTOR_MEMmxsave 
XED_IFORM_XRSTOR64_MEMmxsave 
XED_IFORM_XRSTORS_MEMmxsave 
XED_IFORM_XRSTORS64_MEMmxsave 
XED_IFORM_XSAVE_MEMmxsave 
XED_IFORM_XSAVE64_MEMmxsave 
XED_IFORM_XSAVEC_MEMmxsave 
XED_IFORM_XSAVEC64_MEMmxsave 
XED_IFORM_XSAVEOPT_MEMmxsave 
XED_IFORM_XSAVEOPT64_MEMmxsave 
XED_IFORM_XSAVES_MEMmxsave 
XED_IFORM_XSAVES64_MEMmxsave 
XED_IFORM_XSETBV 
XED_IFORM_XSTORE 
XED_IFORM_XSUSLDTRK 
XED_IFORM_XTEST 
XED_IFORM_LAST